diff options
10 files changed, 251 insertions, 25 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H index bca108fd..5c495e8f 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -399,7 +399,6 @@ HCD_CONST(CPMR_DEBUG_REGION_OFFSET, CPMR_TRACE_REGION_OFFSET + CPMR_ HCD_CONST(CPMR_DEBUG_REGION_SIZE, (64 * ONE_KB)) // 192K + 64K = 256K - //--------------------------------------------------------------------------------------- /// PPMR Header diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H index 1a1a2953..a04e3ab0 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H @@ -70,7 +70,6 @@ HCD_CONST(HOMER_CPMR_TRACE_ADDR, (HOMER_CPMR_BASE_ADDR + CPMR_TRACE_RE HCD_CONST(HOMER_CPMR_DEBUG_ADDR, (HOMER_CPMR_BASE_ADDR + CPMR_DEBUG_REGION_OFFSET)) - /// PPMR HCD_CONST(HOMER_PPMR_BASE_ADDR, (HOMER_BASE_ADDR + (PPMR_HOMER_OFFSET))) diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c index d78513f0..a0edef2e 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c @@ -251,20 +251,17 @@ main(int argc, char** argv) #if TEST_ONLY_BCE_IRR - if ((G_bce_irr.enable = in32(CME_LCL_FLAGS) & FLAG_BCE_IRR_ENABLE)) - { - // Initialize thread control blocks for the threads - pk_thread_create( &G_p9_cme_bce_irr_thread, - (PkThreadRoutine)bce_irr_run, - (void*)NULL, - (PkAddress)G_p9_cme_bce_irr_thread_stack, - (size_t)CME_THREAD_STACK_SIZE_BCE_IRR, - (PkThreadPriority)CME_THREAD_PRIORITY_BCE_IRR); - - PK_TRACE_BIN("G_p9_cme_bce_irr_thread", - &G_p9_cme_bce_irr_thread, - sizeof(G_p9_cme_bce_irr_thread)); - } + // Initialize thread control blocks for the threads + pk_thread_create( &G_p9_cme_bce_irr_thread, + (PkThreadRoutine)bce_irr_thread, + (void*)NULL, + (PkAddress)G_p9_cme_bce_irr_thread_stack, + (size_t)CME_THREAD_STACK_SIZE_BCE_IRR, + (PkThreadPriority)CME_THREAD_PRIORITY_BCE_IRR); + + PK_TRACE_BIN("G_p9_cme_bce_irr_thread", + &G_p9_cme_bce_irr_thread, + sizeof(G_p9_cme_bce_irr_thread)); #endif @@ -282,11 +279,8 @@ main(int argc, char** argv) #if TEST_ONLY_BCE_IRR - if (G_bce_irr.enable) - { - // Make G_p9_cme_bce_irr_thread runnable - pk_thread_resume(&G_p9_cme_bce_irr_thread); - } + // Make G_p9_cme_bce_irr_thread runnable + pk_thread_resume(&G_p9_cme_bce_irr_thread); #endif diff --git a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h index ccdf0b5d..c5d145ef 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h +++ b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h @@ -34,7 +34,12 @@ /// \brief Application specific overrides go here. /// +// debug only enablement + #define DEBUG_RUNTIME_STATE_CHECK 0 +#define TEST_ONLY_BCE_IRR 0 + +// -------------------- #define USE_PPE_IMPRECISE_MODE #define USE_CME_QUEUED_SCOM diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c index 0cbd3676..4aa129f2 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c @@ -23,6 +23,8 @@ /* */ /* IBM_PROLOG_END_TAG */ + + #include "p9_cme_copy_scan_ring.h" #include "p9_cme_stop.h" @@ -34,9 +36,208 @@ enum COPY_DEF_CME_ADDR = 0x00000000, CME_PAGE_RD_SIZE = 0x20, CME_FLAG_EX_ID_BIT = 26, - EX_ID_SHIFT_POS = 5, + EX_ID_SHIFT_POS = 5 }; + + +#if TEST_ONLY_BCE_IRR +extern BceIrritator G_bce_irr; + +#define RAND32_ALL 0 +uint32_t _seed32 = 405405405; + +uint32_t +_rand32(uint32_t* seed, uint32_t limit) +{ + uint64_t x; + + *seed = (*seed * 1664525) + 1013904223; + + if (limit == RAND32_ALL) + { + return *seed; + } + else + { + x = (uint64_t)(*seed) * limit; + return x >> 32; + } +} + +uint32_t +rand32(uint32_t limit) +{ + return _rand32(&_seed32, limit); +} + +void bce_irr_setup() +{ + BceReturnCode_t l_rc; + uint32_t l_cmePir = 0; + uint32_t l_exId = (in32(CME_LCL_FLAGS) & BIT32(26)) >> SHIFT32(26); + asm volatile ( "mfspr %0, %1 \n\t" : "=r" (l_cmePir) : "i" (SPR_NUM_PIR)); + + //CME's PIR gives only quad id. To determine the correct CME instance, follow the steps below: + //(1). Read CME PIR's CME instance bit field (bit 27 -bit 31) + //(2). Bitwise shift left by one bit position. + //(3). OR to LSB of CME PIR (bit 31), bit 26 of CME Flag Register + G_bce_irr.cmeid = (((l_cmePir << 1) & CME_INST_ID_MASK) | l_exId); // get CME instance number + G_bce_irr.mbase = CPMR_DEBUG_REGION_OFFSET + (G_bce_irr.cmeid << 3); //8B for each CME + G_bce_irr.sbase = 0xFFFFFFF0; // use 8B at the end of CME SRAM + + startCmeBlockCopy(G_bce_irr.sbase, 1, G_bce_irr.cmeid, BAR_INDEX_1, G_bce_irr.mbase); + + while(1) + { + l_rc = checkCmeBlockCopyStatus( G_bce_irr.cmeid ); + + if( BLOCK_COPY_SUCCESS == l_rc ) + { + break; + } + + if( BLOCK_COPY_FAILED == l_rc ) + { + PK_TRACE( "failed to read bce irritator data on cme %d", + G_bce_irr.cmeid ); + pk_halt(); + } + } + + G_bce_irr.data.word = in32(G_bce_irr.sbase); + G_bce_irr.data.word++; + out32(G_bce_irr.sbase, G_bce_irr.data.word); + + startCmeBlockCopyWriteHomer(G_bce_irr.sbase, 4, G_bce_irr.cmeid, BAR_INDEX_1, G_bce_irr.mbase); + + while(1) + { + l_rc = checkCmeBlockCopyStatus( G_bce_irr.cmeid ); + + if( BLOCK_COPY_SUCCESS == l_rc ) + { + break; + } + + if( BLOCK_COPY_FAILED == l_rc ) + { + PK_TRACE( "failed to write bce irritator data on cme %d", + G_bce_irr.cmeid ); + pk_halt(); + } + } +} + +void bce_irr_run() +{ + BceReturnCode_t l_rc; + uint32_t l_data32 = 0; + + if (rand32(1000) > 500) + { + return; + } + + while(1) + { + l_rc = checkCmeBlockCopyStatus( G_bce_irr.cmeid ); + + if( BLOCK_COPY_SUCCESS == l_rc ) + { + break; + } + + if( BLOCK_COPY_FAILED == l_rc ) + { + PK_TRACE( "failed to read bce irritator data on cme %d", + G_bce_irr.cmeid ); + pk_halt(); + } + } + + startCmeBlockCopy(G_bce_irr.sbase, 1, G_bce_irr.cmeid, BAR_INDEX_1, G_bce_irr.mbase); + + while(1) + { + l_rc = checkCmeBlockCopyStatus( G_bce_irr.cmeid ); + + if( BLOCK_COPY_SUCCESS == l_rc ) + { + break; + } + + if( BLOCK_COPY_FAILED == l_rc ) + { + PK_TRACE( "failed to read bce irritator data on cme %d", + G_bce_irr.cmeid ); + pk_halt(); + } + } + + l_data32 = in32(G_bce_irr.sbase); + + if (l_data32 != G_bce_irr.data.word) + { + PKTRACE("miscompare between bce irr read[%x] and cme shadow copy[%x]", + l_data32, G_bce_irr.data.word); + pk_halt(); + } + + G_bce_irr.data.word++; + out32(G_bce_irr.sbase, G_bce_irr.data.word); + + while(1) + { + l_rc = checkCmeBlockCopyStatus( G_bce_irr.cmeid ); + + if( BLOCK_COPY_SUCCESS == l_rc ) + { + break; + } + + if( BLOCK_COPY_FAILED == l_rc ) + { + PK_TRACE( "failed to write bce irritator data on cme %d", + G_bce_irr.cmeid ); + pk_halt(); + } + } + + startCmeBlockCopyWriteHomer(G_bce_irr.sbase, 4, G_bce_irr.cmeid, BAR_INDEX_1, G_bce_irr.mbase); + + while(1) + { + l_rc = checkCmeBlockCopyStatus( G_bce_irr.cmeid ); + + if( BLOCK_COPY_SUCCESS == l_rc ) + { + break; + } + + if( BLOCK_COPY_FAILED == l_rc ) + { + PK_TRACE( "failed to write bce irritator data on cme %d", + G_bce_irr.cmeid ); + pk_halt(); + } + } +} + +void bce_irr_thread(void* args) +{ + while(1) + { + wrteei(0); + bce_irr_run(); + wrteei(1); + } +} + +#endif + + + void instance_scan_init( ) { uint32_t l_cmePir = 0; diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.h index 4faf7664..0c47471a 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.h @@ -52,4 +52,11 @@ void instance_scan_init(); /// @retval BLOCK_COPY_SUCCESS if function succeeds else error code. /// @note function call is blocking BceReturnCode_t isScanRingCopyDone(); + +#if TEST_ONLY_BCE_IRR + void bce_irr_setup(); + void bce_irr_run(); + void bce_irr_thread(void*); +#endif + #endif diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h index c8974f04..11719101 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h @@ -200,7 +200,6 @@ enum CME_STOP_FLAGS FLAG_STOP_READY = BIT32(0), FLAG_BLOCK_WKUP_C0 = BIT32(8), FLAG_BLOCK_WKUP_C1 = BIT32(9), - FLAG_BCE_IRR_ENABLE = BIT32(25), FLAG_EX1_INDICATOR = BIT32(26), FLAG_ENTRY_FIRST_C0 = BIT32(28), FLAG_ENTRY_FIRST_C1 = BIT32(29), @@ -250,7 +249,6 @@ typedef struct uint32_t word; uint8_t byte[4]; } data; - uint8_t enable; } BceIrritator; #endif diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c index 09a8a4de..5ac7d97e 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c @@ -927,6 +927,9 @@ p9_cme_stop_exit() CME_PUTSCOM(SPATTN_MASK, core, BITS64(0, 64)); PK_TRACE_INF("SF.RS: Self Restore Kickoff, S-Reset All Core Threads"); + + // Disable interrupts around the sreset to polling check to not miss the self-restore + wrteei(0); CME_PUTSCOM(DIRECT_CONTROLS, core, BIT64(4) | BIT64(12) | BIT64(20) | BIT64(28)); sync(); @@ -935,6 +938,7 @@ p9_cme_stop_exit() while((~(in32_sh(CME_LCL_SISR))) & (core << SHIFT64SH(47))); + wrteei(1); //========================== MARK_TRAP(SX_SRESET_THREADS) diff --git a/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.c b/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.c index f66ecd39..303371e4 100644 --- a/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.c +++ b/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.c @@ -43,9 +43,25 @@ #include "cme_register_addresses.h" - //------------------------------------------------------------------------------------ +void startCmeBlockCopyWriteHomer(uint64_t i_cmeStartBlk, uint32_t i_blockLength, uint32_t i_cmePos, + uint8_t i_barIndex, uint32_t i_mbaseVal) +{ + uint64_t l_bceStatusData = ((START_BLOCK_COPY) | // starts block copy operation + (0) | // sets direction of copy CME SRAM to HOMER + ((i_barIndex == 0) ? SEL_BCEBAR0 : SEL_BCEBAR1) | // BAR register to be used for accessing main memory base + (SET_RD_PRIORITY_0) | // No priority set + ((i_cmeStartBlk & 0x0000FFF ) << SBASE_SHIFT_POS) | //copy page to this SRAM Block. + (((uint64_t) i_blockLength & 0x00007FF) << NUM_BLK_SHIFT_POS ) | // number of blocks to be copied + (((uint64_t) i_mbaseVal & 0x00000000003FFFFF) )); + + // for CME platform use local address for register BCECSR. + // using BCECSR SCOM address will not work as it is meant + // for entities external to CME. + out64(CME_LCL_BCECSR, l_bceStatusData); +} + void startCmeBlockCopy( uint64_t i_cmeStartBlk, uint32_t i_blockLength, uint32_t i_cmePos, uint8_t i_barIndex, uint32_t i_mbaseVal ) { diff --git a/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.h b/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.h index cf78689e..3aff625c 100644 --- a/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.h +++ b/import/chips/p9/procedures/ppe_closed/lib/p9_hcd_block_copy.h @@ -75,6 +75,9 @@ enum void startCmeBlockCopy( uint64_t i_cmeStartBlk, uint32_t i_blockLength, uint32_t i_cmePos, uint8_t i_barIndex, uint32_t i_mbaseVal ); +void startCmeBlockCopyWriteHomer( uint64_t i_cmeStartBlk, uint32_t i_blockLength, + uint32_t i_cmePos, uint8_t i_barIndex, uint32_t i_mbaseVal); + /// @brief accomplishes block copy from mainstore to CME SRAM. /// @param [in] i_cmePos Position of CME in the P9 chip. /// @param [in] i_plat platform requesting block copy transfer. |
