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-rw-r--r--import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c31
-rw-r--r--import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c94
2 files changed, 32 insertions, 93 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
index 2e08c55f..9f926dce 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
@@ -47,22 +47,18 @@ extern CmeRecord G_cme_record;
//
//InterCME_IN0 handler
//
-void p9_cme_pstate_intercme_in0_irq_handler(void* arg, PkIrqId irq)
+void p9_cme_pstate_intercme_in0_irq_handler(void)
{
- PkMachineContext ctx __attribute__((unused));
p9_cme_pstate_process_db0_sibling();
- pk_irq_vec_restore(&ctx);
}
-void p9_cme_pstate_intercme_msg_handler(void* arg, PkIrqId irq)
+void p9_cme_pstate_intercme_msg_handler(void)
{
- PkMachineContext ctx __attribute__((unused));
p9_cme_pstate_sibling_lock_and_intercme_protocol(0);
- pk_irq_vec_restore(&ctx);
}
void p9_cme_pstate_sibling_lock_and_intercme_protocol(uint32_t process_intercme_in0)
@@ -79,7 +75,7 @@ void p9_cme_pstate_sibling_lock_and_intercme_protocol(uint32_t process_intercme_
if(in32_sh(CME_LCL_EISR) & BIT64SH(38))
{
G_cme_pstate_record.pstatesSuspended = 1;
- p9_cme_pstate_pmsr_updt(G_cme_record.core_enabled);
+ p9_cme_pstate_pmsr_updt();
intercme_direct(INTERCME_DIRECT_IN1, INTERCME_DIRECT_ACK, 0);
}
@@ -99,14 +95,7 @@ void p9_cme_pstate_process_db0_sibling()
//Read DB0 from first good core since PGPE
//writes same value for both cores
- if (in32(CME_LCL_FLAGS) & (BIT32(CME_FLAGS_CORE0_GOOD)))
- {
- CME_GETSCOM(CPPM_CMEDB0, CME_MASK_C0, dbData.value);
- }
- else
- {
- CME_GETSCOM(CPPM_CMEDB0, CME_MASK_C1, dbData.value);
- }
+ CME_GETSCOM(CPPM_CMEDB0, G_cme_pstate_record.firstGoodCoreMask, dbData.value);
PK_TRACE("INTER0: Enter\n");
@@ -122,7 +111,7 @@ void p9_cme_pstate_process_db0_sibling()
G_cme_pstate_record.quadPstate = dbQuadInfo;
G_cme_pstate_record.globalPstate = dbBit8_15;
- p9_cme_pstate_pmsr_updt(G_cme_record.core_enabled);
+ p9_cme_pstate_pmsr_updt();
//Clear any pending PMCR interrupts
g_eimr_override |= BITS64(34, 2);
@@ -137,7 +126,7 @@ void p9_cme_pstate_process_db0_sibling()
PK_TRACE("INTER0: DB0 GlbBcast");
G_cme_pstate_record.quadPstate = dbQuadInfo;
G_cme_pstate_record.globalPstate = dbBit8_15;
- p9_cme_pstate_pmsr_updt(G_cme_record.core_enabled);
+ p9_cme_pstate_pmsr_updt();
}
else if(dbData.fields.cme_message_number0 == MSGID_DB0_CLIP_BROADCAST)
{
@@ -152,7 +141,7 @@ void p9_cme_pstate_process_db0_sibling()
G_cme_pstate_record.pmax = dbQuadInfo;
}
- p9_cme_pstate_pmsr_updt(G_cme_record.core_enabled);
+ p9_cme_pstate_pmsr_updt();
}
else if(dbData.fields.cme_message_number0 == MSGID_DB0_STOP_PSTATE_BROADCAST)
{
@@ -162,7 +151,7 @@ void p9_cme_pstate_process_db0_sibling()
//PGPE will update the LMCR[0] before sending the STOP PSTATE Doorbell.
//Here we update the PMSR to indicate that Pstates are no longer honored accordingly.
- p9_cme_pstate_pmsr_updt(G_cme_record.core_enabled);
+ p9_cme_pstate_pmsr_updt();
//Set Core GPMMR RESET_STATE_INDICATOR bit to show pstates have stopped
CME_PUTSCOM(PPM_GPMMR_OR, G_cme_record.core_enabled, BIT64(15));
@@ -186,14 +175,14 @@ void p9_cme_pstate_process_db0_sibling()
break;
}
- p9_cme_pstate_pmsr_updt(G_cme_record.core_enabled);
+ p9_cme_pstate_pmsr_updt();
}
else
{
PK_PANIC(CME_PSTATE_INVALID_DB0_MSGID);
}
- out32_sh(CME_LCL_EISR_CLR, G_cme_record.core_enabled << SHIFT64SH(37));//Clear DB0_C0/C1
+ out32_sh(CME_LCL_EISR_CLR, BITS64SH(36, 2)); //Clear DB0_C0/C1
intercme_direct(INTERCME_DIRECT_IN0, INTERCME_DIRECT_ACK, 0);
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c
index 3b5aca35..fda77451 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_pmcr.c
@@ -47,93 +47,55 @@
//
//Globals
//
-cme_pstate_pmcr_data_t G_pmcr_thread_data;
extern CmePstateRecord G_cme_pstate_record;
-uint32_t G_pmcr_cme_flags;
void cme_pstate_pmcr_action()
{
PkMachineContext ctx __attribute__((unused));
- uint64_t pmcr;
ppm_pig_t ppmPigData;
- uint32_t eisr;
- static
- uint32_t coreMask[CORES_PER_EX] __attribute__((aligned(8))) =
- {
- CME_MASK_C0,
- CME_MASK_C1
- };
+ uint64_t request;
+ uint32_t eisr_mask, core, cm;
- int c;
+ //Determine which cores have pending request & clear interrupt
+ eisr_mask = in32_sh(CME_LCL_EISR) & BITS64SH(34, 2);
+ core = eisr_mask >> SHIFT64SH(35);
+ out32_sh(CME_LCL_EISR_CLR, eisr_mask);
- //Determine which core have pending request
- for(c = 0; c < CORES_PER_EX; c++)
+ //Read PMCR and send request to PGPE (Type1 only, previously sent 2 phases)
+ for(cm = 2; cm > 0; cm--)
{
- if (G_pmcr_cme_flags & (BIT32(CME_FLAGS_CORE0_GOOD) >> c))
+ if (core & cm)
{
- eisr = in32_sh(CME_LCL_EISR); //EISR
-
- if (eisr & (BIT32(2) >> c))
- {
- //Clear interrupt and read PMCR
- out32_sh(CME_LCL_EISR_CLR, BIT32(2) >> c);
- //We read the pmcr into a local variable, so that
- //both phases use the same PMCR value. Otherwise, it's possible
- //for pmcr to change between sending phase 1 and phase 2
- pmcr = in64(CME_LCL_PMCRS0 + (c << 5));
+ request = in64(CME_LCL_PMCRS0 + ((cm & 1) << 5)) & PMCR_LOWERPS_MASK;
+ PK_TRACE_INF("PMCR: Fwd Core[%d] Pstate Request = 0x%02x\n", cm, (uint32_t)(request >> PMCR_PSTATE_SHIFT_AMOUNT));
- //Send Phase 1
- ppmPigData.value = 0;
- ppmPigData.fields.req_intr_type = 0;
- ppmPigData.value |= ((pmcr & PIG_PAYLOAD_PS_PHASE1_MASK) >> 8);
- ppmPigData.value |= ((uint64_t)(G_pmcr_thread_data.seqNum & 0x6) << 57);
- send_pig_packet(ppmPigData.value, coreMask[c]);
- G_pmcr_thread_data.seqNum++;
+ // Note that LowerPS coincidentally is in the correct place for the PIG payload
- //Send Phase 2
- ppmPigData.value = 0;
- ppmPigData.fields.req_intr_type = 1;
- ppmPigData.value |= (pmcr & PIG_PAYLOAD_PS_PHASE2_MASK);
- ppmPigData.value |= ((uint64_t)(G_pmcr_thread_data.seqNum & 0x6) << 57);
- send_pig_packet(ppmPigData.value, coreMask[c]);
- G_pmcr_thread_data.seqNum++;
- PK_TRACE_INF("PMCR_TH: Fwd PMCR[%d]=0x%08x%08x\n", c, pmcr >> 32, pmcr);
- }
+ ppmPigData.value = 0;
+ ppmPigData.fields.req_intr_type = 1;
+ ppmPigData.value |= request;
+ send_pig_packet(ppmPigData.value, cm);
}
}
-
- pk_irq_vec_restore(&ctx);
}
//
//PMCR Interrupt Handler
//
-void p9_cme_pstate_pmcr_handler(void* arg, PkIrqId irq)
+void p9_cme_pstate_pmcr_handler(void)
{
-#if defined(__IOTA__)
wrteei(1);
cme_pstate_pmcr_action();
-#else
- pk_semaphore_post((PkSemaphore*)arg);
-#endif
}
//
-//p9_cme_pmcr_thread
+// Run this when all inits are done
//
-void p9_cme_pstate_pmcr_thread(void* arg)
+void p9_cme_init_done()
{
- PK_TRACE_INF("PMCR_TH: Enter\n");
+ PK_TRACE_INF("CME INIT DONE: Enter\n");
uint32_t msg;
- G_pmcr_thread_data.seqNum = 0; //Initialize seqNum to zero
-
- G_pmcr_cme_flags = in32(CME_LCL_FLAGS);;
-
-#if !defined(__IOTA__)
- pk_semaphore_create(&G_cme_pstate_record.sem[0], 0, 1);
-#endif
-
// Synchronization between QM and Sibling
// @todo RTC173279 move into CME init function
if(G_cme_pstate_record.qmFlag)
@@ -153,20 +115,8 @@ void p9_cme_pstate_pmcr_thread(void* arg)
// This is the current barrier for SGPE booting the CMEs, any and all
// initialization must be completed prior!
+// @todo RTC173279 rename this flag to CME_FLAGS_BOOT_DONE
out32(CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_PMCR_READY));
- PK_TRACE_INF("PMCR_TH: Inited\n");
-
-#if !defined(__IOTA__)
-
- while(1)
- {
- //pend on sempahore
- pk_semaphore_pend(&G_cme_pstate_record.sem[0], PK_WAIT_FOREVER);
- cme_pstate_pmcr_action();
- }
-
-#endif
-
- PK_TRACE_INF("PMCR_TH: Exit\n");
+ PK_TRACE_INF("CME INIT DONE: Exit\n");
}
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