diff options
| -rwxr-xr-x | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c | 81 | ||||
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c | 120 |
2 files changed, 103 insertions, 98 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index 7bd8ebc4..8077e11b 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -115,7 +115,7 @@ uint16_t ram_read_lpid( uint32_t core, uint32_t thread ) if (scom_data > 0xFFF ) { - PKTRACE("RAMMING ERROR Unexpected LPID core %d : 0x%lX 0xFFF", core, scom_data); + PK_TRACE("RAMMING ERROR Unexpected LPID core %d : 0x%lX 0xFFF", core, scom_data); PK_PANIC(CME_STOP_ENTRY_BAD_LPID_ERROR); } @@ -288,7 +288,7 @@ p9_cme_stop_entry() #endif // tlbie stop workaround //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ BEGIN OF STOP ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ BEGIN OF STOP ENTRY +++++ +++++"); //-------------------------------------------------------------------------- // First we need to determine which of the two STOP interrupts fired. @@ -416,7 +416,7 @@ p9_cme_stop_entry() #if HW386841_DD1_DSL_STOP1_FIX //---------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ STOP LEVEL 1 ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ STOP LEVEL 1 ENTRY +++++ +++++"); //---------------------------------------------------------------------- PK_TRACE("Pulse STOP entry acknowledgement to PC via SICR[0/1]"); @@ -447,7 +447,7 @@ p9_cme_stop_entry() } //---------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ STOP LEVEL 2 ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ STOP LEVEL 2 ENTRY +++++ +++++"); //---------------------------------------------------------------------- p9_cme_acquire_pcbmux(core, 1); @@ -480,14 +480,16 @@ p9_cme_stop_entry() PK_TRACE("Update STOP history: in transition of entry"); // Set req_level_level to target_level of either both or just one core scom_data.words.lower = 0; - scom_data.words.upper = (SSH_REQ_LEVEL_UPDATE | (target_level << SHIFT32(7))); + scom_data.words.upper = (SSH_REQ_LEVEL_UPDATE | + (((uint32_t)target_level) << SHIFT32(7))); CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value); // Set req_level_level to deeper_level for deeper core if (deeper_core) { scom_data.words.lower = 0; - scom_data.words.upper = (SSH_REQ_LEVEL_UPDATE | (deeper_level << SHIFT32(7))); + scom_data.words.upper = (SSH_REQ_LEVEL_UPDATE | + (((uint32_t)deeper_level) << SHIFT32(7))); CME_PUTSCOM(PPM_SSHSRC, deeper_core, scom_data.value); } @@ -504,13 +506,13 @@ p9_cme_stop_entry() if (core & CME_MASK_C0) { lpid_c0[thread] = ram_read_lpid(CME_MASK_C0, thread); - PKTRACE("c0lpid %X thread %X", (uint32_t) lpid_c0[thread], thread); + PK_TRACE("c0lpid %X thread %X", (uint32_t) lpid_c0[thread], thread); } if (core & CME_MASK_C1) { lpid_c1[thread] = ram_read_lpid(CME_MASK_C1, thread); - PKTRACE("c1lpid %X thread %X", (uint32_t) lpid_c1[thread], thread); + PK_TRACE("c1lpid %X thread %X", (uint32_t) lpid_c1[thread], thread); } } @@ -524,8 +526,8 @@ p9_cme_stop_entry() if (ram_read_lpid(CME_MASK_C0, thread) != POWMAN_RESERVED_LPID) { - PKTRACE("READ LPID not equal to expected value"); - asm("trap"); + PK_TRACE("READ LPID not equal to expected value"); + PK_PANIC(CME_STOP_ENTRY_BAD_LPID_ERROR); } #endif @@ -539,8 +541,8 @@ p9_cme_stop_entry() if (ram_read_lpid(CME_MASK_C1, thread) != POWMAN_RESERVED_LPID) { - PKTRACE("READ LPID not equal to expected value"); - asm("trap"); + PK_TRACE("READ LPID not equal to expected value"); + PK_PANIC(CME_STOP_ENTRY_BAD_LPID_ERROR); } #endif @@ -552,6 +554,8 @@ p9_cme_stop_entry() #endif // tlbie stop workaround + PK_TRACE_INF("SE.2A: Core[%d] PCB Mux Granted", core); + //============================= MARK_TRAP(SE_QUIESCE_CORE_INTF) //============================= @@ -579,7 +583,7 @@ p9_cme_stop_entry() // MF: verify generate FCB otherwise math is wrong. PPE_WAIT_CORE_CYCLES(512) - PK_TRACE_INF("SE2.B: Interfaces Quiesced"); + PK_TRACE_INF("SE.2B: Interfaces Quiesced"); #if HW402407_NDD1_TLBIE_STOP_WORKAROUND @@ -609,8 +613,8 @@ p9_cme_stop_entry() { if (ram_read_lpid(CME_MASK_C0, thread) != lpid_c0[thread]) { - PKTRACE("READ LPID not equal to expected value"); - asm("trap"); + PK_TRACE("READ LPID not equal to expected value"); + PK_PANIC(CME_STOP_ENTRY_BAD_LPID_ERROR); } } @@ -618,8 +622,8 @@ p9_cme_stop_entry() { if (ram_read_lpid(CME_MASK_C1, thread) != lpid_c1[thread]) { - PKTRACE("READ LPID not equal to expected value"); - asm("trap"); + PK_TRACE("READ LPID not equal to expected value"); + PK_PANIC(CME_STOP_ENTRY_BAD_LPID_ERROR); } } } @@ -693,7 +697,7 @@ p9_cme_stop_entry() // MF: verify compiler generate single rlwmni // MF: delay may be needed for stage latch to propagate thold - PK_TRACE_INF("SE2.C: Core Clock Stopped"); + PK_TRACE_INF("SE.2C: Core Clock Stopped"); //============================== MARK_TRAP(SE_STOP_CORE_GRID) @@ -750,7 +754,7 @@ p9_cme_stop_entry() G_cme_stop_record.act_level[1] = STOP_LEVEL_2; } - PK_TRACE_INF("SE2.D: Clock Sync Dropped"); + PK_TRACE_INF("SE.2D: Clock Sync Dropped"); //=========================== MARK_TAG(SE_STOP2_DONE, core) @@ -763,7 +767,8 @@ p9_cme_stop_entry() STOP_TRANS_COMPLETE : STOP_TRANS_ENTRY; scom_data.words.lower = 0; - scom_data.words.upper = (SSH_ACT_LV2_COMPLETE | (entry_ongoing << SHIFT32(3))); + scom_data.words.upper = (SSH_ACT_LV2_COMPLETE | + (((uint32_t)entry_ongoing) << SHIFT32(3))); CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value); // If both cores targeting different levels @@ -904,7 +909,7 @@ p9_cme_stop_entry() core, deeper_core, target_level, deeper_level); //---------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ STOP LEVEL 3 ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ STOP LEVEL 3 ENTRY +++++ +++++"); //---------------------------------------------------------------------- if (target_level == 3) @@ -970,7 +975,7 @@ p9_cme_stop_entry() } //---------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ STOP LEVEL 4 ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ STOP LEVEL 4 ENTRY +++++ +++++"); //---------------------------------------------------------------------- //=============================== @@ -1022,7 +1027,7 @@ p9_cme_stop_entry() // vdd_pfet_force_state = 00 (Nop) CME_PUTSCOM(PPM_PFCS_CLR, core, BITS64(0, 2)); - PK_TRACE_INF("SE4.A: Core Powered Off"); + PK_TRACE_INF("SE.4A: Core[%d] Powered Off", core); } #endif @@ -1048,7 +1053,8 @@ p9_cme_stop_entry() STOP_TRANS_ENTRY; scom_data.words.lower = 0; - scom_data.words.upper = (SSH_ACT_LV4_COMPLETE | (entry_ongoing << SHIFT32(3))); + scom_data.words.upper = (SSH_ACT_LV4_COMPLETE | + (((uint32_t)entry_ongoing) << SHIFT32(3))); CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value); // If both cores targeting different levels @@ -1117,7 +1123,7 @@ p9_cme_stop_entry() core, deeper_core, target_level, deeper_level); //---------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ STOP LEVEL 5-7 ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ STOP LEVEL 5-7 ENTRY +++++ +++++"); //---------------------------------------------------------------------- if ((G_cme_stop_record.req_level[0] >= STOP_LEVEL_8) && @@ -1163,7 +1169,7 @@ p9_cme_stop_entry() MARK_TAG(SE_PURGE_L2_ABORT, core_aborted) //======================================= - PK_TRACE_DBG("Abort: L2+NCU purge aborted by core[%d]", core_aborted); + PK_TRACE_INF("Abort: L2+NCU purge aborted by core[%d]", core_aborted); out32(CME_LCL_SICR_OR, BIT32(19) | BIT32(23)); } } @@ -1176,7 +1182,7 @@ p9_cme_stop_entry() PK_TRACE("Drop L2+NCU purges and their possible aborts via SICR[18,19,22,23]"); out32(CME_LCL_SICR_CLR, (BITS32(18, 2) | BITS32(22, 2))); - PK_TRACE_INF("SE5.A: L2 and NCU Purged"); + PK_TRACE_INF("SE.5A: L2 and NCU Purged"); //=================================================================== MARK_TAG(SE_PURGE_L2_DONE, core_aborted ? core_aborted : CME_MASK_BC) @@ -1220,7 +1226,7 @@ p9_cme_stop_entry() if ((scom_data.words.upper & BIT32(13))) { - PKTRACE("ERROR: C0 notify was already set?"); + PKTRACE("ERROR.A0: C0 notify was already set?"); pk_halt(); } @@ -1232,7 +1238,7 @@ p9_cme_stop_entry() if ((scom_data.words.upper & BIT32(13))) { - PKTRACE("ERROR: C1 notify was already set?"); + PKTRACE("ERROR.A1: C1 notify was already set?"); pk_halt(); } } @@ -1247,7 +1253,7 @@ p9_cme_stop_entry() { core_index = core_mask & 1; - if (G_cme_stop_record.req_level[core_index] < STOP_LEVEL_11) + if (G_cme_stop_record.req_level[core_index] >= STOP_LEVEL_8) { CME_PUTSCOM(CPPM_CPMMR_OR, core_mask, BIT64(10)); pig.fields.req_intr_type = PIG_TYPE3; @@ -1272,6 +1278,9 @@ p9_cme_stop_entry() #endif + PK_TRACE_DBG("Switch Core PPM wakeup to STOP-GPE via CPMMR[13]"); + CME_PUTSCOM(CPPM_CPMMR_OR, core, BIT64(13)); + #if DEBUG_RUNTIME_STATE_CHECK if (core & CME_MASK_C0) @@ -1280,7 +1289,7 @@ p9_cme_stop_entry() if (!(scom_data.words.upper & BIT32(13))) { - PKTRACE("ERROR: C0 notify fail to set"); + PKTRACE("ERROR.B0: C0 notify fail to set"); pk_halt(); } @@ -1292,23 +1301,23 @@ p9_cme_stop_entry() if (!(scom_data.words.upper & BIT32(13))) { - PKTRACE("ERROR: C1 notify fail to set"); + PKTRACE("ERROR.B1: C1 notify fail to set"); pk_halt(); } } #endif - PKTRACE("Switch Core%d PPM wakeup to STOP-GPE via CPMMR[13]", core); - CME_PUTSCOM(CPPM_CPMMR_OR, core, BIT64(13)); + PK_TRACE("Clear special wakeup after wakeup_notify = 1 since it is edge triggered"); + out32(CME_LCL_EISR_CLR, core << SHIFT32(15)); - PK_TRACE_INF("SE5.B: Handed off to SGPE"); + PK_TRACE_INF("SE.5B: Core[%d] Handed off to SGPE", core); } while(0); //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ END OF STOP ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ END OF STOP ENTRY +++++ +++++"); //-------------------------------------------------------------------------- //============================ diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c index a5ef6449..bf3b51bf 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c @@ -69,7 +69,7 @@ p9_sgpe_stop_entry() #endif //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ BEGIN OF STOP ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ BEGIN OF STOP ENTRY +++++ +++++"); //-------------------------------------------------------------------------- //================================ @@ -290,10 +290,10 @@ p9_sgpe_stop_entry() } // ------------------------------------------------------------------------ - PK_TRACE_INF("+++++ +++++ EX STOP ENTRY [LEVEL 8-10] +++++ +++++"); + PK_TRACE("+++++ +++++ EX STOP ENTRY [LEVEL 8-10] +++++ +++++"); // ------------------------------------------------------------------------ - PK_TRACE_DBG("Check: q[%d]ex[%d] start ex entry", qloop, ex); + PK_TRACE_INF("SX.8A: Quad[%d] EX_L2[%d] Stopping L2 Clocks", qloop, ex); PK_TRACE("Acquire cache clock controller atomic lock"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CC_ATOMIC_LOCK, qloop), BITS64(0, 5)); @@ -301,8 +301,8 @@ p9_sgpe_stop_entry() if ((scom_data.words.upper & BITS32(0, 5)) != 0xC0000000) { - PKTRACE("ERROR: Failed to Obtain Cache %d Clk Ctrl Atomic Lock. Register Content: %x", - qloop, scom_data.words.upper); + PK_TRACE_INF("ERROR: Failed to Obtain Cache %d Clk Ctrl Atomic Lock. Register Content: %x", + qloop, scom_data.words.upper); PK_PANIC(SGPE_STOP_ENTRY_GET_CLK_LOCK_FAILED); } @@ -413,7 +413,7 @@ p9_sgpe_stop_entry() // MF: verify compiler generate single rlwmni // MF: delay may be needed for stage latch to propagate thold - PK_TRACE_INF("SE8.A: L2 Clock Stopped"); + PK_TRACE_INF("SE.8B: L2 Clock Stopped"); //======================== MARK_TRAP(SE_STOP_L2_GRID) @@ -489,7 +489,7 @@ p9_sgpe_stop_entry() ((qloop << 2) + cloop)); scom_data.words.lower = 0; scom_data.words.upper = (SSH_ACT_LV8_COMPLETE | - ((entry_ongoing[cloop >> 1]) << SHIFT32(3))); + (((uint32_t)entry_ongoing[cloop >> 1]) << SHIFT32(3))); GPE_PUTSCOM_VAR(PPM_SSHSRC, CORE_ADDR_BASE, ((qloop << 2) + cloop), 0, scom_data.value); } @@ -498,7 +498,7 @@ p9_sgpe_stop_entry() out32(OCB_QSSR_CLR, BIT32(qloop + 20)); out32(OCB_QSSR_OR, (ex << SHIFT32((qloop << 1) + 1))); - PK_TRACE_INF("SE8.B: L2 Clock Sync Dropped"); + PK_TRACE_INF("SE.8C: L2 Clock Sync Dropped"); //================================================== MARK_TAG(SE_STOP8_DONE, ((ex << 6) | (32 >> qloop))) @@ -532,7 +532,7 @@ p9_sgpe_stop_entry() ex |= SND_EX_IN_QUAD; } - PK_TRACE_DBG("Check: q[%d]ex[%d] starts quad entry", qloop, ex); + PK_TRACE_INF("SX.11A: Quad[%d] EX_PG[%d] Shutting Cache Down", qloop, ex); PK_TRACE("Acquire cache PCB slave atomic lock"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_ATOMIC_LOCK, qloop), BITS64(0, 5)); @@ -540,8 +540,8 @@ p9_sgpe_stop_entry() if ((scom_data.words.upper & BITS32(0, 5)) != 0xC0000000) { - PKTRACE("ERROR: Failed to Obtain Cache %d PCB Slave Atomic Lock. Register Content: %x", - qloop, scom_data.words.upper); + PK_TRACE_INF("ERROR: Failed to Obtain Cache %d PCB Slave Atomic Lock. Register Content: %x", + qloop, scom_data.words.upper); PK_PANIC(SGPE_STOP_ENTRY_GET_SLV_LOCK_FAILED); } @@ -551,7 +551,7 @@ p9_sgpe_stop_entry() PK_TRACE("Update STOP history on quad[%d]: update request stop level", qloop); scom_data.words.lower = 0; scom_data.words.upper = (SSH_REQ_LEVEL_UPDATE | - (G_sgpe_stop_record.state[qloop].req_state_q << SHIFT32(7))); + ((uint32_t)G_sgpe_stop_record.state[qloop].req_state_q << SHIFT32(7))); GPE_PUTSCOM_VAR(PPM_SSHSRC, QUAD_ADDR_BASE, qloop, 0, scom_data.value); //================================== @@ -618,7 +618,7 @@ p9_sgpe_stop_entry() (in32(OCB_OPIT3CN(((qloop << 2) + cloop))) & TYPE3_PAYLOAD_EXIT_EVENT)) { - PK_TRACE_INF("Abort: core wakeup detected"); + PK_TRACE_DBG("Abort: core wakeup detected"); l3_purge_aborted = 1; break; } @@ -628,7 +628,7 @@ p9_sgpe_stop_entry() if ((in32(OCB_OPIT6PRB) & BIT32(qloop)) && (in32(OCB_OPIT6QN(qloop)) & TYPE6_PAYLOAD_EXIT_EVENT)) { - PK_TRACE_INF("Abort: quad wakeup detected"); + PK_TRACE_DBG("Abort: quad wakeup detected"); l3_purge_aborted = 1; } @@ -639,7 +639,7 @@ p9_sgpe_stop_entry() MARK_TAG(SE_PURGE_L3_ABORT, (32 >> qloop)) //======================================== - PK_TRACE_INF("Abort: assert purge L3 abort"); + PK_TRACE_DBG("Abort: assert purge L3 abort"); if (ex & FST_EX_IN_QUAD) GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 0), @@ -649,7 +649,7 @@ p9_sgpe_stop_entry() GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 1), BIT64(2)); - PK_TRACE_INF("Abort: poll for abort done"); + PK_TRACE_DBG("Abort: poll for abort done"); if(ex & FST_EX_IN_QUAD) { @@ -675,7 +675,7 @@ p9_sgpe_stop_entry() MARK_TAG(SE_PURGE_L3_ABORT_DONE, (32 >> qloop)) //============================================= - PK_TRACE_INF("Abort: Drop LCO Disable"); + PK_TRACE("Abort: Drop LCO Disable"); if (ex & FST_EX_IN_QUAD) GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_LCO_DIS_REG, @@ -713,7 +713,7 @@ p9_sgpe_stop_entry() continue; } - PK_TRACE_INF("SE11.A: L3 Purged"); + PK_TRACE_INF("SE.11B: L3 Purged"); #endif @@ -721,32 +721,7 @@ p9_sgpe_stop_entry() MARK_TAG(SE_PURGE_PB, (32 >> qloop)) //================================== - PK_TRACE("Assert powerbus purge via QCCR[30]"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, qloop), BIT64(30)); - - PK_TRACE("Poll PowerBus purge done via QCCR[31]"); - - do - { - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR, qloop), scom_data.value); - } - while(!(scom_data.words.upper & BIT32(31))); - - PK_TRACE("Drop powerbus purge via QCCR[30]"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(30)); - - PK_TRACE_INF("SE11.B: PowerBus Purged"); - - //=========================================== - MARK_TAG(SE_WAIT_PGPE_SUSPEND, (32 >> qloop)) - //=========================================== - - /// @todo RTC166577 - /// IPC poll will move to here when multicast - - //====================================== - MARK_TAG(SE_QUIESCE_QUAD, (32 >> qloop)) - //====================================== + // Stopping CME first in case CME initiates Powerbus Traffic if (ex & FST_EX_IN_QUAD) { @@ -784,6 +759,36 @@ p9_sgpe_stop_entry() PK_TRACE("CME1 Halted"); } + PK_TRACE_DBG("CME Halted"); + + + PK_TRACE("Assert powerbus purge via QCCR[30]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, qloop), BIT64(30)); + + PK_TRACE("Poll PowerBus purge done via QCCR[31]"); + + do + { + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR, qloop), scom_data.value); + } + while(!(scom_data.words.upper & BIT32(31))); + + PK_TRACE("Drop powerbus purge via QCCR[30]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(30)); + + PK_TRACE_INF("SE.11C: PowerBus Purged"); + + //=========================================== + MARK_TAG(SE_WAIT_PGPE_SUSPEND, (32 >> qloop)) + //=========================================== + + /// @todo RTC166577 + /// IPC poll will move to here when multicast + + //====================================== + MARK_TAG(SE_QUIESCE_QUAD, (32 >> qloop)) + //====================================== + PK_TRACE("Assert refresh quiesce prior to L3 (refresh domain) stop clk via EX_DRAM_REF_REG[7]"); // Assert refresh quiesce prior to L3 (refresh domain) stop clk @@ -824,7 +829,7 @@ p9_sgpe_stop_entry() while(((~(scom_data.words.upper)) & BITS32(0, 4)) != BITS32(0, 4)); } - PK_TRACE_INF("SE11.C: NCU Status Clean"); + PK_TRACE_DBG("NCU Status Clean"); // In order to preserve state for PRD, // skip power off if host attn or local xstop present @@ -851,10 +856,7 @@ p9_sgpe_stop_entry() PK_TRACE("Stop cache clocks via CLK_REGION"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLK_REGION, qloop), - (CLK_STOP_CMD | CLK_THOLD_ALL | - CLK_REGION_ALL_BUT_EX | - ((uint64_t)ex << SHIFT64(7)) | - ((uint64_t)ex << SHIFT64(13)))); + (CLK_STOP_CMD | CLK_THOLD_ALL | CLK_REGION_ALL)); PK_TRACE("Poll for cache clocks stopped via CPLT_STAT0[8]"); @@ -864,12 +866,10 @@ p9_sgpe_stop_entry() } while(!(scom_data.words.upper & BIT32(8))); - PK_TRACE("Check core clock is stopped via CLOCK_STAT_SL[4-13]"); + PK_TRACE("Check cache clock is stopped via CLOCK_STAT_SL[4-13]"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLOCK_STAT_SL, qloop), scom_data.value); - if (((~scom_data.value) & (CLK_REGION_ALL_BUT_EX | - ((uint64_t)ex << SHIFT64(7)) | - ((uint64_t)ex << SHIFT64(13)))) != 0) + if (((~scom_data.value) & CLK_REGION_ALL) != 0) { PK_TRACE("ERROR: Cache clock stop failed. HALT SGPE!"); PK_PANIC(SGPE_STOP_ENTRY_EQ_STOPCLK_FAILED); @@ -881,11 +881,7 @@ p9_sgpe_stop_entry() PK_TRACE("Assert partial good regional fences via CPLT_CTRL1[4-14]"); // Must cover partial bad fences as well or powerbus error will raise // Note: Stop11 will lose all the fences so here needs to assert them - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_OR, qloop), - (CLK_REGION_ALL_BUT_EX | - ((uint64_t)ex << SHIFT64(7)) | - ((uint64_t)ex << SHIFT64(9)) | - ((uint64_t)ex << SHIFT64(13)))); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_OR, qloop), CLK_REGION_ALL); PK_TRACE("Drop CME_INTERPPM_DPLL_ENABLE after DPLL is stopped via QPMMR[26]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QPMMR_CLR, qloop), BIT64(20) | BIT64(22) | BIT64(24) | BIT64(26)); @@ -894,7 +890,7 @@ p9_sgpe_stop_entry() PK_TRACE("Drop vdm enable via CPPM_VDMCR[0]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_VDMCR_CLR, qloop), BIT64(0)); - PK_TRACE_INF("SE11.D: Cache Clock Stopped"); + PK_TRACE_INF("SE.11D: Cache Clock Stopped"); #if HW405292_NDD1_PCBMUX_FENCE_FIX // Gate the PCBMux request so scanning doesn't cause random requests @@ -907,7 +903,7 @@ p9_sgpe_stop_entry() #if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX - PK_TRACE_INF("PBRW: Engage with PBIE Read/Write Pointer Scan Workaround"); + PK_TRACE_DBG("PBRW: Engage with PBIE Read/Write Pointer Scan Workaround"); // bit4,5,11 = perv/eqpb/pbieq, bit59 = inex PK_TRACE("PBRW: Setup scan register to select the ring"); @@ -1045,7 +1041,7 @@ p9_sgpe_stop_entry() // vcs_pfet_force_state = 00 (Nop) GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_CLR, qloop), BITS64(0, 4)); - PK_TRACE_INF("SE11.E: Cache Powered Off"); + PK_TRACE_INF("SE.11E: Cache Powered Off"); } #endif @@ -1086,7 +1082,7 @@ p9_sgpe_stop_entry() } //-------------------------------------------------------------------------- - PK_TRACE_INF("+++++ +++++ END OF STOP ENTRY +++++ +++++"); + PK_TRACE("+++++ +++++ END OF STOP ENTRY +++++ +++++"); //-------------------------------------------------------------------------- //loop quad to clear qswu record |
