STOP: express processing targets of stop1/2 and stop5/8 exit

Change-Id: I2f3cb6487b33051b40b68386cc72110678f0e5f6
Original-Change-Id: I4dd0d2fd1d87340b7cc73ecd4196310c96a23f24
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38290
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

3 files changed, 26 insertions, 31 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index 8077e11b..d25a71c9 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -257,7 +257,7 @@ void p9_cme_pcbmux_savior_epilogue(uint32_t core)
 
 #endif
 
-int
+void
 p9_cme_stop_entry()
 {
     int             catchup_ongoing     = 0;
@@ -317,7 +317,7 @@ p9_cme_stop_entry()
     {
         // PM_ACTIVE can be phantom, only gives warning
         PK_TRACE_INF("WARNING: Only Phantom PM_ACTIVE to be Ignored. Return");
-        return CME_STOP_SUCCESS;
+        return;
     }
 
     // NDD2: OOB bits wired to SISR
@@ -328,7 +328,7 @@ p9_cme_stop_entry()
         ((core & CME_MASK_C1) && (in32_sh(CME_LCL_SISR) & BITS64SH(61, 2))))
     {
         PK_TRACE_INF("WARNING: Attn/Recov Present, Abort Entry and Return");
-        return CME_STOP_SUCCESS;
+        return;
     }
 
     //===================================
@@ -1324,5 +1324,5 @@ p9_cme_stop_entry()
     MARK_TRAP(ENDSCOPE_STOP_ENTRY)
     //============================
 
-    return CME_STOP_SUCCESS;
+    return;
 }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
index 67183acd..1cb45b90 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
@@ -170,11 +170,6 @@ enum SGPE_IPC_CONSTANTS
     SGPE_IPC_RETURN_CODE_ACK          = 1
 };
 
-enum SGPE_STOP_RETURN_CODES
-{
-    SGPE_STOP_SUCCESS                 = 0
-};
-
 enum SGPE_STOP_IRQ_SHORT_NAMES
 {
     IRQ_STOP_TYPE2                    = OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING,
@@ -326,28 +321,28 @@ void p9_sgpe_ipc_pgpe_suspend_stop(ipc_msg_t* cmd, void* arg);
 void p9_sgpe_stop_pig_handler(void*, PkIrqId);
 void p9_sgpe_stop_enter_thread(void*);
 void p9_sgpe_stop_exit_thread(void*);
-int  p9_sgpe_stop_entry();
-int  p9_sgpe_stop_exit();
+void p9_sgpe_stop_entry();
+void p9_sgpe_stop_exit();
 
 /// Procedures shared between Istep4 and SGPE Stop
-int  p9_hcd_cache_scan0(uint32_t, uint64_t, uint64_t);
-int  p9_hcd_cache_poweron(uint32_t);
-int  p9_hcd_cache_chiplet_reset(uint32_t, uint32_t);
-int  p9_hcd_cache_chiplet_l3_dcc_setup(uint32_t);
-int  p9_hcd_cache_gptr_time_initf(uint32_t);
-int  p9_hcd_cache_dpll_initf(uint32_t);
-int  p9_hcd_cache_dpll_setup(uint32_t);
-int  p9_hcd_cache_dcc_skewadjust_setup(uint32_t);
-int  p9_hcd_cache_chiplet_init(uint32_t);
-int  p9_hcd_cache_repair_initf(uint32_t);
-int  p9_hcd_cache_arrayinit(uint32_t, uint32_t ex);
-int  p9_hcd_cache_initf(uint32_t);
-int  p9_hcd_cache_startclocks(uint32_t, uint32_t);
-int  p9_hcd_cache_l2_startclocks(uint32_t, uint32_t, uint32_t);
-int  p9_hcd_cache_scominit(uint32_t, uint32_t, int);
-int  p9_hcd_cache_scomcust(uint32_t, uint32_t, int);
-int  p9_hcd_cache_ras_runtime_scom(uint32_t);
-int  p9_hcd_cache_occ_runtime_scom(uint32_t);
+void p9_hcd_cache_scan0(uint32_t, uint64_t, uint64_t);
+void p9_hcd_cache_poweron(uint32_t);
+void p9_hcd_cache_chiplet_reset(uint32_t, uint32_t);
+void p9_hcd_cache_chiplet_l3_dcc_setup(uint32_t);
+void p9_hcd_cache_gptr_time_initf(uint32_t);
+void p9_hcd_cache_dpll_initf(uint32_t);
+void p9_hcd_cache_dpll_setup(uint32_t);
+void p9_hcd_cache_dcc_skewadjust_setup(uint32_t);
+void p9_hcd_cache_chiplet_init(uint32_t);
+void p9_hcd_cache_repair_initf(uint32_t);
+void p9_hcd_cache_arrayinit(uint32_t, uint32_t ex);
+void p9_hcd_cache_initf(uint32_t);
+void p9_hcd_cache_startclocks(uint32_t, uint32_t);
+void p9_hcd_cache_l2_startclocks(uint32_t, uint32_t, uint32_t);
+void p9_hcd_cache_scominit(uint32_t, uint32_t, int);
+void p9_hcd_cache_scomcust(uint32_t, uint32_t, int);
+void p9_hcd_cache_ras_runtime_scom(uint32_t);
+void p9_hcd_cache_occ_runtime_scom(uint32_t);
 
 #ifdef __cplusplus
 }  // extern "C"
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
index bf3b51bf..c8d79439 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
@@ -44,7 +44,7 @@ extern SgpeStopRecord                           G_sgpe_stop_record;
 
 #endif
 
-int
+void
 p9_sgpe_stop_entry()
 {
     int          entry_ongoing[2] = {0, 0};
@@ -1145,5 +1145,5 @@ p9_sgpe_stop_entry()
     MARK_TRAP(ENDSCOPE_STOP_ENTRY)
     //============================
 
-    return SGPE_STOP_SUCCESS;
+    return;
 }