diff options
author | Yue Du <daviddu@us.ibm.com> | 2018-02-23 09:57:34 -0600 |
---|---|---|
committer | hostboot <hostboot@us.ibm.com> | 2018-03-22 14:04:11 -0500 |
commit | c4298d3e3ec9f44fbc6d15b1157ad1369b9f5292 (patch) | |
tree | 0049660ca3694141bfb1353b6715671217bde7f5 /import | |
parent | 23beea75bf21b835a4d87eee917416f2e3865554 (diff) | |
download | talos-hcode-c4298d3e3ec9f44fbc6d15b1157ad1369b9f5292.tar.gz talos-hcode-c4298d3e3ec9f44fbc6d15b1157ad1369b9f5292.zip |
STOP: Support Suspend Entry/Exit and Fix Pig Collision
1) also cleanup todos in Stop Hcode
2) make STOP3 complete trans in SSH
Key_Cronus_Test=PM_REGRESS
Change-Id: I28a146e15e455f09f8d8ff588e122d5ecf34110a
CQ: SW416550
CQ: HW437955
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54660
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Diffstat (limited to 'import')
6 files changed, 110 insertions, 102 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c index c36ee54e..55a22848 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c @@ -39,7 +39,7 @@ CmePstateRecord G_cme_pstate_record __attribute__((section (".dump_ptr_pstate")) // CME Stop Header and Structure #include "p9_cme_stop.h" -CmeStopRecord G_cme_stop_record __attribute__((section (".dump_ptr_stop"))) = {{0}, {0}, 0, 0, 0, 0, 0, 0, 0, {0}}; +CmeStopRecord G_cme_stop_record __attribute__((section (".dump_ptr_stop"))) = {{0}, {0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0}}; #if !DISABLE_PERIODIC_CORE_QUIESCE && (NIMBUS_DD_LEVEL == 20 || NIMBUS_DD_LEVEL == 21 || CUMULUS_DD_LEVEL == 10) CmeFitRecord G_cme_fit_record = {0, 0, 0, 0, 0xFFFFFFFF, 0}; diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c index 4c9d3210..3e4275d7 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c +++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c @@ -76,6 +76,9 @@ int send_pig_packet(uint64_t data, uint32_t coreMask) int rc = 0; uint64_t data_tmp; + PkMachineContext ctx __attribute__((unused)); + pk_critical_section_enter(&ctx); + // First make sure no interrupt request is currently granted do { @@ -87,6 +90,8 @@ int send_pig_packet(uint64_t data, uint32_t coreMask) // Send PIG packet CME_PUTSCOM(PPM_PIG, coreMask, data); + pk_critical_section_exit(&ctx); + return rc; } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h index 7cafec64..3483fced 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h @@ -222,6 +222,16 @@ enum CME_STOP_SRR1 NO_STATE_LOSS = 1 }; +enum CME_STOP_SUSPEND_BLOCK +{ + STOP_SUSPEND_ENCODE = 0xF, //0bxxxx for command encodings of (un)block or (un)suspend + STOP_SUSPEND_ACTION = 0x8, //0b1xxY for suspend/block, 0xxY for unsuspend/unblock + STOP_SUSPEND_EXIT = 0x4, //0bZ10Y for (un)suspend/(un)block exit + STOP_SUSPEND_ENTRY = 0x2, //0bZ01Y for (un)suspend/(un)block entry + STOP_SUSPEND_SELECT = 0x1 //0bZxx1 for SUSPEND, 0bZxx0 for BLOCK +}; + + enum CME_SCOM_RESTORE_CONST { SCOM_REST_SKIP_CODE = 0x60000000, @@ -273,6 +283,10 @@ typedef struct uint32_t core_blockwu; // core in block entry mode, can be used as core select in scom address or data uint32_t core_blockey; + // core in suspend wakeup mode, can be used as core select in scom address or data + uint32_t core_suspendwu; + // core in suspend entry mode, can be used as core select in scom address or data + uint32_t core_suspendey; // core in special wakeup, can be used as core select in scom address or data uint32_t core_in_spwu; // core in error state, prevent it being further processed diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index ee660ecd..54cee07b 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -584,13 +584,11 @@ p9_cme_stop_entry() while((in32(CME_LCL_EINR)) & (core << SHIFT32(21))); wrteei(1); - sync(); // end of HW407385 // --------------------------------- - #if NIMBUS_DD_LEVEL != 10 if (target_level > STOP_LEVEL_3 || deeper_level > STOP_LEVEL_3) @@ -846,6 +844,8 @@ p9_cme_stop_entry() } } + sync(); + #endif // tlbie stop workaround // ==================================== @@ -933,6 +933,8 @@ p9_cme_stop_entry() #endif turn_off_ram_mode (core); + sync(); + #endif // tlbie stop workaround // ==================================== @@ -940,7 +942,6 @@ p9_cme_stop_entry() // --------------------------------- // Permanent workaround for HW407385 - sync(); wrteei(0); PK_TRACE("HW407385: Drop pm_exit via SICR[4/5]"); @@ -1106,6 +1107,18 @@ p9_cme_stop_entry() MARK_TAG(SE_STOP2_DONE, core) //=========================== + // Round Stop3 to Stop2 + if (target_level == STOP_LEVEL_3) + { + target_level = STOP_LEVEL_2; + } + + if (deeper_level == STOP_LEVEL_3) + { + deeper_core = 0; + deeper_level = 0; + } + PK_TRACE("Update STOP history: in core stop level 2"); // Check if STOP level 2 reaches the target for both or one core entry_ongoing = @@ -1258,72 +1271,6 @@ p9_cme_stop_entry() core, deeper_core, target_level, deeper_level); //---------------------------------------------------------------------- - PK_TRACE("+++++ +++++ STOP LEVEL 3 ENTRY +++++ +++++"); - //---------------------------------------------------------------------- - - if (target_level == 3) - { - /* - //========================== - MARK_TAG(SE_CORE_VMIN, core) - //========================== - - PK_TRACE("SE3.a"); - // Enable IVRM if not already - - PK_TRACE("SE3.b"); - - // Drop to Vmin - if(core & CME_MASK_C0) - { - G_cme_stop_record.act_level[0] = STOP_LEVEL_3; - } - - if(core & CME_MASK_C1) - { - G_cme_stop_record.act_level[1] = STOP_LEVEL_3; - } - - //=========================== - MARK_TAG(SE_STOP3_DONE, core) - //=========================== - - PK_TRACE("SE3.c"); - // Update Stop History: In Core Stop Level 3 - scom_data.words.lower = 0; - scom_data.words.upper = SSH_ACT_LV3_COMPLETE; - CME_PUTSCOM(PPM_SSHSRC, core, scom_data.value); - */ - // If both cores targeting different levels - // deeper core should have at least deeper stop level than 3 - // only need to modify deeper core history if another one was done - if (deeper_core) - { - /* - scom_data.words.lower = 0; - scom_data.words.upper = SSH_ACT_LV3_CONTINUE; - CME_PUTSCOM(PPM_SSHSRC, deeper_core, scom_data.value); - */ - // from now on, proceed with only deeper core - core = deeper_core; - target_level = deeper_level; - deeper_level = 0; - deeper_core = 0; - entry_ongoing = 1; - } - else - { - entry_ongoing = 0; - } - - // If we are done at STOP level 3 - if (!entry_ongoing) - { - break; - } - } - - //---------------------------------------------------------------------- PK_TRACE("+++++ +++++ STOP LEVEL 4 ENTRY +++++ +++++"); //---------------------------------------------------------------------- @@ -1625,7 +1572,7 @@ p9_cme_stop_entry() pig.fields.req_intr_payload = G_cme_stop_record.req_level[core_index]; // put PIG and Wakeup_Notify_Select back to back as possible - CME_PUTSCOM(PPM_PIG, core_mask, pig.value); + send_pig_packet(pig.value, core_mask); CME_PUTSCOM(CPPM_CPMMR_OR, core_mask, BIT64(13)); PK_TRACE_DBG("Switch Core[%d] PPM wakeup to STOP-GPE via CPMMR[13]", core_mask); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c index 539f5555..f4fe6a1e 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c @@ -50,7 +50,8 @@ p9_cme_stop_pcwu_handler(void) PK_TRACE_INF("PCWU Handler Trigger: Core Interrupts %x", core); // consider wakeup is done on a running core - core &= (~G_cme_stop_record.core_running); + // also ignore the decrementor request that already sent to sgpe + core &= ~(G_cme_stop_record.core_running | G_cme_stop_record.core_blockpc); out32(CME_LCL_EISR_CLR, (G_cme_stop_record.core_running << SHIFT32(13))); for (core_mask = 2; core_mask; core_mask--) @@ -67,7 +68,7 @@ p9_cme_stop_pcwu_handler(void) { pig.fields.req_intr_type = PIG_TYPE2; pig.fields.req_intr_payload = TYPE2_PAYLOAD_DECREMENTER_WAKEUP; - CME_PUTSCOM_NOP(PPM_PIG, core_mask, pig.value); + send_pig_packet(pig.value, core_mask); } // block pc for stop8,11 or stop5 as pig sent @@ -82,7 +83,7 @@ p9_cme_stop_pcwu_handler(void) { PK_TRACE_INF("PCWU Launching exit thread"); - out32(CME_LCL_EIMR_OR, BITS32(12, 10)); + out32(CME_LCL_EIMR_OR, BITS32(10, 12)); wrteei(1); p9_cme_stop_exit(); } @@ -168,7 +169,7 @@ p9_cme_stop_spwu_handler(void) { PK_TRACE_INF("SPWU Launching exit thread"); - out32(CME_LCL_EIMR_OR, BITS32(12, 10)); + out32(CME_LCL_EIMR_OR, BITS32(10, 12)); wrteei(1); p9_cme_stop_exit(); } @@ -185,7 +186,7 @@ p9_cme_stop_rgwu_handler(void) MARK_TRAP(STOP_RGWU_HANDLER) PK_TRACE_INF("RGWU Handler Trigger"); - out32(CME_LCL_EIMR_OR, BITS32(12, 10)); + out32(CME_LCL_EIMR_OR, BITS32(10, 12)); wrteei(1); p9_cme_stop_exit(); @@ -201,7 +202,7 @@ p9_cme_stop_enter_handler(void) MARK_TRAP(STOP_ENTER_HANDLER) PK_TRACE_INF("PM_ACTIVE Handler Trigger"); - out32(CME_LCL_EIMR_OR, BITS32(12, 10)); + out32(CME_LCL_EIMR_OR, BITS32(10, 12)); wrteei(1); // The actual entry sequence @@ -269,7 +270,7 @@ p9_cme_stop_db2_handler(void) // Finish handshake with SGPE for Stop11 via PIG pig.fields.req_intr_type = PIG_TYPE5; pig.fields.req_intr_payload = TYPE5_PAYLOAD_ENTRY_RCLK | STOP_LEVEL_11; - CME_PUTSCOM_NOP(PPM_PIG, core_mask, pig.value); + send_pig_packet(pig.value, core_mask); break; case MSGID_DB2_RESONANT_CLOCK_ENABLE: @@ -297,7 +298,7 @@ p9_cme_stop_db2_handler(void) // Finish handshake with SGPE for Stop11 via PIG pig.fields.req_intr_type = PIG_TYPE5; pig.fields.req_intr_payload = TYPE5_PAYLOAD_EXIT_RCLK; - CME_PUTSCOM_NOP(PPM_PIG, core_mask, pig.value); + send_pig_packet(pig.value, core_mask); break; default: @@ -317,13 +318,15 @@ p9_cme_stop_db1_handler(void) { cppm_cmedb1_t db1 = {0}; ppm_pig_t pig = {0}; + uint32_t core = 0; + uint32_t encode = 0; uint32_t suspend_ack = 0; MARK_TRAP(STOP_DB1_HANDLER) PK_TRACE_INF("DB1 Handler Trigger"); // Suspend DB should only come from the first good core - uint32_t core = G_cme_pstate_record.firstGoodCoreMask; + core = G_cme_pstate_record.firstGoodCoreMask; CME_GETSCOM(CPPM_CMEDB1, core, db1.value); CME_PUTSCOM_NOP(CPPM_CMEDB1, core, 0); @@ -332,16 +335,26 @@ p9_cme_stop_db1_handler(void) PK_TRACE_DBG("DB1 Handler MessageID %d Triggered By Core %d", db1.fields.cme_message_numbern, core); - // block msgs - if ((db1.fields.cme_message_numbern > 0x4) && - (db1.fields.cme_message_numbern < 0x8)) + encode = db1.fields.cme_message_numbern & STOP_SUSPEND_ENCODE; + + // block/suspend msgs(0xA-0xF) + if ((encode > (STOP_SUSPEND_ACTION | STOP_SUSPEND_SELECT)) && (encode <= STOP_SUSPEND_ENCODE)) { suspend_ack = 1; // exit - if (db1.fields.cme_message_numbern & 0x2) + if (encode & STOP_SUSPEND_EXIT) { - G_cme_stop_record.core_blockwu |= CME_MASK_BC; + if (encode & STOP_SUSPEND_SELECT) + { + G_cme_stop_record.core_suspendwu |= CME_MASK_BC; + } + else + { + G_cme_stop_record.core_blockwu |= CME_MASK_BC; + } + + g_eimr_override |= IRQ_VEC_WAKE_C0 | IRQ_VEC_WAKE_C1; #if HW386841_NDD1_DSL_STOP1_FIX @@ -358,9 +371,18 @@ p9_cme_stop_db1_handler(void) } // entry - if (db1.fields.cme_message_numbern & 0x1) + if (encode & STOP_SUSPEND_ENTRY) { - G_cme_stop_record.core_blockey |= CME_MASK_BC; + if (encode & STOP_SUSPEND_SELECT) + { + G_cme_stop_record.core_suspendey |= CME_MASK_BC; + } + else + { + G_cme_stop_record.core_blockey |= CME_MASK_BC; + } + + g_eimr_override |= IRQ_VEC_STOP_C0 | IRQ_VEC_STOP_C1; #if HW386841_NDD1_DSL_STOP1_FIX @@ -373,16 +395,24 @@ p9_cme_stop_db1_handler(void) out32(CME_LCL_FLAGS_OR, BITS32(10, 2)); } } - // unblock msgs - else if ((db1.fields.cme_message_numbern < 0x4) && - (db1.fields.cme_message_numbern > 0)) + // unblock/unsuspend msgs(0x2-0x7) + else if ((encode < STOP_SUSPEND_ACTION) && (encode > STOP_SUSPEND_SELECT)) { suspend_ack = 1; // exit - if (db1.fields.cme_message_numbern & 0x2) + if (encode & STOP_SUSPEND_EXIT) { - G_cme_stop_record.core_blockwu &= ~CME_MASK_BC; + if (encode & STOP_SUSPEND_SELECT) + { + G_cme_stop_record.core_suspendwu &= ~CME_MASK_BC; + } + else + { + G_cme_stop_record.core_blockwu &= ~CME_MASK_BC; + } + + g_eimr_override &= ~(IRQ_VEC_WAKE_C0 | IRQ_VEC_WAKE_C1); #if HW386841_NDD1_DSL_STOP1_FIX @@ -399,9 +429,18 @@ p9_cme_stop_db1_handler(void) } // entry - if (db1.fields.cme_message_numbern & 0x1) + if (encode & STOP_SUSPEND_ENTRY) { - G_cme_stop_record.core_blockey &= ~CME_MASK_BC; + if (encode & STOP_SUSPEND_SELECT) + { + G_cme_stop_record.core_suspendey &= ~CME_MASK_BC; + } + else + { + G_cme_stop_record.core_blockey &= ~CME_MASK_BC; + } + + g_eimr_override &= ~(IRQ_VEC_STOP_C0 | IRQ_VEC_STOP_C1); #if HW386841_NDD1_DSL_STOP1_FIX @@ -417,11 +456,10 @@ p9_cme_stop_db1_handler(void) if (suspend_ack) { - pig.fields.req_intr_payload = db1.fields.cme_message_numbern; - pig.fields.req_intr_payload = pig.fields.req_intr_payload << 8; - pig.fields.req_intr_payload |= 0x080; // set bit 4 for ack package + // Shift encode to bit4 of 12 bits, then set bit5 + pig.fields.req_intr_payload = ((encode << 7) | TYPE2_PAYLOAD_SUSPEND_ACK_MASK); pig.fields.req_intr_type = PIG_TYPE3; - CME_PUTSCOM_NOP(PPM_PIG, core, pig.value); + send_pig_packet(pig.value, core); } // re-evaluate stop entry & exit enables diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_threads.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_threads.c index 93d72e5f..58310c4c 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_threads.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_threads.c @@ -69,24 +69,28 @@ p9_cme_stop_eval_eimr_override() G_cme_stop_record.core_running | G_cme_stop_record.core_errored | G_cme_stop_record.core_blockpc | - G_cme_stop_record.core_blockwu) & CME_MASK_BC) << SHIFT32(13)) | + G_cme_stop_record.core_blockwu | + G_cme_stop_record.core_suspendwu) & CME_MASK_BC) << SHIFT32(13)) | #if SPWU_AUTO ((((~G_cme_record.core_enabled) | G_cme_stop_record.core_running | G_cme_stop_record.core_errored) & CME_MASK_BC) << SHIFT32(15)) | #else ((((~G_cme_stop_record.core_running) & - G_cme_stop_record.core_blockwu) & CME_MASK_BC) << SHIFT32(15)) | + (G_cme_stop_record.core_blockwu | + G_cme_stop_record.core_suspendwu)) & CME_MASK_BC) << SHIFT32(15)) | #endif ((((~G_cme_record.core_enabled) | G_cme_stop_record.core_running | G_cme_stop_record.core_errored | - G_cme_stop_record.core_blockwu) & CME_MASK_BC) << SHIFT32(17)) | + G_cme_stop_record.core_blockwu | + G_cme_stop_record.core_suspendwu) & CME_MASK_BC) << SHIFT32(17)) | ((((~G_cme_record.core_enabled) | (~G_cme_stop_record.core_running) | G_cme_stop_record.core_errored | G_cme_stop_record.core_in_spwu | - G_cme_stop_record.core_blockey) & CME_MASK_BC) << SHIFT32(21)); + G_cme_stop_record.core_blockey | + G_cme_stop_record.core_suspendey) & CME_MASK_BC) << SHIFT32(21)); g_eimr_override |= mask_irqs.value; } |