diff options
| author | Brian Vanderpool <vanderp@us.ibm.com> | 2017-05-17 10:01:39 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-08-22 17:54:53 -0500 |
| commit | 927a4ffbc292e27f764bb7e3b2a353a9974d7bad (patch) | |
| tree | e953de02ab5f15b2ef21084287f2264dbb24b1a3 /import | |
| parent | 8e8f54fb5906f78a7ef84fd9e76451847e63e38e (diff) | |
| download | talos-hcode-927a4ffbc292e27f764bb7e3b2a353a9974d7bad.tar.gz talos-hcode-927a4ffbc292e27f764bb7e3b2a353a9974d7bad.zip | |
STOP: Move delay after LPID change to before asserting quiesce
Change-Id: Ia6ca4e34a22f3a392672c9d4970269f06444ec61
Original-Change-Id: Ie4f44477258ad97432a368949618189905ad9c25
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40626
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Diffstat (limited to 'import')
| -rwxr-xr-x | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index 8f15f4c7..43332b64 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -171,8 +171,6 @@ void turn_off_ram_mode (uint32_t core) PK_TRACE("LPID Clear core maintenance mode via direct controls"); CME_PUTSCOM(DIRECT_CONTROLS, core, (BIT64(3) | BIT64(11) | BIT64(19) | BIT64(27))); - PK_TRACE("LPID Wait for 8K Core Cycles"); - PPE_WAIT_CORE_CYCLES(8000); } #endif @@ -564,6 +562,12 @@ p9_cme_stop_entry() out32(CME_LCL_LMCR_OR, (core << SHIFT32(13))); #endif + +#if HW402407_NDD1_TLBIE_STOP_WORKAROUND + // Need to wait for any pending TLBIEs to complete + PPE_WAIT_CORE_CYCLES(2000) +#endif + PK_TRACE("Assert core-L2 + core-CC quiesces via SICR[6/7,8/9]"); out32(CME_LCL_SICR_OR, (core << SHIFT32(7)) | (core << SHIFT32(9))); |
