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| author | Yue Du <daviddu@us.ibm.com> | 2017-09-21 09:15:06 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-08-22 17:55:25 -0500 |
| commit | 42f7f07224835f7e1fe9ef14e916861a9886045e (patch) | |
| tree | 66c637c52fea002121ba83ae7ebc0e54604b5e44 /import | |
| parent | 2f9abf6ea21a579ad6f5af79292ba29e8d889a19 (diff) | |
| download | talos-hcode-42f7f07224835f7e1fe9ef14e916861a9886045e.tar.gz talos-hcode-42f7f07224835f7e1fe9ef14e916861a9886045e.zip | |
STOP: Properly clear DPLL unlock indication in dpll_setup
Change-Id: If0139c9208d0b961b7454df46bbda183cce7d24d
Original-Change-Id: I0d8ecd45e3b4f7414de10bb785069509b623f7ab
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46563
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import')
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h | 2 | ||||
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h index 2e51c40f..8dd916a9 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h @@ -93,6 +93,8 @@ extern "C" { #define EQ_THERM_MODE_REG 0x1005000F #define EQ_BIST 0x100F000B +#define EQ_SLAVE_CONFIG_REG 0x100F001E +#define EQ_ERROR_REG 0x100F001F #define EQ_HANG_PULSE_6_REG 0x100F0026 #define EQ_NET_CTRL0_WAND 0x100F0041 #define EQ_NET_CTRL0_WOR 0x100F0042 diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c index adc70b5c..0f3efd56 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c @@ -1169,6 +1169,14 @@ p9_sgpe_stop_entry() } else { + // upon power off cache, dpll is about to be unlocked + // to prevent pcb fir fires, need to mask the bit for the time being + // the error will be cleared and unmasked when dpll is locked again + PK_TRACE("Mask DPLL unlock error in FIR via SLAVE_CONFIG[12]"); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_SLAVE_CONFIG_REG, qloop), scom_data.value); + scom_data.words.upper |= BIT32(12); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_SLAVE_CONFIG_REG, qloop), scom_data.value); + PK_TRACE("Drop vdd/vcs_pfet_val/sel_override/regulation_finger_en via PFCS[4-7,8]"); // vdd_pfet_val/sel_override = 0 (disbaled) // vcs_pfet_val/sel_override = 0 (disbaled) |
