diff options
| author | Yue Du <daviddu@us.ibm.com> | 2017-02-21 21:42:59 -0600 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-08-22 17:54:30 -0500 |
| commit | 2b66fcf8c509c83d0a1ffe55e49ac4f85787f8de (patch) | |
| tree | 74d4d918f05c6a139f62649e4fad2f0b663a6786 /import | |
| parent | 2770649588ff569e119cf489b13069d44a88aeee (diff) | |
| download | talos-hcode-2b66fcf8c509c83d0a1ffe55e49ac4f85787f8de.tar.gz talos-hcode-2b66fcf8c509c83d0a1ffe55e49ac4f85787f8de.zip | |
STOP: Change ring_save structure to 0xfff3fc00 PDA location
z .pda_ptrs 0x00000000fff3fc00 0x180
z 0x00000000fff3fc00 G_ring_save
z
z uint64_t G_ring_save[MAX_QUADS][8]
z __attribute__((section(".pda_ptrs"))) =
z {
z {0, 0, 0, 0, 0, 0, 0, 0},
z {0, 0, 0, 0, 0, 0, 0, 0},
z {0, 0, 0, 0, 0, 0, 0, 0},
z {0, 0, 0, 0, 0, 0, 0, 0},
z {0, 0, 0, 0, 0, 0, 0, 0},
z {0, 0, 0, 0, 0, 0, 0, 0}
z };
Change-Id: I1d4163887e9a0c8964ce1ee9e309c7bd92da5a98
Original-Change-Id: Ie48971ffaaa0d342d4091e0884cf1ae27a0265d6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36837
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Diffstat (limited to 'import')
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h | 8 | ||||
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c | 31 |
2 files changed, 13 insertions, 26 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h index 7aa7a0ad..561a4e39 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h @@ -303,6 +303,14 @@ typedef struct uint64_t data; } SgpeScomRestore; +#if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX +// Types for PB EQ asynch work-around +struct ring_save +{ + uint64_t element[MAX_QUADS][8]; +}; +#endif + #if HW405292_NDD1_PCBMUX_FENCE_FIX void p9_sgpe_set_slvcfg_pm_disable(uint32_t); void p9_sgpe_clear_slvcfg_pm_disable(uint32_t); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c index c56c0b14..0a0ffcfa 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c @@ -39,29 +39,8 @@ extern SgpeStopRecord G_sgpe_stop_record; #if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX -uint64_t G_ring_save[MAX_QUADS][8] = -{ - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0} -}; - -uint64_t G_ring_spin[10][2] = -{ - {0, 0}, - {5039, 0xE000000000000000}, //3 - {5100, 0xC1E061FFED5F0000}, //29 - {5664, 0xE000000000000000}, //3 - {5725, 0xC1E061FFED5F0000}, //29 - {5973, 0xE000000000000000}, //3 - {6034, 0xC1E061FFED5F0000}, //29 - {6282, 0xE000000000000000}, //3 - {6343, 0xC1E061FFED5F0000}, //29 - {17871, 0} //128 -}; + extern struct ring_save* G_ring_save; + extern uint64_t G_ring_spin[10][2]; #endif @@ -929,7 +908,7 @@ p9_sgpe_stop_entry() PK_TRACE("FCMS: save pbie read ptr"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data.value); EXTRACT_RING_BITS(G_ring_spin[spin][1], scom_data.value, - G_ring_save[qloop][spin - 1]); + G_ring_save->element[qloop][spin - 1]); PK_TRACE("FCMS: mask: %8x %8x", UPPER32(G_ring_spin[spin][1]), LOWER32(G_ring_spin[spin][1])); @@ -937,8 +916,8 @@ p9_sgpe_stop_entry() scom_data.words.upper, scom_data.words.lower); PK_TRACE("FCMS: save: %8x %8x", - UPPER32(G_ring_save[qloop][spin - 1]), - LOWER32(G_ring_save[qloop][spin - 1])); + UPPER32(G_ring_save->element[qloop][spin - 1]), + LOWER32(G_ring_save->element[qloop][spin - 1])); } GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10030005, qloop), 0); |
