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author | Yue Du <daviddu@us.ibm.com> | 2017-03-23 17:25:37 -0500 |
---|---|---|
committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:16:46 -0500 |
commit | 2960f26ef6d3d74fa74cd24f3aca6df75ba79ace (patch) | |
tree | 43e65ffcb93fc4c7dbf1f2124fde59613c1253f2 /import | |
parent | 1d3803bbe6e6176e0850d5940c7cfcea80dd6275 (diff) | |
download | talos-hcode-2960f26ef6d3d74fa74cd24f3aca6df75ba79ace.tar.gz talos-hcode-2960f26ef6d3d74fa74cd24f3aca6df75ba79ace.zip |
STOP: Using PANIC codes at every pk_halt
Change-Id: I89bba67a31ac5a049b5f7787a179aeea58adb917
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38390
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import')
20 files changed, 113 insertions, 109 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h b/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h index e29fca38..0c1fecd0 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h +++ b/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h @@ -42,23 +42,23 @@ // The following are reserved for instance specific use. -PUTRING_HEADER_ERROR = 0x1c00, -//_UNUSED_1c01 = 0x1c01, -//_UNUSED_1c02 = 0x1c02, -//_UNUSED_1c03 = 0x1c03, -//_UNUSED_1c04 = 0x1c04, -//_UNUSED_1c05 = 0x1c05, -//_UNUSED_1c06 = 0x1c06, -//_UNUSED_1c07 = 0x1c07, -//_UNUSED_1c08 = 0x1c08, -//_UNUSED_1c09 = 0x1c09, -//_UNUSED_1c0a = 0x1c0a, -//_UNUSED_1c0d = 0x1c0d, -//_UNUSED_1c1c = 0x1c1c, -//_UNUSED_1c1d = 0x1c1d, +CME_UIH_DISABLED_NOT_LAST_LVL = 0x1c00, +CME_UIH_NOT_ALL_IN_PRTY_GROUP = 0x1c01, +CME_UIH_EIMR_STACK_UNDERFLOW = 0x1c02, +CME_UIH_EIMR_STACK_OVERFLOW = 0x1c03, +CME_UIH_PHANTOM_INTERRUPT = 0x1c04, +CME_STOP_PUTRING_HEADER_ERROR = 0x1c05, +CME_STOP_BCE_CORE_RING_FAILED = 0x1c06, +CME_STOP_EXIT_PHANTOM_WAKEUP = 0x1c07, +CME_STOP_EXIT_BCE_SCOM_FAILED = 0x1c08, +CME_STOP_EXIT_SELF_RES_SPATTN = 0x1c09, +CME_STOP_EXIT_STARTCLK_FAILED = 0x1c0a, +CME_STOP_ENTRY_STOPCLK_FAILED = 0x1c0d, +CME_STOP_ENTRY_WITH_AUTO_NAP = 0x1c1c, // NDD1 +CME_STOP_ENTRY_BAD_LPID_ERROR = 0x1c1d, // NDD1 //_UNUSED_1c1e = 0x1c1e, //_UNUSED_1c1f = 0x1c1f, - +// //_UNUSED_1d00 = 0x1d00, //_UNUSED_1d01 = 0x1d01, //_UNUSED_1d02 = 0x1d02, diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c index 253490c1..096b9732 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c @@ -204,7 +204,7 @@ void pk_unified_irq_prty_mask_handler(void) { MY_TRACE_ERR("Code bug: EIMR S/R stack counter=%d >= max=%d.", g_eimr_stack_ctr, NUM_EXT_IRQ_PRTY_LEVELS); - pk_halt(); + PK_PANIC(CME_UIH_EIMR_STACK_OVERFLOW); } // 3. Write the new mask for this priority level. @@ -217,7 +217,7 @@ void pk_unified_irq_prty_mask_handler(void) MY_TRACE_ERR("A disabled IRQ fired"); MY_TRACE_ERR("ext_irq_vector_pk=0x%08x%08x", ext_irq_vector_pk); #if !EPM_P9_TUNING - pk_halt(); + PK_PANIC(CME_UIH_PHANTOM_INTERRUPT); #endif } diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h index ca56f2fe..927b9d0d 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h @@ -145,7 +145,7 @@ pk_irq_vec_restore(PkMachineContext* context) { PK_TRACE("Code bug: Messed up EIMR book keeping: g_eimr_stack_ctr=%d", g_eimr_stack_ctr); - pk_halt(); + PK_PANIC(CME_UIH_EIMR_STACK_UNDERFLOW); } //pk_critical_section_exit(context); diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c index 7317a51d..0ef43d2d 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c @@ -187,14 +187,14 @@ main(int argc, char** argv) { MY_TRACE_ERR("Code bug: IDX_PRTY_LVL_DISABLED(=%d)!=NUM_EXT_IRQ_PRTY_LEVELS(=%d)-1", IDX_PRTY_LVL_DISABLED, NUM_EXT_IRQ_PRTY_LEVELS); - pk_halt(); + PK_PANIC(CME_UIH_DISABLED_NOT_LAST_LVL); } if (IRQ_VEC_PRTY_CHECK != 0xFFFFFFFFFFFFFFFF) { MY_TRACE_ERR("Code bug: IRQ_VEC_PRTY_CHECK=0x%08x%08x should be all ones", IRQ_VEC_PRTY_CHECK); - pk_halt(); + PK_PANIC(CME_UIH_NOT_ALL_IN_PRTY_GROUP); } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index 97be5573..aa91de4b 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -116,7 +116,7 @@ uint16_t ram_read_lpid( uint32_t core, uint32_t thread ) if (scom_data > 0xFFF ) { PKTRACE("RAMMING ERROR Unexpected LPID core %d : 0x%lX 0xFFF", core, scom_data); - pk_halt(); + PK_PANIC(CME_STOP_ENTRY_BAD_LPID_ERROR); } return ((uint16_t) scom_data); @@ -440,7 +440,7 @@ p9_cme_stop_entry() // Nap should be done by hardware when auto_stop1 is enabled // Halt on error if target STOP level == 1(Nap) PK_TRACE_INF("ERROR: Stop 1 Requested to CME When AUTO_STOP1 Enabled, HALT CME!"); - pk_halt(); + PK_PANIC(CME_STOP_ENTRY_WITH_AUTO_NAP); #endif @@ -687,7 +687,7 @@ p9_cme_stop_entry() if (((~scom_data.value) & CLK_REGION_ALL_BUT_PLL) != 0) { PK_TRACE_INF("ERROR: Core Clock Stop Failed. HALT CME!"); - pk_halt(); + PK_PANIC(CME_STOP_ENTRY_STOPCLK_FAILED); } // MF: verify compiler generate single rlwmni diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c index 75dd7926..613fb1b6 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c @@ -203,7 +203,7 @@ p9_cme_stop_exit() if (!core) { PK_TRACE_INF("ERROR: No Wakeup Fired to a Stopped and Enabled Core. HALT CME!"); - pk_halt(); + PK_PANIC(CME_STOP_EXIT_PHANTOM_WAKEUP); } @@ -525,7 +525,7 @@ p9_cme_stop_exit() if( BLOCK_COPY_SUCCESS != isScanRingCopyDone() ) { PK_TRACE_INF("ERROR: BCE Scom Restore Copy Failed. HALT CME!"); - pk_halt(); + PK_PANIC(CME_STOP_EXIT_BCE_SCOM_FAILED); } #endif @@ -667,7 +667,7 @@ p9_cme_stop_exit() if (in32_sh(CME_LCL_SISR) & (core << SHIFT64SH(33))) { PK_TRACE("ERROR: Core Special Attention Detected. HALT CME!"); - pk_halt(); + PK_PANIC(CME_STOP_EXIT_SELF_RES_SPATTN); } } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c index 93649fbe..9a540e17 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c @@ -135,7 +135,7 @@ p9_hcd_core_startclocks(uint32_t core) if(scom_data.value & CLK_REGION_ALL_BUT_PLL) { PK_TRACE("Core clock start failed"); - pk_halt(); + PK_PANIC(CME_STOP_EXIT_STARTCLK_FAILED); } PK_TRACE("Core clock is now running"); diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c index 52c5f399..d94b0768 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c +++ b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c @@ -544,7 +544,7 @@ int rs4DecompressionSvc( uint32_t debug_data_1 = (uint32_t)(l_readHeader >> 32); asm volatile ("mtedr %0" : : "r" (debug_data_0) : "memory"); asm volatile ("mtsprg0 %0" : : "r" (debug_data_1) : "memory"); - PK_PANIC(PUTRING_HEADER_ERROR); + PK_PANIC(CME_STOP_PUTRING_HEADER_ERROR); } // Clean scan region and type data diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c index 9dd1fcc1..a5e70627 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c @@ -207,7 +207,7 @@ p9_hcd_cache_chiplet_reset(uint32_t quad, uint32_t ex) if (scom_data & l_regions) { PK_TRACE("Perv/l20/l21 clock start failed"); - pk_halt(); + PK_PANIC(SGPE_STOP_EXIT_VCS_STARTCLK_FAILED); } PK_TRACE("Perv/l20/l21 clocks running now"); @@ -256,7 +256,7 @@ p9_hcd_cache_chiplet_reset(uint32_t quad, uint32_t ex) if (((~scom_data) & l_regions) != 0) { PK_TRACE("Perv/l20/l21 clock stop failed"); - pk_halt(); + PK_PANIC(SGPE_STOP_EXIT_VCS_STOPCLK_FAILED); } PK_TRACE("Perv/l20/l21 Clock Stopped"); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c index 637cec78..95d9f312 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c @@ -72,7 +72,7 @@ p9_hcd_cache_dpll_setup(uint32_t quad) if (scom_data & BIT64(14)) { PK_TRACE("Start DPLL clock failed"); - pk_halt(); + PK_PANIC(SGPE_STOP_EXIT_DPLL_STARTCLK_FAILED); } PK_TRACE("DPLL clock is now running"); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c index 5038ac84..989492c9 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c @@ -108,7 +108,7 @@ p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex, uint32_t pg) if (scom_data & ((uint64_t)ex << SHIFT64(9))) { PK_TRACE("L2 clock start failed"); - pk_halt(); + PK_PANIC(SGPE_STOP_EXIT_L2_STARTCLK_FAILED); } PK_TRACE("L2 clock is now running"); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c index bd24b033..9a340420 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c @@ -165,7 +165,7 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex) ((uint64_t)ex << SHIFT64(13)))) { PK_TRACE("Cache clock start failed"); - pk_halt(); + PK_PANIC(SGPE_STOP_EXIT_EQ_STARTCLK_FAILED); } PK_TRACE("Cache clocks running now"); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c index ca51cf54..0d183c01 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c @@ -133,7 +133,7 @@ void pk_unified_irq_prty_mask_handler(void) { MY_TRACE_ERR("Code bug: EIMR S/R stack counter=%d >= max=%d.", g_oimr_stack_ctr, NUM_EXT_IRQ_PRTY_LEVELS); - pk_halt(); + PK_PANIC(SGPE_UIH_EIMR_STACK_OVERFLOW); } // 3. Write the new mask for this priority level. @@ -159,7 +159,7 @@ void pk_unified_irq_prty_mask_handler(void) MY_TRACE_ERR("A disabled IRQ fired"); MY_TRACE_ERR("ext_irq_vector_pk=0x%08x%08x", ext_irq_vector_pk); #if !EPM_P9_TUNING - pk_halt(); + PK_PANIC(SGPE_UIH_PHANTOM_INTERRUPT); #endif } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h index 2c7c13f8..de69f5ef 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h @@ -134,7 +134,7 @@ pk_irq_vec_restore(PkMachineContext* context) { PK_TRACE("Code bug: Messed up EIMR book keeping: g_oimr_stack_ctr=%d", g_oimr_stack_ctr); - pk_halt(); + PK_PANIC(SGPE_UIH_EIMR_STACK_UNDERFLOW); } //pk_critical_section_exit(context); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C index 53e60beb..fad5d88d 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C @@ -153,7 +153,7 @@ main(int argc, char** argv) if( fapiRc != fapi2::FAPI2_RC_SUCCESS ) { PK_TRACE_INF("ERROR: FAPI2 Init Failed. HALT SGPE!"); - pk_halt(); + PK_PANIC(SGPE_MAIN_FAPI2_INIT_FAILED); } // Initialize the thread control block for G_p9_sgpe_stop_enter_thread diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c index 52f7d57f..d2a8ebdb 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c @@ -199,7 +199,7 @@ p9_sgpe_stop_entry() if (rc) { PK_TRACE_INF("ERROR: Entry Updates PGPE with Active Cores Failed. HALT SGPE!"); - pk_halt(); + PK_PANIC(SGPE_STOP_ENTRY_IPC_CORE_FAILED); } // can poll right away since pgpe should ack right back @@ -210,7 +210,7 @@ p9_sgpe_stop_entry() if (G_sgpe_ipcmsg_update_cores.fields.return_code != SGPE_IPC_RETURN_CODE_ACK) { PK_TRACE_INF("ERROR: Entry Updates PGPE with Active Cores Bad RC. HALT SGPE!"); - pk_halt(); + PK_PANIC(SGPE_STOP_ENTRY_IPC_CORE_BAD_RC); } G_sgpe_stop_record.group.core[VECTOR_ACTIVE] &= @@ -255,7 +255,7 @@ p9_sgpe_stop_entry() if(rc) { PK_TRACE_INF("ERROR: Entry Suspend PGPE Pstate Function Failed. HALT SGPE!"); - pk_halt(); + PK_PANIC(SGPE_STOP_ENTRY_IPC_PSTATE_FAILED); } /// @todo RTC166577 @@ -267,7 +267,7 @@ p9_sgpe_stop_entry() if (G_sgpe_ipcmsg_suspend_pstate.fields.return_code != SGPE_IPC_RETURN_CODE_ACK) { PK_TRACE_INF("ERROR: Entry Suspend PGPE Pstate Function Bad RC. HALT SGPE!"); - pk_halt(); + PK_PANIC(SGPE_STOP_ENTRY_IPC_PSTATE_BAD_RC); } G_sgpe_stop_record.group.quad[VECTOR_ACTIVE] &= @@ -309,7 +309,7 @@ p9_sgpe_stop_entry() { PKTRACE("ERROR: Failed to Obtain Cache %d Clk Ctrl Atomic Lock. Register Content: %x", qloop, scom_data.words.upper); - pk_halt(); + PK_PANIC(SGPE_STOP_ENTRY_GET_CLK_LOCK_FAILED); } PK_TRACE("Update QSSR: stop_entry_ongoing"); @@ -413,7 +413,7 @@ p9_sgpe_stop_entry() if (((~(scom_data.words.upper)) & (ex << SHIFT32(9))) != 0) { PK_TRACE("ERROR: L2 clock stop failed. HALT SGPE!"); - pk_halt(); + PK_PANIC(SGPE_STOP_ENTRY_L2_STOPCLK_FAILED); } // MF: verify compiler generate single rlwmni @@ -548,7 +548,7 @@ p9_sgpe_stop_entry() { PKTRACE("ERROR: Failed to Obtain Cache %d PCB Slave Atomic Lock. Register Content: %x", qloop, scom_data.words.upper); - pk_halt(); + PK_PANIC(SGPE_STOP_ENTRY_GET_SLV_LOCK_FAILED); } PK_TRACE("Update QSSR: stop_entry_ongoing"); @@ -878,7 +878,7 @@ p9_sgpe_stop_entry() ((uint64_t)ex << SHIFT64(13)))) != 0) { PK_TRACE("ERROR: Cache clock stop failed. HALT SGPE!"); - pk_halt(); + PK_PANIC(SGPE_STOP_ENTRY_EQ_STOPCLK_FAILED); } PK_TRACE("Assert vital fence via CPLT_CTRL1[3]"); @@ -913,24 +913,24 @@ p9_sgpe_stop_entry() #if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX - PK_TRACE_INF("FCMS: Engage with PBIE Read/Write Pointer Scan Workaround"); + PK_TRACE_INF("PBRW: Engage with PBIE Read/Write Pointer Scan Workaround"); // bit4,5,11 = perv/eqpb/pbieq, bit59 = inex - PK_TRACE("FCMS: Setup scan register to select the ring"); + PK_TRACE("PBRW: Setup scan register to select the ring"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10030005, qloop), BITS64(4, 2) | BIT64(11) | BIT64(59)); - PK_TRACE("FCMS: checkword set"); + PK_TRACE("PBRW: checkword set"); scom_data.value = 0xa5a5a5a5a5a5a5a5; GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data.value); for(spin = 1;; spin++) { - PK_TRACE("FCMS: spin ring loop%d", spin); + PK_TRACE("PBRW: spin ring loop%d", spin); scom_data.words.upper = (G_ring_spin[spin][0] - G_ring_spin[spin - 1][0]); scom_data.words.lower = 0; GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10039000, qloop), scom_data.value); - PK_TRACE("FCMS: Poll OPCG done for ring spin"); + PK_TRACE("PBRW: Poll OPCG done for ring spin"); do { @@ -940,30 +940,30 @@ p9_sgpe_stop_entry() if (spin == 9) { - PK_TRACE("FCMS: checkword check"); + PK_TRACE("PBRW: checkword check"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data.value); if (scom_data.value != 0xa5a5a5a5a5a5a5a5) { PK_TRACE("ERROR: checkword[%x%x] failed. HALT SGPE!", scom_data.words.upper, scom_data.words.lower); - pk_halt(); + PK_PANIC(SGPE_STOP_ENTRY_PBRW_SCAN_HEADER_ERR); } break; } - PK_TRACE("FCMS: save pbie read ptr"); + PK_TRACE("PBRW: save pbie read ptr"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data.value); EXTRACT_RING_BITS(G_ring_spin[spin][1], scom_data.value, G_ring_save->element[qloop][spin - 1]); - PK_TRACE("FCMS: mask: %8x %8x", + PK_TRACE("PBRW: mask: %8x %8x", UPPER32(G_ring_spin[spin][1]), LOWER32(G_ring_spin[spin][1])); - PK_TRACE("FCMS: ring: %8x %8x", + PK_TRACE("PBRW: ring: %8x %8x", scom_data.words.upper, scom_data.words.lower); - PK_TRACE("FCMS: save: %8x %8x", + PK_TRACE("PBRW: save: %8x %8x", UPPER32(G_ring_save->element[qloop][spin - 1]), LOWER32(G_ring_save->element[qloop][spin - 1])); } @@ -1130,7 +1130,8 @@ p9_sgpe_stop_entry() if(rc) { - pk_halt(); + PK_TRACE_INF("ERROR: Entry Updates PGPE with Active Quads FAILED. HALT SGPE!"); + PK_PANIC(SGPE_STOP_ENTRY_IPC_QUAD_FAILED); } PK_TRACE_INF("SEIPC: Poll PGPE Update Active Quads Ack"); @@ -1140,7 +1141,7 @@ p9_sgpe_stop_entry() if (G_sgpe_ipcmsg_update_quads.fields.return_code != SGPE_IPC_RETURN_CODE_ACK) { PK_TRACE_INF("ERROR: Entry Updates PGPE with Active Quads Bad RC. HALT SGPE!"); - pk_halt(); + PK_PANIC(SGPE_STOP_ENTRY_IPC_QUAD_BAD_RC); } G_sgpe_stop_record.group.quad[VECTOR_ACTIVE] &= diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c index 625ff027..c5402e8f 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c @@ -126,7 +126,7 @@ fused_core_mode_scan_fix(uint32_t qloop, int l2bit) { PK_TRACE_INF("ERROR: checkword[%x%x] failed. HALT SGPE!", UPPER32(scom_data), LOWER32(scom_data)); - pk_halt(); + PK_PANIC(SGPE_STOP_EXIT_FUSE_SCAN_HEADER_ERR); } break; @@ -217,7 +217,7 @@ p9_sgpe_stop_exit() if(rc) { PK_TRACE_INF("ERROR: Exit Updates PGPE with Active Cores Failed. HALT SGPE!"); - pk_halt(); + PK_PANIC(SGPE_STOP_EXIT_IPC_CORE_FAILED); } /// @todo RTC166577 @@ -229,7 +229,7 @@ p9_sgpe_stop_exit() if (G_sgpe_ipcmsg_update_cores.fields.return_code != SGPE_IPC_RETURN_CODE_ACK) { PK_TRACE_INF("ERROR: Exit Updates PGPE with Active Cores Bad RC. HALT SGPE!"); - pk_halt(); + PK_PANIC(SGPE_STOP_EXIT_IPC_CORE_BAD_RC); } G_sgpe_stop_record.group.core[VECTOR_ACTIVE] |= @@ -267,7 +267,7 @@ p9_sgpe_stop_exit() if(rc) { PK_TRACE_INF("ERROR: Exit Updates PGPE with Active Quads Failed. HALT SGPE!"); - pk_halt(); + PK_PANIC(SGPE_STOP_EXIT_IPC_QUAD_FAILED); } /// @todo RTC166577 @@ -279,7 +279,7 @@ p9_sgpe_stop_exit() if (G_sgpe_ipcmsg_update_quads.fields.return_code != SGPE_IPC_RETURN_CODE_ACK) { PK_TRACE_INF("ERROR: Exit Updates PGPE with Active Quads Bad RC. HALT SGPE!"); - pk_halt(); + PK_PANIC(SGPE_STOP_EXIT_IPC_QUAD_BAD_RC); } G_sgpe_stop_record.group.quad[VECTOR_ACTIVE] |= @@ -544,7 +544,7 @@ p9_sgpe_stop_exit() { PK_TRACE_INF("ERROR: checkword[%x%x] failed. HALT SGPE!", scom_data.words.upper, scom_data.words.lower); - pk_halt(); + PK_PANIC(SGPE_STOP_EXIT_PBRW_SCAN_HEADER_ERR); } break; @@ -652,7 +652,7 @@ p9_sgpe_stop_exit() { PKTRACE("ERROR: Failed to Release Cache %d Clk Ctrl Atomic Lock. Register Content: %x", qloop, scom_data.words.upper); - pk_halt(); + PK_PANIC(SGPE_STOP_EXIT_DROP_CLK_LOCK_FAILED); } } @@ -933,7 +933,7 @@ p9_sgpe_stop_exit() { PKTRACE("ERROR: Failed to Release Cache %d PCB Slave Atomic Lock. Register Content: %x", qloop, scom_data.words.upper); - pk_halt(); + PK_PANIC(SGPE_STOP_EXIT_DROP_SLV_LOCK_FAILED); } G_sgpe_stop_record.state[qloop].act_state_q = 0; diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c index 6d9e814a..866993d9 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c @@ -257,14 +257,14 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) if ((!cpayload_t2) && (!cpayload_t3)) { PK_TRACE_INF("ERROR: Empty Requests on Both Type2 and Type3"); - pk_halt(); + PK_PANIC(SGPE_PIG_TYPE23_BOTH_EMPTY); } // both entry else if ((cpayload_t2 && (!(cpayload_t2 & TYPE2_PAYLOAD_EXIT_EVENT))) && (cpayload_t3 && (!(cpayload_t3 & TYPE2_PAYLOAD_EXIT_EVENT)))) { PK_TRACE_INF("ERROR: Entry Requests on Both Type2 and Type3"); - pk_halt(); + PK_PANIC(SGPE_PIG_TYPE23_BOTH_ENTRY); } // if t2 entry (t3 exit or empty) else if (cpayload_t2 && (!(cpayload_t2 & TYPE2_PAYLOAD_EXIT_EVENT))) @@ -273,7 +273,7 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) if (!(scom_data & BIT64(13))) { PK_TRACE_INF("ERROR: Received Type2 Entry PIG When Wakeup_notify_select = 0"); - pk_halt(); + PK_PANIC(SGPE_PIG_TYPE2_ENTRY_WNS_CME); } PK_TRACE_INF("C[%d] Request Entry via Type2", cloop); @@ -288,7 +288,7 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) if (!(scom_data & BIT64(13))) { PK_TRACE_INF("ERROR: Received Type3 Entry PIG When Wakeup_notify_select = 0"); - pk_halt(); + PK_PANIC(SGPE_PIG_TYPE3_ENTRY_WNS_CME); } PK_TRACE_INF("C[%d] Request Entry via Type3", cloop); @@ -306,7 +306,7 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) (cpayload_t3 & TYPE2_PAYLOAD_EXIT_EVENT)) { PK_TRACE_INF("ERROR: Received Both Types of Exit PIG When Wakeup_notify_select = 0"); - pk_halt(); + PK_PANIC(SGPE_PIG_TYPE23_EXIT_WNS_CME); } } else diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/sgpe_panic_codes.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/sgpe_panic_codes.h index b37b4a75..ac480f44 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/sgpe_panic_codes.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/sgpe_panic_codes.h @@ -42,50 +42,53 @@ // The following are reserved for instance specific use. -PUTRING_HEADER_ERROR = 0x1c00, -PUTRING_OPCG_TIMEOUT = 0x1c02, -//_UNUSED_1c03 = 0x1c03, -//_UNUSED_1c04 = 0x1c04, -//_UNUSED_1c05 = 0x1c05, -//_UNUSED_1c06 = 0x1c06, -//_UNUSED_1c07 = 0x1c07, -//_UNUSED_1c08 = 0x1c08, -//_UNUSED_1c09 = 0x1c09, -//_UNUSED_1c0a = 0x1c0a, -//_UNUSED_1c0d = 0x1c0d, +SGPE_MAIN_FAPI2_INIT_FAILED = 0x1c00, +SGPE_UIH_EIMR_STACK_UNDERFLOW = 0x1c01, +SGPE_UIH_EIMR_STACK_OVERFLOW = 0x1c02, +SGPE_UIH_PHANTOM_INTERRUPT = 0x1c03, +SGPE_STOP_EX0_PARTIAL_ERROR = 0x1c04, +SGPE_STOP_EX1_PARTIAL_ERROR = 0x1c05, +SGPE_STOP_QUAD_PARTIAL_ERROR = 0x1c06, +SGPE_PIG_TYPE23_BOTH_EMPTY = 0x1c07, +SGPE_PIG_TYPE23_BOTH_ENTRY = 0x1c08, +SGPE_PIG_TYPE23_EXIT_WNS_CME = 0x1c09, +SGPE_PIG_TYPE2_ENTRY_WNS_CME = 0x1c0a, +SGPE_PIG_TYPE3_ENTRY_WNS_CME = 0x1c0d, //_UNUSED_1c1c = 0x1c1c, //_UNUSED_1c1d = 0x1c1d, //_UNUSED_1c1e = 0x1c1e, //_UNUSED_1c1f = 0x1c1f, -//_UNUSED_1d00 = 0x1d00, -//_UNUSED_1d01 = 0x1d01, -//_UNUSED_1d02 = 0x1d02, -//_UNUSED_1d03 = 0x1d03, -//_UNUSED_1d04 = 0x1d04, -//_UNUSED_1d05 = 0x1d05, -//_UNUSED_1d06 = 0x1d06, -//_UNUSED_1d07 = 0x1d07, -//_UNUSED_1d08 = 0x1d08, -//_UNUSED_1d09 = 0x1d09, -//_UNUSED_1d0a = 0x1d0a, -//_UNUSED_1d0d = 0x1d0d, -//_UNUSED_1d1c = 0x1d1c, -//_UNUSED_1d1d = 0x1d1d, + +SGPE_STOP_PUTRING_HEADER_ERROR = 0x1d00, +SGPE_STOP_PUTRING_OPCG_TIMEOUT = 0x1d00, +SGPE_STOP_EXIT_IPC_CORE_FAILED = 0x1d01, +SGPE_STOP_EXIT_IPC_CORE_BAD_RC = 0x1d02, +SGPE_STOP_EXIT_IPC_QUAD_FAILED = 0x1d03, +SGPE_STOP_EXIT_IPC_QUAD_BAD_RC = 0x1d04, +SGPE_STOP_EXIT_DROP_CLK_LOCK_FAILED = 0x1d05, +SGPE_STOP_EXIT_DROP_SLV_LOCK_FAILED = 0x1d06, +SGPE_STOP_EXIT_DPLL_STARTCLK_FAILED = 0x1d07, +SGPE_STOP_EXIT_L2_STARTCLK_FAILED = 0x1d08, +SGPE_STOP_EXIT_EQ_STARTCLK_FAILED = 0x1d09, +SGPE_STOP_EXIT_VCS_STOPCLK_FAILED = 0x1d0a, // NDD1 +SGPE_STOP_EXIT_VCS_STARTCLK_FAILED = 0x1d0d, // NDD1 +SGPE_STOP_EXIT_FUSE_SCAN_HEADER_ERR = 0x1d1c, // NDD1 +SGPE_STOP_EXIT_PBRW_SCAN_HEADER_ERR = 0x1d1d, // NDD1 //_UNUSED_1d1e = 0x1d1e, //_UNUSED_1d1f = 0x1d1f, -//_UNUSED_1e00 = 0x1e00, -//_UNUSED_1e01 = 0x1e01, -//_UNUSED_1e02 = 0x1e02, -//_UNUSED_1e03 = 0x1e03, -//_UNUSED_1e04 = 0x1e04, -//_UNUSED_1e05 = 0x1e05, -//_UNUSED_1e06 = 0x1e06, -//_UNUSED_1e07 = 0x1e07, -//_UNUSED_1e08 = 0x1e08, -//_UNUSED_1e09 = 0x1e09, -//_UNUSED_1e0a = 0x1e0a, +SGPE_STOP_ENTRY_IPC_CORE_FAILED = 0x1e00, +SGPE_STOP_ENTRY_IPC_CORE_BAD_RC = 0x1e01, +SGPE_STOP_ENTRY_IPC_QUAD_FAILED = 0x1e02, +SGPE_STOP_ENTRY_IPC_QUAD_BAD_RC = 0x1e03, +SGPE_STOP_ENTRY_IPC_PSTATE_FAILED = 0x1e04, +SGPE_STOP_ENTRY_IPC_PSTATE_BAD_RC = 0x1e05, +SGPE_STOP_ENTRY_GET_CLK_LOCK_FAILED = 0x1e06, +SGPE_STOP_ENTRY_GET_SLV_LOCK_FAILED = 0x1e07, +SGPE_STOP_ENTRY_L2_STOPCLK_FAILED = 0x1e08, +SGPE_STOP_ENTRY_EQ_STOPCLK_FAILED = 0x1e09, +SGPE_STOP_ENTRY_PBRW_SCAN_HEADER_ERR = 0x1e0a, // NDD1 //_UNUSED_1e0d = 0x1e0d, //_UNUSED_1e1c = 0x1e1c, //_UNUSED_1e1d = 0x1e1d, diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C index 75014d70..d46c3230 100755 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C @@ -367,7 +367,7 @@ fapi2::ReturnCode verifyHeader(const fapi2::Target<fapi2::TARGET_TYPE_ALL>& uint32_t debug_data_1 = (uint32_t)(l_readHeader >> 32); asm volatile ("mtedr %0" : : "r" (debug_data_0) : "memory"); asm volatile ("mtsprg0 %0" : : "r" (debug_data_1) : "memory"); - PK_PANIC(PUTRING_HEADER_ERROR); + PK_PANIC(SGPE_STOP_PUTRING_HEADER_ERROR); } @@ -526,7 +526,7 @@ fapi2::ReturnCode rs4DecompressionSvc( uint32_t debug_data_0 = ((uint32_t)l_ringId << 24) | ((uint32_t) ((l_chiplet >> 24) & 0x0F) << 20) | (l_bitRotates & 0x000FFFFF); asm volatile ("mtedr %0" : : "r" (debug_data_0) : "memory"); - PK_PANIC(PUTRING_OPCG_TIMEOUT); + PK_PANIC(SGPE_STOP_PUTRING_OPCG_TIMEOUT); } } |