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| author | Michael Floyd <mfloyd@us.ibm.com> | 2017-06-27 12:16:24 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-08-22 17:55:00 -0500 |
| commit | 0fea3b0735370ee2c1b967fcc417c1cca3d131c8 (patch) | |
| tree | 4a36f6eda23d33cc59de92247d50f9e7b4bea6b6 /import | |
| parent | 5ef29f4f0b449d5a82be2f7b32b25abf1db4ac7c (diff) | |
| download | talos-hcode-0fea3b0735370ee2c1b967fcc417c1cca3d131c8.tar.gz talos-hcode-0fea3b0735370ee2c1b967fcc417c1cca3d131c8.zip | |
Fix DD LEVEL to support minor ECs
Change-Id: Ifdc48eeadbae4df747d7dd19e84d43b1f463b197
Original-Change-Id: I658b545b74e4aab8b766b1424632c25edd76c73f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42513
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: BRIAN D. VICTOR <brian.d.victor1@ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Diffstat (limited to 'import')
| -rwxr-xr-x | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c | 10 | ||||
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c | 2 |
2 files changed, 6 insertions, 6 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index bc749425..05d12753 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -291,7 +291,7 @@ p9_cme_stop_entry() MARK_TAG(BEGINSCOPE_STOP_ENTRY, core) //=================================== -#if NIMBUS_DD_LEVEL == 2 || DISABLE_CME_DUAL_CAST == 1 +#if NIMBUS_DD_LEVEL == 20 || DISABLE_CME_DUAL_CAST == 1 uint32_t dual_core = core; uint32_t single_core = CME_MASK_C0; @@ -693,7 +693,7 @@ p9_cme_stop_entry() PK_TRACE("Clear SCAN_REGION_TYPE prior to stop core clocks"); CME_PUTSCOM(C_SCAN_REGION_TYPE, core, 0); -#if NIMBUS_DD_LEVEL == 1 +#if NIMBUS_DD_LEVEL == 10 // NDD1: Core Global Xstop FIR if (core & CME_MASK_C0) @@ -1174,7 +1174,7 @@ p9_cme_stop_entry() //---------------------------------------------------------------------- // NDD1 workaround to save cme image size -#if NIMBUS_DD_LEVEL != 1 +#if NIMBUS_DD_LEVEL != 10 if ((G_cme_stop_record.req_level[0] >= STOP_LEVEL_8) && (G_cme_stop_record.req_level[1] >= STOP_LEVEL_8)) @@ -1324,7 +1324,7 @@ p9_cme_stop_entry() } } -#if NIMBUS_DD_LEVEL != 1 +#if NIMBUS_DD_LEVEL != 10 PK_TRACE("Drop PPM_WRITE_DISABLE via CPMMR[0]"); CME_PUTSCOM(CPPM_CPMMR_CLR, core, BIT64(0)); @@ -1372,7 +1372,7 @@ p9_cme_stop_entry() PK_TRACE("+++++ +++++ END OF STOP ENTRY +++++ +++++"); //-------------------------------------------------------------------------- -#if NIMBUS_DD_LEVEL == 2 || DISABLE_CME_DUAL_CAST == 1 +#if NIMBUS_DD_LEVEL == 20 || DISABLE_CME_DUAL_CAST == 1 // NDD2: dual cast workaround loop end } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c index 81750587..da36fc77 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c @@ -346,7 +346,7 @@ p9_sgpe_stop_entry() } // NDD1 workaround to save cme image size -#if NIMBUS_DD_LEVEL == 1 +#if NIMBUS_DD_LEVEL == 10 PK_TRACE("Assert L2+NCU purge and NCU tlbie quiesce via SICR[18,21,22]"); // insert tlbie quiesce before ncu purge to avoid window condition |
