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| author | Yue Du <daviddu@us.ibm.com> | 2016-10-08 15:33:01 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 16:40:25 -0500 |
| commit | 9935a1f237ec8bbe2258b598c9327e88d54190ff (patch) | |
| tree | 4066a64b7833e40d3601a3332fd4c6b5ad6b5f03 /import/chips | |
| parent | c98e02bd54fc973304da43be6c95d5126e395de9 (diff) | |
| download | talos-hcode-9935a1f237ec8bbe2258b598c9327e88d54190ff.tar.gz talos-hcode-9935a1f237ec8bbe2258b598c9327e88d54190ff.zip | |
CME/SGPE: yet another updating commit for stop images
patchset 1: fix EISTR in stop interrupt handler
patchset 2: add QPMMR[21-26] setup in sgpe(for John)
patchset 3: add DD1 VCS workaround to sgpe
patchset 4: add common header file change for patch3
patchset 5: fix an error in vcs workaround
patchset 6: reorganize the compiler flags
patchset 7: fix a typo in 6, and rebase to fix jenkins
patchset 8: reorganize the compiler flags(cme)
remove ppm write protection of cme
patchset 9: fix a typo in sgpe_exit qssr reporting
patchset 10:add extra dd1 vcs workaround
patchset 11:rebase
patchset 12:fix cme interrupt handler(marker changed)
patchset 13:fix compiler error in 12
turn on sgpe kernel trace
patchset 14:fix again
patchset 15:fix wake/stop priority group
patchset 16:fix markers for EPM
patchset 17:reformat CME PK_TRACEs
patchset 18:reformat SGPE PK_TRACEs
patchset 19:fix some typo in 18
patchset 20:fix VDM scom fail via INTERPPM settings
patchset 21:core hist in sgpe based on partial good
fix vcs workaround in stop image
add qloop limiter in sgpe exit
add stop level mapping support
patchset 22:enable vcs workaround by default
patchset 23:add dpll_initf
fix dpll_setup bit(9)
make epm skip workaround doesnt need
patchset 24:fix stop2 exit express
fix some old compiler flags
patchset 25:add dd1 doorbell workaround
add comment on serialize quad PFETs
patchset 26:fix cme_boot() on repeat booting one CME
patchset 27:increase sgpe_exit_thread stack size
patchset 28:sdis_n set/reset becomes permanent
patchset 29:add skewadjust procedures
patchset 30:add queue scom mode init
patchset 31:using ppe_scom instead of fapi_scom
patchset 32:continue protect cme on partial bad core
patchset 33:add support for EX_L3_MODE_REG1 setup
patchset 34:using real time qcsr for l3-lco victem
patchset 35:fix a bug in patchset 32
patchset 36:Increased the CME/SGPE Hcode defines.
Change-Id: Id3fd4d4e0d9740a7903c913fa8fc80b6cee55ff9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30925
Dev-Ready: YUE DU <daviddu@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Diffstat (limited to 'import/chips')
31 files changed, 1460 insertions, 612 deletions
diff --git a/import/chips/p9/common/pmlib/include/p9_stop_common.h b/import/chips/p9/common/pmlib/include/p9_stop_common.h index 876ca7fa..f362e36e 100644 --- a/import/chips/p9/common/pmlib/include/p9_stop_common.h +++ b/import/chips/p9/common/pmlib/include/p9_stop_common.h @@ -28,8 +28,11 @@ enum P9_HCD_COMMON_CLK_CTRL_CONSTANTS { CLK_STOP_CMD = BIT64(0), CLK_START_CMD = BIT64(1), + CLK_REGION_PERV = BIT64(4), CLK_REGION_ANEP = BIT64(10), CLK_REGION_DPLL = BIT64(14), + CLK_REGION_EX0_L2 = BIT64(8), + CLK_REGION_EX1_L2 = BIT64(9), CLK_REGION_EX0_L2_L3_REFR = BIT64(6) | BIT64(8) | BIT64(12), CLK_REGION_EX1_L2_L3_REFR = BIT64(7) | BIT64(9) | BIT64(13), CLK_REGION_ALL_BUT_EX = BITS64(4, 2) | BITS64(10, 2) | BIT64(14), @@ -37,9 +40,29 @@ enum P9_HCD_COMMON_CLK_CTRL_CONSTANTS CLK_REGION_ALL_BUT_EX_ANEP_DPLL = BITS64(4, 2) | BIT64(11), CLK_REGION_ALL_BUT_PLL = BITS64(4, 10), CLK_REGION_ALL = BITS64(4, 11), + CLK_THOLD_SL = BIT64(48), + CLK_THOLD_NSL = BIT64(49), + CLK_THOLD_ARY = BIT64(50), CLK_THOLD_ALL = BITS64(48, 3) }; +// Scan Type Constants +enum P9_HCD_COMMON_SCAN_TYPE_CONSTANTS +{ + SCAN_TYPE_FUNC = BIT64(48), + SCAN_TYPE_CFG = BIT64(49), + SCAN_TYPE_CCFG_GPTR = BIT64(50), + SCAN_TYPE_REGF = BIT64(51), + SCAN_TYPE_LBIST = BIT64(52), + SCAN_TYPE_ABIST = BIT64(53), + SCAN_TYPE_REPR = BIT64(54), + SCAN_TYPE_TIME = BIT64(55), + SCAN_TYPE_BNDY = BIT64(56), + SCAN_TYPE_FARR = BIT64(57), + SCAN_TYPE_CMSK = BIT64(58), + SCAN_TYPE_INEX = BIT64(59) +}; + // SCAN0 Constants enum P9_HCD_COMMON_SCAN0_CONSTANTS { diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index dd668679..aea5a525 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -320,7 +320,7 @@ enum SGPE_IMG_HEADER = sizeof(sgpeHeader_t), SGPE_DBG_PTR_AREA_SIZE = 64, //SGPE_HCODE_SIZE = 32 * ONE_KB, // FIXME RTC 155018 Revisit after Hcode optimization - SGPE_HCODE_SIZE = 42 * ONE_KB, // @todo RTC 158543 Reallocate space + SGPE_HCODE_SIZE = 45 * ONE_KB, // @todo RTC 158543 Reallocate space SGPE_EXE_SIZE = (SGPE_HCODE_SIZE - ( SGPE_INT_VECT + SGPE_IMG_HEADER + PK_DBG_PTR_AREA_SIZE )), @@ -371,7 +371,7 @@ enum CME_INT_VECTOR_SIZE = 384, CME_IMG_HEADER_SIZE = 64, CPMR_CME_HCODE_OFFSET = (CORE_SCOM_START + CORE_SCOM_RES_SIZE), - CME_HCODE_SIZE = (27 * ONE_KB) + HALF_KB, + CME_HCODE_SIZE = (28 * ONE_KB) + HALF_KB, //** Scan CORE_COMMON_RING_SIZE = 3 * ONE_KB, // common ring( 2KB) + common overrides (1KB) diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h index 45fc7a21..fc60c76b 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h @@ -80,12 +80,12 @@ extern const uint64_t ext_irq_vectors_cme[NUM_EXT_IRQ_PRTY_LEVELS][2]; // Group0: Non-task hi-prty IRQs #define IRQ_VEC_PRTY0_CME (uint64_t)(0xFE00000000000000) -// Group1: DB3 +// Group1: BCE+DB3 #define IRQ_VEC_PRTY1_CME (uint64_t)(0x0030000000000000) -// Group2: DB2 -#define IRQ_VEC_PRTY2_CME (uint64_t)(0x0000300000000000) -// Group3: WAKEUP + STOP -#define IRQ_VEC_PRTY3_CME (uint64_t)(0x000FCC0000000000) +// Group2: WAKE+DB2 +#define IRQ_VEC_PRTY2_CME (uint64_t)(0x000FF00000000000) +// Group3: STOP +#define IRQ_VEC_PRTY3_CME (uint64_t)(0x00000C0000000000) // Group4: DB1 #define IRQ_VEC_PRTY4_CME (uint64_t)(0x0000000000C00000) // Group5: DB0 diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c index 4b7559c7..3f9a9912 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c @@ -26,6 +26,7 @@ #include "pk.h" #include "p9_cme_irq.h" #include "p9_cme_flags.h" +#include "p9_hcode_image_defines.H" // CME Pstate Header and Structure #include "p9_cme_pstate.h" @@ -55,23 +56,23 @@ IRQ_HANDLER_DEFAULT //CMEHW_IRQ_BCE_BUSY_HIGH IRQ_HANDLER_DEFAULT //CMEHW_IRQ_BCE_TIMEOUT IRQ_HANDLER_DEFAULT //CMEHW_IRQ_DOORBELL3_C0 IRQ_HANDLER_DEFAULT //CMEHW_IRQ_DOORBELL3_C1 -IRQ_HANDLER(p9_cme_stop_event_handler, (void*) & (G_cme_stop_record.sem[1])) +IRQ_HANDLER(p9_cme_stop_exit_handler, (void*) & (G_cme_stop_record.sem[1])) //CMEHW_IRQ_PC_INTR_PENDING_C0 -IRQ_HANDLER(p9_cme_stop_event_handler, (void*) & (G_cme_stop_record.sem[1])) +IRQ_HANDLER(p9_cme_stop_exit_handler, (void*) & (G_cme_stop_record.sem[1])) //CMEHW_IRQ_PC_INTR_PENDING_C1 -IRQ_HANDLER(p9_cme_stop_event_handler, (void*) & (G_cme_stop_record.sem[1])) +IRQ_HANDLER(p9_cme_stop_exit_handler, (void*) & (G_cme_stop_record.sem[1])) //CMEHW_IRQ_REG_WAKEUP_C0 -IRQ_HANDLER(p9_cme_stop_event_handler, (void*) & (G_cme_stop_record.sem[1])) +IRQ_HANDLER(p9_cme_stop_exit_handler, (void*) & (G_cme_stop_record.sem[1])) //CMEHW_IRQ_REG_WAKEUP_C1 -IRQ_HANDLER(p9_cme_stop_event_handler, (void*) & (G_cme_stop_record.sem[1])) +IRQ_HANDLER(p9_cme_stop_exit_handler, (void*) & (G_cme_stop_record.sem[1])) //CMEHW_IRQ_SPECIAL_WAKEUP_C0 -IRQ_HANDLER(p9_cme_stop_event_handler, (void*) & (G_cme_stop_record.sem[1])) +IRQ_HANDLER(p9_cme_stop_exit_handler, (void*) & (G_cme_stop_record.sem[1])) //CMEHW_IRQ_SPECIAL_WAKEUP_C1 IRQ_HANDLER(p9_cme_stop_db2_handler, 0) //CMEHW_IRQ_DOORBELL2_C0 IRQ_HANDLER(p9_cme_stop_db2_handler, 0) //CMEHW_IRQ_DOORBELL2_C1 -IRQ_HANDLER(p9_cme_stop_event_handler, (void*) & (G_cme_stop_record.sem[0])) +IRQ_HANDLER(p9_cme_stop_enter_handler, (void*) & (G_cme_stop_record.sem[0])) //CMEHW_IRQ_PC_PM_STATE_ACTIVE_C0 -IRQ_HANDLER(p9_cme_stop_event_handler, (void*) & (G_cme_stop_record.sem[0])) +IRQ_HANDLER(p9_cme_stop_enter_handler, (void*) & (G_cme_stop_record.sem[0])) //CMEHW_IRQ_PC_PM_STATE_ACTIVE_C1 IRQ_HANDLER_DEFAULT //CMEHW_IRQ_L2_PURGE_DONE IRQ_HANDLER_DEFAULT //CMEHW_IRQ_NCU_PURGE_DONE @@ -168,6 +169,19 @@ main(int argc, char** argv) PK_TRACE("Kernel init completed"); + // reading header attributes and initialize the queued scom mode + cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_BASE + CME_HEADER_IMAGE_OFFSET); + G_cme_stop_record.header_flags = pCmeImgHdr->g_cme_mode_flags; + + if (G_cme_stop_record.header_flags & QUEUED_SCAN_DISABLE) + { + out32(CME_LCL_LMCR_CLR, BITS32(8, 2)); + } + else + { + out32(CME_LCL_LMCR_OR, BITS32(8, 2)); + } + // Unified interrupt handler checks if (IDX_PRTY_LVL_DISABLED != (NUM_EXT_IRQ_PRTY_LEVELS - 1)) { diff --git a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h index 1a2b1433..4fd3cc7c 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h +++ b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h @@ -34,53 +34,68 @@ /// \brief Application specific overrides go here. /// -#define HW386841_PLS_SRR1_DSL_STOP1_FIX 0 -#define BROADSIDE_SCAN0 0 -#define TEST_ONLY_BCE_IRR 0 +// @todo RTC 161182 +#define HW386841_DD1_PLS_SRR1_DSL_STOP1_FIX 0 +#define TEST_ONLY_BCE_IRR 0 + +// -------------------- + +#ifndef EPM_P9_TUNING + #define EPM_P9_TUNING 0 +#endif #define STOP_PRIME 0 #define SKIP_ABORT 0 #define SKIP_L2_PURGE_ABORT 0 #define SKIP_ENTRY_CATCHUP 0 -#define ISTEP15_HACK 1 - -#if !ISTEP15_HACK - #define SKIP_EXIT_CATCHUP 0 - #define EPM_P9_TUNING 1 - #define SKIP_SCAN0 0 - #define SKIP_INITF 0 - #define SKIP_SELF_RESTORE 0 - #define SKIP_RAM_HRMOR 0 +#define SKIP_EXIT_CATCHUP 0 +#define SKIP_ARRAYINIT 0 +#define SKIP_SCAN0 0 +#define SKIP_INITF 0 +#define SKIP_SELF_RESTORE 0 +#define SKIP_RAM_HRMOR 0 + +#if EPM_P9_TUNING + #define SPWU_AUTO 1 #define SKIP_BCE_SCAN_RING 1 #define SKIP_BCE_SCOM_RESTORE 1 - #define SPWU_AUTO 1 - #define SKIP_ARRAYINIT 0 + #define EPM_BROADSIDE_SCAN0 0 #else - #define SKIP_EXIT_CATCHUP 1 - #define EPM_P9_TUNING 0 - #define SKIP_SCAN0 0 - #define SKIP_INITF 0 - #define SKIP_SELF_RESTORE 0 - #define SKIP_RAM_HRMOR 0 + #define SPWU_AUTO 0 #define SKIP_BCE_SCAN_RING 0 #define SKIP_BCE_SCOM_RESTORE 1 - #define SPWU_AUTO 0 - #define SKIP_ARRAYINIT 0 + #define EPM_BROADSIDE_SCAN0 0 #endif - // -------------------- -#define SIMICS_TUNING 0 -#define USE_SIMICS_IO 0 -#define DEV_DEBUG 1 +#define PK_TRACE_LEVEL 2 + +#if PK_TRACE_LEVEL == 0 /*No TRACEs*/ + #define PK_TRACE_ENABLE 0 + #define PK_KERNEL_TRACE_ENABLE 0 +#elif PK_TRACE_LEVEL == 1 /*only PK_TRACE_INF*/ + #define PK_TRACE_ENABLE 1 + #define PK_TRACE_CRIT_ENABLE 1 + #define PK_TRACE_DBG_SUPPRESS 1 + #define PK_KERNEL_TRACE_ENABLE 0 +#else /*All TRACEs*/ + #define PK_TRACE_ENABLE 1 + #define PK_TRACE_CRIT_ENABLE 1 + #define PK_TRACE_DBG_SUPPRESS 0 + #define PK_KERNEL_TRACE_ENABLE 1 +#endif #if EPM_P9_TUNING #define PK_TRACE_BUFFER_WRAP_MARKER 1 #endif -#define PK_TRACE_TIMER_OUTPUT 0 -#define PK_TRACE_ENABLE 1 -#define PK_KERNEL_TRACE_ENABLE 1 +#define PK_TRACE_TIMER_OUTPUT 0 + +// -------------------- + +#define SIMICS_TUNING 0 +#define USE_SIMICS_IO 0 +#define DEV_DEBUG 1 // -------------------- diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h index 32ee95fd..247dec5e 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h @@ -138,7 +138,7 @@ (((uint64_t)pls) << SHIFT64(60)) | ((uint64_t)srr1_t3) | \ (BIT64(32) | BIT64(40) | BIT64(48) | BIT64(56))) -#if HW386841_PLS_SRR1_DLS_STOP1_FIX +#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX #define CME_STOP_UPDATE_DLS(dls, srr1) \ ((((uint64_t)dls.threads.t0) << SHIFT64(36)) | (((uint64_t)srr1[0]) << SHIFT64(39)) | \ (((uint64_t)dls.threads.t1) << SHIFT64(44)) | (((uint64_t)srr1[1]) << SHIFT64(47)) | \ @@ -172,12 +172,22 @@ enum CME_STOP_IRQ_SHORT_NAME enum CME_IRQ_VECTORS { +// if auto mask eimr.spwu else never mask eimr.spwu +#if SPWU_AUTO IRQ_VEC_WAKE_C0 = BIT64(12) | BIT64(14) | BIT64(16), IRQ_VEC_WAKE_C1 = BIT64(13) | BIT64(15) | BIT64(17), +#else + IRQ_VEC_WAKE_C0 = BIT64(12) | BIT64(16), + IRQ_VEC_WAKE_C1 = BIT64(13) | BIT64(17), +#endif IRQ_VEC_SGPE_C0 = BIT64(12) | BIT64(20), IRQ_VEC_SGPE_C1 = BIT64(13) | BIT64(21), IRQ_VEC_PCWU_C0 = BIT64(12), IRQ_VEC_PCWU_C1 = BIT64(13), + IRQ_VEC_SPWU_C0 = BIT64(14), + IRQ_VEC_SPWU_C1 = BIT64(15), + IRQ_VEC_RGWU_C0 = BIT64(16), + IRQ_VEC_RGWU_C1 = BIT64(17), IRQ_VEC_STOP_C0 = BIT64(20), IRQ_VEC_STOP_C1 = BIT64(21) }; @@ -195,6 +205,17 @@ enum CME_STOP_FLAGS FLAG_PARTIAL_GOOD_C1 = BIT32(31) }; +enum ATTR_CME_MODE_FLAGS +{ + MAP_3_TO_2 = BIT32(0), + MAP_4_TO_2 = BIT32(1), + MAP_5_TO_4 = BIT32(2), + MAP_8_TO_5 = BIT32(3), + MAP_11_TO_8 = BIT32(4), + QUEUED_SCAN_DISABLE = BIT32(30), + SKIP_CORE_POWEROFF = BIT32(31) +}; + enum CME_STOP_PIG_TYPES { PIG_TYPE2 = 2, @@ -215,7 +236,7 @@ enum CME_STOP_SRR1 NO_STATE_LOSS = 1 }; -#if HW386841_PLS_SRR1_DLS_STOP1_FIX +#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX typedef union { uint16_t vector; @@ -274,6 +295,10 @@ typedef struct uint32_t core_stopgpe; // core in block wakeup mode uint32_t core_blockwu; + // core in special wakeup + uint32_t core_in_spwu; + // cme header attributes + uint32_t header_flags; PkSemaphore sem[2]; } CmeStopRecord; @@ -284,7 +309,9 @@ void p9_cme_stop_exit_thread(void*); int p9_cme_stop_entry(); int p9_cme_stop_exit(); -void p9_cme_stop_event_handler(void*, PkIrqId); +void p9_cme_stop_enter_handler(void*, PkIrqId); +void p9_cme_stop_exit_handler(void*, PkIrqId); +void p9_cme_stop_spwu_handler(void*, PkIrqId); void p9_cme_stop_db1_handler(void*, PkIrqId); void p9_cme_stop_db2_handler(void*, PkIrqId); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_enter_marks.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_enter_marks.h index 5ee4326a..4a049ea9 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_enter_marks.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_enter_marks.h @@ -38,9 +38,10 @@ enum CME_SE_MARKS { BEGINSCOPE_STOP_ENTRY = 0x0, ENDSCOPE_STOP_ENTRY = 0x8, - STOP_EVENT_HANDLER = 0x10, - STOP_DB1_HANDLER = 0x18, - STOP_DB2_HANDLER = 0x20, + STOP_ENTER_HANDLER = 0x10, + STOP_EXIT_HANDLER = 0x18, + STOP_DB1_HANDLER = 0x20, + STOP_DB2_HANDLER = 0x28, SE_QUIESCE_CORE_INTF = 0x68, SE_STOP_CORE_CLKS = 0xe0, SE_STOP_CORE_GRID = 0xe8, @@ -67,7 +68,8 @@ const std::vector<CME_SE_MARKS> MARKS = { BEGINSCOPE_STOP_ENTRY, ENDSCOPE_STOP_ENTRY, - STOP_EVENT_HANDLER, + STOP_ENTER_HANDLER, + STOP_EXIT_HANDLER, STOP_DB1_HANDLER, STOP_DB2_HANDLER, SE_QUIESCE_CORE_INTF, @@ -92,7 +94,8 @@ const std::vector<CME_SE_MARKS> MARKS = const std::map<CME_SE_MARKS, std::string> mMARKS = boost::assign::map_list_of (BEGINSCOPE_STOP_ENTRY, "BEGINSCOPE_STOP_ENTRY") (ENDSCOPE_STOP_ENTRY, "ENDSCOPE_STOP_ENTRY") - (STOP_EVENT_HANDLER, "STOP_EVENT_HANDLER") + (STOP_ENTER_HANDLER, "STOP_ENTER_HANDLER") + (STOP_EXIT_HANDLER, "STOP_EXIT_HANDLER") (STOP_DB1_HANDLER, "STOP_DB1_HANDLER") (STOP_DB2_HANDLER, "STOP_DB2_HANDLER") (SE_QUIESCE_CORE_INTF, "SE_QUIESCE_CORE_INTF") diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index 43e3f4fb..6ec1b08e 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -70,7 +70,7 @@ p9_cme_stop_entry() ppm_pig_t pig; //-------------------------------------------------------------------------- - // BEGIN OF STOP ENTRY + PK_TRACE_INF("+++++ +++++ BEGIN OF STOP ENTRY +++++ +++++"); //-------------------------------------------------------------------------- // First we need to determine which of the two STOP interrupts fired. @@ -84,14 +84,13 @@ p9_cme_stop_entry() core = core & G_cme_stop_record.core_enabled & G_cme_stop_record.core_running; - PK_TRACE("SE0: Core Select[%d] Enabled[%d] Running[%d]", - core, G_cme_stop_record.core_enabled, - G_cme_stop_record.core_running); + PK_TRACE_INF("Check: Core Select[%d] Enabled[%d] Running[%d]", + core, G_cme_stop_record.core_enabled, + G_cme_stop_record.core_running); - // Return error if None of both fired if (!core) { - PK_TRACE("Error: no pm_active fired"); + PK_TRACE_INF("ERROR: No PM_ACTIVE Fired From a Running and Enabled Core. HALT CME!"); pk_halt(); } @@ -102,10 +101,6 @@ p9_cme_stop_entry() do // while(0) loop for stop flow control { - //---------------------------------------------------------------------- - // STOP LEVEL 1 (should be done by hardware) - //---------------------------------------------------------------------- - // Read SISR for pm_state_cX pm_states = in32_sh(CME_LCL_SISR); @@ -136,6 +131,31 @@ p9_cme_stop_entry() G_cme_stop_record.act_level_c0 = STOP_LEVEL_1; core_stop1 |= CME_MASK_C0; } + + if ((G_cme_stop_record.header_flags & MAP_11_TO_8) && + (G_cme_stop_record.req_level_c0 == STOP_LEVEL_11)) + { + + G_cme_stop_record.req_level_c0 = STOP_LEVEL_8; + } + + if ((G_cme_stop_record.header_flags & MAP_8_TO_5) && + (G_cme_stop_record.req_level_c0 == STOP_LEVEL_8)) + { + G_cme_stop_record.req_level_c0 = STOP_LEVEL_5; + } + + if ((G_cme_stop_record.header_flags & MAP_5_TO_4) && + (G_cme_stop_record.req_level_c0 == STOP_LEVEL_5)) + { + G_cme_stop_record.req_level_c0 = STOP_LEVEL_4; + } + + if ((G_cme_stop_record.header_flags & MAP_4_TO_2) && + (G_cme_stop_record.req_level_c0 == STOP_LEVEL_4)) + { + G_cme_stop_record.req_level_c0 = STOP_LEVEL_2; + } } if (core & CME_MASK_C1) @@ -148,24 +168,56 @@ p9_cme_stop_entry() G_cme_stop_record.act_level_c1 = STOP_LEVEL_1; core_stop1 |= CME_MASK_C1; } + + if ((G_cme_stop_record.header_flags & MAP_11_TO_8) && + (G_cme_stop_record.req_level_c1 == STOP_LEVEL_11)) + { + G_cme_stop_record.req_level_c1 = STOP_LEVEL_8; + } + + if ((G_cme_stop_record.header_flags & MAP_8_TO_5) && + (G_cme_stop_record.req_level_c1 == STOP_LEVEL_8)) + { + G_cme_stop_record.req_level_c1 = STOP_LEVEL_5; + } + + if ((G_cme_stop_record.header_flags & MAP_5_TO_4) && + (G_cme_stop_record.req_level_c1 == STOP_LEVEL_5)) + { + G_cme_stop_record.req_level_c1 = STOP_LEVEL_4; + } + + if ((G_cme_stop_record.header_flags & MAP_4_TO_2) && + (G_cme_stop_record.req_level_c1 == STOP_LEVEL_4)) + { + G_cme_stop_record.req_level_c1 = STOP_LEVEL_2; + } } - G_cme_stop_record.core_running &= ~core; + PK_TRACE_INF("Check: Stop Levels Request[%d %d] Actual[%d, %d]", + G_cme_stop_record.req_level_c0, + G_cme_stop_record.req_level_c1, + G_cme_stop_record.act_level_c0, + G_cme_stop_record.act_level_c1); - PK_TRACE("SE1: Stop Levels Request[%d %d] Actual[%d, %d]", - G_cme_stop_record.req_level_c0, - G_cme_stop_record.req_level_c1, - G_cme_stop_record.act_level_c0, - G_cme_stop_record.act_level_c1); + // Mark core as to be stopped + G_cme_stop_record.core_running &= ~core; - // Return error if target STOP level == 1(Nap) if(core_stop1) { -#if HW386841_PLS_SRR1_DLS_STOP1_FIX - // Acknowledge the STOP Entry to PC with a pulse + PK_TRACE_INF("Check: core[%d] core_stop1[%d]", core, core_stop1); + +#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX + + //---------------------------------------------------------------------- + PK_TRACE_INF("+++++ +++++ STOP LEVEL 1 ENTRY +++++ +++++"); + //---------------------------------------------------------------------- + + PK_TRACE("Pulse STOP entry acknowledgement to PC via SICR[0/1]"); out32(CME_LCL_SICR_OR, core_stop1 << SHIFT32(1)); out32(CME_LCL_SICR_CLR, core_stop1 << SHIFT32(1)); + PK_TRACE("Update STOP history: in core stop level 1"); CME_STOP_UPDATE_HISTORY(core_stop1, STOP_CORE_IS_GATED, STOP_TRANS_COMPLETE, @@ -182,25 +234,24 @@ p9_cme_stop_entry() } #else - PK_TRACE("Error: stop 1 requested to hcode"); + + // Nap should be done by hardware when auto_stop1 is enabled + // Halt on error if target STOP level == 1(Nap) + PK_TRACE_INF("ERROR: Stop 1 Requested to CME When AUTO_STOP1 Enabled, HALT CME!"); pk_halt(); + #endif + } //---------------------------------------------------------------------- - // STOP LEVEL 2 + PK_TRACE_INF("+++++ +++++ STOP LEVEL 2 ENTRY +++++ +++++"); //---------------------------------------------------------------------- - PK_TRACE("SE2.c"); - // Request PCB Mux + PK_TRACE("Request PCB mux via SICR[10/11]"); out32(CME_LCL_SICR_OR, core << SHIFT32(11)); - PK_TRACE("SE2.d"); - // Protect PPM Register Write - CME_PUTSCOM(CPPM_CPMMR_OR, core, BIT64(0)); - - PK_TRACE("SE2.g"); - // Acknowledge the STOP Entry to PC with a pulse + PK_TRACE("Pulse STOP entry acknowledgement to PC via SICR[0/1]"); out32(CME_LCL_SICR_OR, core << SHIFT32(1)); out32(CME_LCL_SICR_CLR, core << SHIFT32(1)); @@ -225,8 +276,7 @@ p9_cme_stop_entry() } } - PK_TRACE("SE2.e"); - // Update STOP History: In Transition of Entry + PK_TRACE("Update STOP history: in transition of entry"); // Set req_level_level to target_level of either both or just one core CME_STOP_UPDATE_HISTORY(core, STOP_CORE_READY_RUN, @@ -248,30 +298,31 @@ p9_cme_stop_entry() STOP_ACT_DISABLE); } - PK_TRACE("SE2: core[%d], target_lv[%d], deeper_lv[%d], deeper_core[%d]", - core, target_level, deeper_level, deeper_core); + PK_TRACE_INF("Check: core[%d] target_lv[%d] deeper_lv[%d] deeper_core[%d]", + core, target_level, deeper_level, deeper_core); // Poll Infinitely for PCB Mux Grant // MF: change watchdog timer in pk to ensure forward progress while((core & (in32(CME_LCL_SISR) >> SHIFT32(11))) != core); - PK_TRACE("SE2: PCB Mux Granted"); + PK_TRACE_INF("SE2.A: PCB Mux Granted"); //============================= MARK_TRAP(SE_QUIESCE_CORE_INTF) //============================= - /// Set LMCR bits 12/13, 14/15 (override disables) + PK_TRACE("Assert halt STOP override disable via LMCR[14/15]"); out32(CME_LCL_LMCR_OR, (core << SHIFT32(15))); + #if SPWU_AUTO + PK_TRACE("Assert auto special wakeup disable via LMCR[12/13]"); out32(CME_LCL_LMCR_OR, (core << SHIFT32(13))); #endif - PK_TRACE("SE2.h"); - // Raise Core-L2 + Core-CC Quiesces + PK_TRACE("Assert core-L2 + core-CC quiesces via SICR[6/7,8/9]"); out32(CME_LCL_SICR_OR, (core << SHIFT32(7)) | (core << SHIFT32(9))); - PK_TRACE("SE2.i"); + PK_TRACE("Poll for L2 interface quiesced via SISR[30/31]"); do { @@ -283,25 +334,24 @@ p9_cme_stop_entry() // MF: verify generate FCB otherwise math is wrong. PPE_WAIT_CORE_CYCLES(loop, 512) + PK_TRACE_INF("SE2.B: Interfaces Quiesced"); + //========================== MARK_TRAP(SE_STOP_CORE_CLKS) //========================== - PK_TRACE("SE2.j"); - // Raise Core Chiplet Fence + PK_TRACE("Assert core chiplet fence via NET_CTRL0[18]"); CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(18)); - PK_TRACE("SE2.k"); - // Set all bits to zero prior stop core clocks + PK_TRACE("Clear SCAN_REGION_TYPE prior to stop core clocks"); CME_PUTSCOM(C_SCAN_REGION_TYPE, core, 0); - PK_TRACE("SE2.l"); - // Stop Core Clocks - CME_PUTSCOM(C_CLK_REGION, core, (CLK_STOP_CMD | CLK_REGION_ALL_BUT_PLL | CLK_THOLD_ALL)); + PK_TRACE("Stop Core Clocks via CLK_REGION"); + CME_PUTSCOM(C_CLK_REGION, core, + (CLK_STOP_CMD | CLK_REGION_ALL_BUT_PLL | CLK_THOLD_ALL)); - PK_TRACE("SE2.m"); + PK_TRACE("Poll for core clocks stopped via CPLT_STAT0[8]"); - // Poll for core clocks stopped do { CME_GETSCOM(C_CPLT_STAT0, core, CME_SCOM_AND, scom_data); @@ -313,52 +363,51 @@ p9_cme_stop_entry() if (((~scom_data) & CLK_REGION_ALL_BUT_PLL) != 0) { - PK_TRACE("Core clock stop failed"); + PK_TRACE_INF("ERROR: Core Clock Stop Failed. HALT CME!"); pk_halt(); } // MF: verify compiler generate single rlwmni // MF: delay may be needed for stage latch to propagate thold - PK_TRACE("SE2: Core Clock Stopped"); + PK_TRACE_INF("SE2.C: Core Clock Stopped"); //============================== MARK_TRAP(SE_STOP_CORE_GRID) //============================== - PK_TRACE("SE2.n"); - // Drop clock sync enable before switch to refclk + PK_TRACE("Drop clock sync enable before switch to refclk via CACCR[15]"); CME_PUTSCOM(CPPM_CACCR_CLR, core, BIT64(15)); - PK_TRACE("SE2.o"); + PK_TRACE("Poll for clock sync done to drop via CACSR[13]"); - // Poll for clock sync done to drop do { CME_GETSCOM(CPPM_CACSR, core, CME_SCOM_OR, scom_data); } while(scom_data & BIT64(13)); - PK_TRACE("SE2.p"); - // Switch glsmux to refclk to save clock grid power + PK_TRACE("Switch glsmux to refclk to save clock grid power via CGCR[3]"); CME_PUTSCOM(C_PPM_CGCR, core, 0); - // Assert skew sense to skewadjust Fence + PK_TRACE("Assert skew sense to skewadjust fence via NET_CTRL0[22]"); CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(22)); - // Assert Vital Fence + + PK_TRACE("Assert vital fence via CPLT_CTRL1[3]"); CME_PUTSCOM(C_CPLT_CTRL1_OR, core, BIT64(3)); - // Assert Regional Fences + + PK_TRACE("Assert regional fences via CPLT_CTRL1[4-13]"); CME_PUTSCOM(C_CPLT_CTRL1_OR, core, BITS64(4, 11)); - /// @todo add DD1 attribute control - PK_TRACE("DD1 only: reset sdis_n(flushing LCBES condition workaround"); + + PK_TRACE("Drop sdis_n(flushing LCBES condition) via CPLT_CONF0[34]"); CME_PUTSCOM(C_CPLT_CONF0_CLEAR, core, BIT64(34)); + /// @todo add VDM_ENABLE attribute control PK_TRACE("Drop vdm enable via CPPM_VDMCR[0]"); CME_PUTSCOM(PPM_VDMCR_CLR, core, BIT64(0)); - PK_TRACE("SE2: Clock Sync Dropped"); + PK_TRACE("Copy PECE CME sample to PPM Shadow via PECES"); - // Copy PECE CME sample to PPM Shadow if (core & CME_MASK_C0) { scom_data = in64(CME_LCL_PECESR0); @@ -373,12 +422,13 @@ p9_cme_stop_entry() G_cme_stop_record.act_level_c1 = STOP_LEVEL_2; } + PK_TRACE_INF("SE2.D: Clock Sync Dropped"); + //=========================== MARK_TAG(SE_STOP2_DONE, core) //=========================== - PK_TRACE("SE2.q"); - // Update Stop History: In Core Stop Level 2 + PK_TRACE("Update STOP history: in core stop level 2"); // Check if STOP level 2 reaches the target for both or one core entry_ongoing = target_level == STOP_LEVEL_2 ? @@ -472,8 +522,8 @@ p9_cme_stop_entry() //======================== } - PK_TRACE("core[%d] running[%d] core_catchup[%d] origin_core[%d]", - core, G_cme_stop_record.core_running, core_catchup, origin_core); + PK_TRACE_INF("Catch: core[%d] running[%d] core_catchup[%d] origin_core[%d]", + core, G_cme_stop_record.core_running, core_catchup, origin_core); #endif @@ -492,6 +542,7 @@ p9_cme_stop_entry() //=========================== MARK_TRAP(SE_IS0_BEGIN) //=========================== + #if !SKIP_ABORT out32(CME_LCL_EIMR_CLR, (core << SHIFT32(13)) | (core << SHIFT32(15)) | @@ -501,6 +552,7 @@ p9_cme_stop_entry() (core << SHIFT32(15)) | (core << SHIFT32(17))); #endif + //=================== MARK_TRAP(SE_IS0_END) //=================== @@ -508,8 +560,8 @@ p9_cme_stop_entry() core_aborted = core & G_cme_stop_record.core_running; core = core & ~G_cme_stop_record.core_running; - PK_TRACE("core[%d] running[%d] core_aborted[%d]", - core, G_cme_stop_record.core_running, core_aborted); + PK_TRACE_INF("Abort: core[%d] running[%d] core_aborted[%d]", + core, G_cme_stop_record.core_running, core_aborted); if (!core) { @@ -528,12 +580,11 @@ p9_cme_stop_entry() deeper_core = 0; } - PK_TRACE("SE2+:core[%d],deeper_core[%d],\ - target_level[%d],deeper_level[%d]", - core, deeper_core, target_level, deeper_level); + PK_TRACE_INF("Check: core[%d] deeper_core[%d] target_level[%d] deeper_level[%d]", + core, deeper_core, target_level, deeper_level); //---------------------------------------------------------------------- - // STOP LEVEL 3 + PK_TRACE_INF("+++++ +++++ STOP LEVEL 3 ENTRY +++++ +++++"); //---------------------------------------------------------------------- if (target_level == 3) @@ -608,34 +659,34 @@ p9_cme_stop_entry() } //---------------------------------------------------------------------- - // STOP LEVEL 4 + PK_TRACE_INF("+++++ +++++ STOP LEVEL 4 ENTRY +++++ +++++"); //---------------------------------------------------------------------- //=============================== MARK_TAG(SE_POWER_OFF_CORE, core) //=============================== - // DD: Assert Cores Vital Thold/PCB Fence/Electrical Fence - PK_TRACE("SE4.a"); + PK_TRACE("Assert PCB fence via NET_CTRL0[25]"); CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(25)); + + PK_TRACE("Assert electrical fence via NET_CTRL0[26]"); CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(26)); + + PK_TRACE("Assert vital thold via NET_CTRL0[16]"); CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(16)); #if !STOP_PRIME - // Prepare PFET Controls + PK_TRACE("Drop vdd_pfet_val/sel_override/regulation_finger_en via PFCS[4,5,8]"); // vdd_pfet_val/sel_override = 0 (disbaled) // vdd_pfet_regulation_finger_en = 0 (controled by FSM) - PK_TRACE("SE4.c"); CME_PUTSCOM(PPM_PFCS_CLR, core, BIT64(4) | BIT64(5) | BIT64(8)); - // Power Off Core VDD + PK_TRACE("Power off core VDD via PFCS[0-1]"); // vdd_pfet_force_state = 01 (Force Voff) - PK_TRACE("SE4.d"); CME_PUTSCOM(PPM_PFCS_OR, core, BIT64(1)); - // Poll for power gate sequencer state: 0x8 (FSM Idle) - PK_TRACE("SE4.e"); + PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle) via PFCS[42]"); do { @@ -643,15 +694,12 @@ p9_cme_stop_entry() } while(!(scom_data & BIT64(42))); - // Turn Off Force Voff + PK_TRACE("Turn off force voff via PFCS[0-1]"); // vdd_pfet_force_state = 00 (Nop) - PK_TRACE("SE4.g"); CME_PUTSCOM(PPM_PFCS_CLR, core, BITS64(0, 2)); #endif - PK_TRACE("SE4: Core Powered Off"); - if (core & CME_MASK_C0) { G_cme_stop_record.act_level_c0 = STOP_LEVEL_4; @@ -662,12 +710,13 @@ p9_cme_stop_entry() G_cme_stop_record.act_level_c1 = STOP_LEVEL_4; } + PK_TRACE_INF("SE4.A: Core Powered Off"); + //=========================== MARK_TAG(SE_STOP4_DONE, core) //=========================== - PK_TRACE("SE4.h"); - // Update Stop History: In Core Stop Level 4 + PK_TRACE("Update STOP history: in core stop level 4"); // Check if STOP level 4 reaches the target for both or one core entry_ongoing = target_level == STOP_LEVEL_4 ? STOP_TRANS_COMPLETE : @@ -709,6 +758,7 @@ p9_cme_stop_entry() //=========================== MARK_TRAP(SE_IS1_BEGIN) //=========================== + #if !SKIP_ABORT out32(CME_LCL_EIMR_CLR, (core << SHIFT32(13)) | (core << SHIFT32(15)) | @@ -718,6 +768,7 @@ p9_cme_stop_entry() (core << SHIFT32(15)) | (core << SHIFT32(17))); #endif + //=================== MARK_TRAP(SE_IS1_END) //=================== @@ -725,8 +776,8 @@ p9_cme_stop_entry() core_aborted = core & G_cme_stop_record.core_running; core = core & ~G_cme_stop_record.core_running; - PK_TRACE("core[%d] running[%d] core_aborted[%d]", - core, G_cme_stop_record.core_running, core_aborted); + PK_TRACE_INF("Abort: core[%d] running[%d] core_aborted[%d]", + core, G_cme_stop_record.core_running, core_aborted); if (!core) { @@ -742,15 +793,14 @@ p9_cme_stop_entry() target_level = deeper_level; } - deeper_core = 0; + deeper_core = 0; } - PK_TRACE("SE4+:core[%d],deeper_core[%d],\ - target_level[%d],deeper_level[%d]", - core, deeper_core, target_level, deeper_level); + PK_TRACE_INF("Check: core[%d] deeper_core[%d] target_level[%d] deeper_level[%d]", + core, deeper_core, target_level, deeper_level); //---------------------------------------------------------------------- - // STOP LEVEL 5 (preparsion of STOP LEVEL 8 and above) + PK_TRACE_INF("+++++ +++++ STOP LEVEL 5-7 ENTRY +++++ +++++"); //---------------------------------------------------------------------- if ((G_cme_stop_record.req_level_c0 >= STOP_LEVEL_8) && @@ -761,21 +811,20 @@ p9_cme_stop_entry() MARK_TAG(SE_PURGE_L2, CME_MASK_BC) //================================ - // Assert L2+NCU Purge and NCU tlbie quiesce - // (chtm purge will be done in SGPE), + PK_TRACE("Assert L2+NCU purge and NCU tlbie quiesce via SICR[18,21,22]"); // insert tlbie quiesce before ncu purge to avoid window condition // of ncu traffic still happening when purging starts - PK_TRACE("SE5.1a"); + // Note: chtm purge will be done in SGPE out32(CME_LCL_SICR_OR, BIT32(18) | BIT32(21)); out32(CME_LCL_SICR_OR, BIT32(22)); // todo: poll for tlbie quiesce done? - // Poll for Purged Done - PK_TRACE("SE5.1b"); + PK_TRACE("Poll for purged done via EISR[22,23]"); do { + #if !SKIP_L2_PURGE_ABORT if (!core_aborted && @@ -793,27 +842,27 @@ p9_cme_stop_entry() core_aborted |= CME_MASK_C1; } - PK_TRACE("L2 Purge aborted by core[%d]", core_aborted); //======================================= MARK_TAG(SE_PURGE_L2_ABORT, core_aborted) //======================================= - // abort L2+NCU purges + + PK_TRACE_INF("Abort: L2+NCU purge aborted by core[%d]", core_aborted); out32(CME_LCL_SICR_OR, BIT32(19) | BIT32(23)); } #endif + } while((in32(CME_LCL_EISR) & BITS32(22, 2)) != BITS32(22, 2)); - // Deassert L2+NCU Purges, their possible aborts - PK_TRACE("SE5.1c"); + PK_TRACE("Drop L2+NCU purges and their possible aborts via SICR[18,19,22,23]"); out32(CME_LCL_SICR_CLR, (BITS32(18, 2) | BITS32(22, 2))); - PK_TRACE("SE5.1: L2/NCU/CHTM Purged"); + PK_TRACE_INF("SE5.A: L2 and NCU Purged"); - //=============================================================== + //=================================================================== MARK_TAG(SE_PURGE_L2_DONE, core_aborted ? core_aborted : CME_MASK_BC) - //=============================================================== + //=================================================================== // if core = 3 aborted = 1, core = 2(sgpe handoff) aborted (cme wakeup) // if core = 1 aborted = 1, core = 0(break) aborted (cme wakeup) @@ -832,8 +881,7 @@ p9_cme_stop_entry() MARK_TAG(SE_SGPE_HANDOFF, core) //============================= - // Update Stop History: In Core Stop Level 5 - PK_TRACE("SE5.2a"); + PK_TRACE("Update STOP history: in core stop level 5"); CME_STOP_UPDATE_HISTORY(core, STOP_CORE_IS_GATED, STOP_TRANS_CORE_PORTION, @@ -842,8 +890,7 @@ p9_cme_stop_entry() STOP_REQ_DISABLE, STOP_ACT_ENABLE); - // Send PCB Interrupt per core - PK_TRACE("SE5.2b"); + PK_TRACE("Send PCB interrupt per core via PIG, select irq type via CPMMR[10]"); if (core & CME_MASK_C0) { @@ -883,22 +930,18 @@ p9_cme_stop_entry() G_cme_stop_record.act_level_c1 = STOP_LEVEL_5; } - // Change PPM Wakeup to STOPGPE - PK_TRACE("SE5.2c"); + PK_TRACE("Switch PPM wakeup to STOP-GPE via CPMMR[13]"); CME_PUTSCOM(CPPM_CPMMR_OR, core, BIT64(13)); - PK_TRACE("SE5.2: Handed off to SGPE"); + PK_TRACE_INF("SE5.2B: Handed off to SGPE"); } while(0); //-------------------------------------------------------------------------- - // END OF STOP ENTRY + PK_TRACE_INF("+++++ +++++ END OF STOP ENTRY +++++ +++++"); //-------------------------------------------------------------------------- - // Release PPM Write Protection - CME_PUTSCOM(CPPM_CPMMR_CLR, CME_MASK_BC, BIT64(0)); - //============================ MARK_TRAP(ENDSCOPE_STOP_ENTRY) //============================ diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c index a0115c85..9b73095f 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c @@ -28,8 +28,11 @@ #include "p9_cme_copy_scan_ring.h" extern CmeStopRecord G_cme_stop_record; -#if HW386841_PLS_SRR1_DLS_STOP1_FIX + +#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX + CoreThreadsInfo G_dsl[MAX_CORES_PER_CME] = {0, 0}; + #endif int @@ -51,29 +54,30 @@ p9_cme_stop_exit() uint8_t catchup_level; uint32_t core_catchup; #endif -#if HW386841_PLS_SRR1_DLS_STOP1_FIX - uint32_t core_stop1 = 0; +#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX uint8_t dsl; uint8_t thread; uint8_t G_srr1[MAX_CORES_PER_CME][MAX_THREADS_PER_CORE] = {{0, 0, 0, 0}, {0, 0, 0, 0}}; + uint32_t core_stop1 = 0; cme_scom_pscrs00_t pscrs; #endif ppm_sshsrc_t hist; - uint64_t data64; + uint64_t scom_data; //-------------------------------------------------------------------------- - // BEGIN OF STOP EXIT + PK_TRACE_INF("+++++ +++++ BEGIN OF STOP EXIT +++++ +++++"); //-------------------------------------------------------------------------- // extract wakeup signals, clear status, and mask wakeup interrupts wakeup = (in32(CME_LCL_EISR) >> SHIFT32(17)) & 0x3F; core = ((wakeup >> 4) | (wakeup >> 2) | wakeup) & CME_MASK_BC; + // ignore wakeup when it suppose to be handled by sgpe if (core & CME_MASK_C0) { - CME_GETSCOM(CPPM_CPMMR, CME_MASK_C0, CME_SCOM_AND, data64); + CME_GETSCOM(CPPM_CPMMR, CME_MASK_C0, CME_SCOM_AND, scom_data); - if (data64 & BIT64(13)) + if (scom_data & BIT64(13)) { core = core - CME_MASK_C0; } @@ -81,48 +85,55 @@ p9_cme_stop_exit() if (core & CME_MASK_C1) { - CME_GETSCOM(CPPM_CPMMR, CME_MASK_C1, CME_SCOM_AND, data64); + CME_GETSCOM(CPPM_CPMMR, CME_MASK_C1, CME_SCOM_AND, scom_data); - if (data64 & BIT64(13)) + if (scom_data & BIT64(13)) { core = core - CME_MASK_C1; } } - // override with partial good core mask - // also ignore wakeup to running cores + // override with partial good core mask, also ignore wakeup to running cores core = core & G_cme_stop_record.core_enabled & (~G_cme_stop_record.core_running); - PK_TRACE("X0: Core Select[%d] Wakeup[%x] Actual Stop Levels[%d %d]", - core, wakeup, - G_cme_stop_record.act_level_c0, - G_cme_stop_record.act_level_c1); + PK_TRACE_INF("Check: Core Select[%d] Wakeup[%x] Actual Stop Levels[%d %d]", + core, wakeup, + G_cme_stop_record.act_level_c0, + G_cme_stop_record.act_level_c1); + + #if !SPWU_AUTO + + // figure out who is already awake and who needs to exit spwu_stop = (wakeup >> 2) & G_cme_stop_record.core_enabled; spwu_wake = spwu_stop & G_cme_stop_record.core_running; spwu_stop = spwu_stop & (~G_cme_stop_record.core_running); if (spwu_wake) { - PK_TRACE("X0: setting spwu done"); + PK_TRACE_INF("SX0.A: Assert Core[%d] Special Wakeup Done via SICR[16/17]", spwu_wake); out32(CME_LCL_SICR_OR, spwu_wake << SHIFT32(17)); } #endif - // Code Error: function should never be entered without wakeup source active if (!core) { + #if !SPWU_AUTO if (!spwu_wake) { + #endif - PK_TRACE("Error: no wakeup fired"); + + PK_TRACE_INF("ERROR: No Wakeup Fired to a Stopped and Enabled Core. HALT CME!"); pk_halt(); + #if !SPWU_AUTO + } else { @@ -130,14 +141,18 @@ p9_cme_stop_exit() } #endif + } + + //================================== MARK_TAG(BEGINSCOPE_STOP_EXIT, core) //================================== -#if HW386841_PLS_SRR1_DLS_STOP1_FIX +#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX + // figure out who needs stop1 exit if ((core & CME_MASK_C0) && G_cme_stop_record.act_level_c0 == STOP_LEVEL_1) { core_stop1 |= CME_MASK_C0; @@ -148,16 +163,24 @@ p9_cme_stop_exit() core_stop1 |= CME_MASK_C1; } + PK_TRACE_INF("SX0.B: Core[%d] Requested Stop1 Exit", core_stop1); + core = core & ~core_stop1; -if (!core) goto STOP1_EXIT: + if (!core) + { + goto STOP1_EXIT; + } + #endif - // set target_level to STOP level for c0 - // unless c1(also or only) wants to wakeup - target_level = deeper_level = - (core == CME_MASK_C0) ? G_cme_stop_record.act_level_c0 : - G_cme_stop_record.act_level_c1; + + + // set target_level to STOP level for c0 + // unless c1(also or only) wants to wakeup + target_level = deeper_level = + (core == CME_MASK_C0) ? G_cme_stop_record.act_level_c0 : + G_cme_stop_record.act_level_c1; // If both cores want to wakeup but are in different STOP levels, // set deeper_level to the deeper level targeted by deeper core @@ -177,17 +200,20 @@ if (!core) goto STOP1_EXIT: } } - PK_TRACE("X0: target_lv[%d], deeper_lv[%d], deeper_c[%d]", - target_level, deeper_level, deeper_core); + PK_TRACE_INF("Check: core[%d] target_lv[%d], deeper_lv[%d], deeper_c[%d]", + core, target_level, deeper_level, deeper_core); + + + PK_TRACE("Ensure PCB mux by request anyway via SICR[10/11]"); // ensure PCB Mux grant is present for all cores that wants to wakeup - // only stop 11 needs to request for new grant + // should only stop 11 need to request for new grant out32(CME_LCL_SICR_OR, (core << SHIFT32(11))); - // chtm purge done + PK_TRACE("Clear chtm purge done via ESIR[24/25]"); out32(CME_LCL_EISR_CLR, (core << SHIFT32(25))); - PK_TRACE("X0: Update STOP History: In Transition of Exit"); + PK_TRACE("Update STOP history: in transition of exit"); CME_STOP_UPDATE_HISTORY(core, STOP_CORE_IS_GATED, STOP_TRANS_EXIT, @@ -196,16 +222,21 @@ if (!core) goto STOP1_EXIT: STOP_REQ_DISABLE, STOP_ACT_DISABLE); - PK_TRACE("X0: Check and Request PCB Mux"); + PK_TRACE("Check for PCB mux granted via SISR[10/11]"); while((core & (in32(CME_LCL_SISR) >> SHIFT32(11))) != core); - //-------------------------------------------------------------------------- - // STOP LEVEL 2 - single core express - //-------------------------------------------------------------------------- + PK_TRACE_INF("SX0.C: PCB Mux Granted"); + - if (deeper_core) + + if (deeper_core && target_level == 2) { + + //-------------------------------------------------------------------------- + PK_TRACE_INF("+++++ +++++ STOP LEVEL 2 EXIT EXPRESS +++++ +++++"); + //-------------------------------------------------------------------------- + core = CME_MASK_BC - deeper_core; //============================ @@ -214,26 +245,28 @@ if (!core) goto STOP1_EXIT: // do this again here for stop2 in addition to chiplet_reset // Note IPL doesnt need to do this twice - PK_TRACE("4S2: Set Core Glitchless Mux to DPLL"); + PK_TRACE("Assert core glitchless mux to DPLL via CGCR[3]"); CME_PUTSCOM(C_PPM_CGCR, core, BIT64(3)); - PK_TRACE("X9: Start Core Clock"); + PK_TRACE_INF("SX2.X: Start Core Clock on Core[%d]", core); p9_hcd_core_startclocks(core); - // Clear CPPM PECE Shadow + PK_TRACE("Clear CPPM PECE shadow via PECES"); CME_PUTSCOM(CPPM_PECES, core, 0); core = deeper_core; deeper_core = 0; + } - //-------------------------------------------------------------------------- - // STOP LEVEL 4 - //-------------------------------------------------------------------------- + if (deeper_level >= STOP_LEVEL_4) { - PK_TRACE("STOP Level 4+ Sequence"); + + //-------------------------------------------------------------------------- + PK_TRACE_INF("+++++ +++++ STOP LEVEL 4 EXIT +++++ +++++"); + //-------------------------------------------------------------------------- // if deeper_core is set, then core must be 0b11 if (deeper_core && target_level < STOP_LEVEL_4) @@ -246,23 +279,25 @@ if (!core) goto STOP1_EXIT: { #if !SKIP_BCE_SCOM_RESTORE - PK_TRACE("BCE Runtime Kickoff: copy scom restore"); + + PK_TRACE_INF("SX4.A: BCE Runtime Kickoff to Copy Scom Restore"); //right now a blocking call. Need to confirm this. instance_scom_restore(); + #endif //======================== MARK_TAG(SX_POWERON, core) //======================== - PK_TRACE("X1: Core Poweron"); + PK_TRACE_INF("SX4.B: Core[%d] Poweron", core); p9_hcd_core_poweron(core); //========================= MARK_TRAP(SX_CHIPLET_RESET) //========================= - PK_TRACE("X2: Core Chiplet Reset"); + PK_TRACE_INF("SX4.C: Core[%d] Chiplet Reset", core); p9_hcd_core_chiplet_reset(core); #if !STOP_PRIME @@ -283,9 +318,9 @@ if (!core) goto STOP1_EXIT: if (core_catchup & CME_MASK_C0) { - CME_GETSCOM(CPPM_CPMMR, CME_MASK_C0, CME_SCOM_AND, data64); + CME_GETSCOM(CPPM_CPMMR, CME_MASK_C0, CME_SCOM_AND, scom_data); - if (data64 & BIT64(13)) + if (scom_data & BIT64(13)) { core_catchup = core_catchup - CME_MASK_C0; } @@ -293,9 +328,9 @@ if (!core) goto STOP1_EXIT: if (core_catchup & CME_MASK_C1) { - CME_GETSCOM(CPPM_CPMMR, CME_MASK_C1, CME_SCOM_AND, data64); + CME_GETSCOM(CPPM_CPMMR, CME_MASK_C1, CME_SCOM_AND, scom_data); - if (data64 & BIT64(13)) + if (scom_data & BIT64(13)) { core_catchup = core_catchup - CME_MASK_C1; } @@ -324,9 +359,10 @@ if (!core) goto STOP1_EXIT: G_cme_stop_record.act_level_c0 : G_cme_stop_record.act_level_c1 ; - PK_TRACE("core[%d] running[%d] core_catchup[%d] catchup_level[%d]", - core, G_cme_stop_record.core_running, - core_catchup, catchup_level); + PK_TRACE_INF("Catch: core[%d] running[%d] \ + core_catchup[%d] catchup_level[%d]", + core, G_cme_stop_record.core_running, + core_catchup, catchup_level); while((core_catchup & (in32(CME_LCL_SISR) >> SHIFT32(11))) != core_catchup); @@ -350,17 +386,22 @@ if (!core) goto STOP1_EXIT: //============================== MARK_TAG(SX_CHIPLET_INITS, core) //============================== + #if !SKIP_INITF - PK_TRACE("X3: Core GPTR Time Initf"); + + PK_TRACE_INF("SX4.D: Core[%d] GPTR Time Initf", core); p9_hcd_core_gptr_time_initf(core); + #endif - PK_TRACE("X5: Core Chiplet Init"); + PK_TRACE_INF("SX4.E: Core[%d] Chiplet Init", core); p9_hcd_core_chiplet_init(core); #if !SKIP_INITF - PK_TRACE("X6: Core Repair Initf"); + + PK_TRACE_INF("SX4.F: Core[%d] Repair Initf", core); p9_hcd_core_repair_initf(core); + #endif #if !SKIP_EXIT_CATCHUP @@ -380,9 +421,9 @@ if (!core) goto STOP1_EXIT: if (core_catchup & CME_MASK_C0) { - CME_GETSCOM(CPPM_CPMMR, CME_MASK_C0, CME_SCOM_AND, data64); + CME_GETSCOM(CPPM_CPMMR, CME_MASK_C0, CME_SCOM_AND, scom_data); - if (data64 & BIT64(13)) + if (scom_data & BIT64(13)) { core_catchup = core_catchup - CME_MASK_C0; } @@ -390,9 +431,9 @@ if (!core) goto STOP1_EXIT: if (core_catchup & CME_MASK_C1) { - CME_GETSCOM(CPPM_CPMMR, CME_MASK_C1, CME_SCOM_AND, data64); + CME_GETSCOM(CPPM_CPMMR, CME_MASK_C1, CME_SCOM_AND, scom_data); - if (data64 & BIT64(13)) + if (scom_data & BIT64(13)) { core_catchup = core_catchup - CME_MASK_C1; } @@ -421,9 +462,10 @@ if (!core) goto STOP1_EXIT: G_cme_stop_record.act_level_c0 : G_cme_stop_record.act_level_c1 ; - PK_TRACE("core[%d] running[%d] core_catchup[%d] catchup_level[%d]", - core, G_cme_stop_record.core_running, - core_catchup, catchup_level); + PK_TRACE_INF("Catch: core[%d] running[%d] \ + core_catchup[%d] catchup_level[%d]", + core, G_cme_stop_record.core_running, + core_catchup, catchup_level); while((core_catchup & (in32(CME_LCL_SISR) >> SHIFT32(11))) != core_catchup); @@ -447,17 +489,23 @@ if (!core) goto STOP1_EXIT: //=========================== MARK_TAG(SX_ARRAY_INIT, core) //=========================== + #if !SKIP_ARRAYINIT - PK_TRACE("X7: Core Array Init"); + + PK_TRACE_INF("SX4.G: Core[%d] Array Init", core); p9_hcd_core_arrayinit(core); + #endif //===================== MARK_TRAP(SX_FUNC_INIT) //===================== + #if !SKIP_INITF - PK_TRACE("X8: Core Func Scan"); + + PK_TRACE_INF("SX4.H: Core[%d] Func Scan", core); p9_hcd_core_initf(core); + #endif #endif @@ -470,23 +518,27 @@ if (!core) goto STOP1_EXIT: } } - //-------------------------------------------------------------------------- - // STOP LEVEL 3 - //-------------------------------------------------------------------------- + if (deeper_level == STOP_LEVEL_3 || target_level == STOP_LEVEL_3) { + + //-------------------------------------------------------------------------- + PK_TRACE_INF("+++++ +++++ STOP LEVEL 3 EXIT +++++ +++++"); + //-------------------------------------------------------------------------- + //====================== MARK_TAG(SX_STOP3, core) //====================== - PK_TRACE("STOP Level 3 Sequence"); //Return to full voltage //disable ivrm? } + + //-------------------------------------------------------------------------- - // STOP LEVEL 2 + PK_TRACE_INF("+++++ +++++ STOP LEVEL 2 EXIT +++++ +++++"); //-------------------------------------------------------------------------- //============================ @@ -495,22 +547,23 @@ if (!core) goto STOP1_EXIT: // do this again here for stop2 in addition to chiplet_reset // Note IPL doesnt need to do this twice - PK_TRACE("4S2: Set Core Glitchless Mux to DPLL"); + PK_TRACE("Assert core glitchless mux to DPLL via CGCR[3]"); CME_PUTSCOM(C_PPM_CGCR, core, BIT64(3)); - PK_TRACE("X9: Start Core Clock"); + PK_TRACE_INF("SX2.A: Start Core[%d] Clock", core); p9_hcd_core_startclocks(core); - // Clear CPPM PECE Shadow + PK_TRACE("Clear CPPM PECE shadow via PECES"); CME_PUTSCOM(CPPM_PECES, core, 0); - //-------------------------------------------------------------------------- - // STOP LEVEL 4 - //-------------------------------------------------------------------------- + if (deeper_level >= STOP_LEVEL_4) { - PK_TRACE("STOP Level 4+ Sequence"); + + //-------------------------------------------------------------------------- + PK_TRACE_INF("+++++ +++++ STOP LEVEL 4 EXIT CONTINUE +++++ +++++"); + //-------------------------------------------------------------------------- if (d2u4_flag) { @@ -518,11 +571,12 @@ if (!core) goto STOP1_EXIT: } #if !STOP_PRIME + //=========================== MARK_TAG(SX_SCOM_INITS, core) //=========================== - PK_TRACE("X10: Image Hardcoded Scoms"); + PK_TRACE_INF("SX4.I: Image Hardcoded Scoms on Core[%d]", core); p9_hcd_core_scominit(core); //========================== @@ -530,100 +584,118 @@ if (!core) goto STOP1_EXIT: //========================== #if !SKIP_BCE_SCOM_RESTORE - PK_TRACE("BCE Runtime Check"); + + PK_TRACE_INF("SX4.J: BCE Runtime Check Scom Restore Copy Completed"); if( BLOCK_COPY_SUCCESS != isScanRingCopyDone() ) { - PK_TRACE("BCE: Copy of scom restore failed"); + PK_TRACE_INF("ERROR: BCE Scom Restore Copy Failed. HALT CME!"); pk_halt(); } - PK_TRACE("X11: XIP Customized Scoms"); + PK_TRACE_INF("SX4.K: XIP Customized Scoms on Core[%d]", core); p9_hcd_core_scomcust(core); + #endif //============================== MARK_TAG(SX_RUNTIME_INITS, core) //============================== - // todo - //PK_TRACE("X12: RAS Runtime Scom"); - //p9_hcd_core_ras_runtime_scom(core); + PK_TRACE_INF("SX4.L: RAS Runtime Scom on Core[%d]", core); + p9_hcd_core_ras_runtime_scom(core); + + PK_TRACE_INF("SX4.M: OCC Runtime Scom on Core[%d]", core); + p9_hcd_core_occ_runtime_scom(core); - // todo - //PK_TRACE("X13: OCC Runtime Scom"); - //p9_hcd_core_occ_runtime_scom(core); #endif //============================= MARK_TAG(SX_SELF_RESTORE, core) //============================= - PK_TRACE("X14: Core Self Restore"); + PK_TRACE_INF("SX4.N: Core Self Restore"); #if !SKIP_SELF_RESTORE - PK_TRACE("Raise block interrupt to PC"); + + PK_TRACE("Assert block interrupt to PC via SICR[2/3]"); out32(CME_LCL_SICR_OR, core << SHIFT32(3)); - PK_TRACE("Now Wakeup the Core(pm_exit=1)"); + PK_TRACE("Waking up the core(pm_exit=1) via SICR[4/5]"); out32(CME_LCL_SICR_OR, core << SHIFT32(5)); - PK_TRACE("Polling for Core Wakeup(pm_active=0)"); + PK_TRACE("Polling for core wakeup(pm_active=0) via EINR[20/21]"); while((in32(CME_LCL_EINR)) & (core << SHIFT32(21))); + PK_TRACE_INF("SX4.O: Core Wakes Up, Ramming HRMOR with HOMER address"); + #if !SKIP_RAM_HRMOR - PK_TRACE("Activate Thread0 for RAM"); + + PK_TRACE("Activate thread0 for RAM via THREAD_INFO[18]"); CME_PUTSCOM(THREAD_INFO, core, BIT64(18)); - PK_TRACE("Enable RAM mode"); + PK_TRACE("Enable RAM mode via RAM_MODEREG[0]"); CME_PUTSCOM(RAM_MODEREG, core, BIT64(0)); - PK_TRACE("Set SPR mode to LT0-7"); + PK_TRACE("Set SPR mode to LT0-7 via SPR_MODE[20-27]"); CME_PUTSCOM(SPR_MODE, core, BITS64(20, 8)); if (core & CME_MASK_C0) { - PK_TRACE("Set SPRC to Scratch0 for core0"); + PK_TRACE("Set SPRC to scratch0 for core0 via SCOM_SPRC"); CME_PUTSCOM(SCOM_SPRC, CME_MASK_C0, 0); - PK_TRACE("Load Scratch0 with HOMER+2MB"); + PK_TRACE("Load SCRACTH0 with HOMER+2MB"); + #if EPM_P9_TUNING + CME_PUTSCOM(SCRACTH0, CME_MASK_C0, 0x200000); + #else + CME_PUTSCOM(SCRACTH0, CME_MASK_C0, 0xA200000); //CME_PUTSCOM(SCRACTH0, CME_MASK_C0, in64(SELF_RESTORE_ADDR_FETCH)); + #endif + } if (core & CME_MASK_C1) { - PK_TRACE("Set SPRC to Scratch1 for core1"); + PK_TRACE("Set SPRC to scratch1 for core1 via SCOM_SPRC"); CME_PUTSCOM(SCOM_SPRC, CME_MASK_C1, BIT64(60)); - PK_TRACE("Load Scratch1 with HOMER+2MB"); + PK_TRACE("Load SCRACTH1 with HOMER+2MB"); + #if EPM_P9_TUNING + CME_PUTSCOM(SCRACTH1, CME_MASK_C1, 0x200000); + #else + CME_PUTSCOM(SCRACTH1, CME_MASK_C1, 0xA200000); //CME_PUTSCOM(SCRACTH1, CME_MASK_C1, in64(SELF_RESTORE_ADDR_FETCH)); + #endif + } - PK_TRACE("RAM: mfspr sprd , gpr0"); + PK_TRACE("RAM: mfspr sprd , gpr0 via RAM_CTRL"); CME_PUTSCOM(RAM_CTRL, core, RAM_MFSPR_SPRD_GPR0); - PK_TRACE("RAM: mtspr hrmor, gpr0"); + PK_TRACE("RAM: mtspr hrmor, gpr0 via RAM_CTRL"); CME_PUTSCOM(RAM_CTRL, core, RAM_MTSPR_HRMOR_GPR0); - PK_TRACE("Disable Thread0 for RAM"); + PK_TRACE("Disable thread0 for RAM via THREAD_INFO"); CME_PUTSCOM(THREAD_INFO, core, 0); - PK_TRACE("Disable RAM mode"); + PK_TRACE("Disable RAM mode via RAM_MODEREG"); CME_PUTSCOM(RAM_MODEREG, core, 0); + #endif - PK_TRACE("S-Reset all threads"); + PK_TRACE_INF("SX4.P: S-Reset All Core[%d] Threads to Run Self Restore Image", core); CME_PUTSCOM(DIRECT_CONTROLS, core, BIT64(4) | BIT64(12) | BIT64(20) | BIT64(28)); @@ -631,22 +703,25 @@ if (!core) goto STOP1_EXIT: MARK_TRAP(SX_SRESET_THREADS) //========================== - PK_TRACE("Allow threads to run(pm_exit=0) core: %d data:0x%08x ", core, (core << SHIFT32(5))); + PK_TRACE("Allow threads to run(pm_exit=0)"); out32(CME_LCL_SICR_CLR, core << SHIFT32(5)); - PK_TRACE("Poll for Core stop again(pm_active=1)"); + PK_TRACE("Poll for core stop again(pm_active=1)"); while((~(in32(CME_LCL_EINR))) & (core << SHIFT32(21))) { if (in32_sh(CME_LCL_SISR) & (core << SHIFT32(1))) { - PK_TRACE("Error: Core Special Attention Detected"); + PK_TRACE("ERROR: Core Special Attention Detected. HALT CME!"); pk_halt(); } } - PK_TRACE("Drop block interrupt to PC"); + PK_TRACE_INF("SX4.Q: Self Restore Completed, Core is Stopped Again"); + + PK_TRACE("Drop block interrupt to PC via SICR[2/3]"); out32(CME_LCL_SICR_CLR, core << SHIFT32(3)); + #endif if (d2u4_flag) @@ -660,17 +735,15 @@ if (!core) goto STOP1_EXIT: //========================= //-------------------------------------------------------------------------- - // END OF STOP EXIT + PK_TRACE_INF("+++++ +++++ END OF STOP EXIT +++++ +++++"); //-------------------------------------------------------------------------- -#if HW386841_PLS_SRR1_CME_DLS_FIX +#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX + STOP1_EXIT: - core = core | core_stop1; -#endif - PK_TRACE("Restore PSSCR.PLS+SRR1 back to actual level"); + PK_TRACE_INF("SX0.D: Restore PSSCR.PLS+SRR1 back to actual level"); -#if HW386841_PLS_SRR1_CME_DLS_FIX core = core | core_stop1; if (core & CME_MASK_C0) @@ -682,13 +755,13 @@ STOP1_EXIT: pscrs.value = in32((CME_LCL_PSCRS00 + (thread << 2))); dsl = (G_dsl[0].vector & BITS16((thread << 2), 4)) >> SHIFT16((thread << 2) + 3); - PK_TRACE("PSCRS1%d %x, old dsl %d", thread, pscrs.value, dsl); + PK_TRACE("C0: PSCRS1%d %x, old dsl %d", thread, pscrs.value, dsl); dsl = MIN(pscrs.field.esl_a_n ? pscrs.fields.rl_a_n : 0, MAX(hist.fields.act_stop_level, dsl)); G_dsl[0].vector = ((G_dsl[0].vector & ~BITS16((thread << 2), 4)) | (dsl << SHIFT16((thread << 2) + 3))); - PK_TRACE("new dsl %d", dsl); + PK_TRACE("C0: new dsl %d", dsl); if (dsl >= STOP_LEVEL_8) { @@ -704,10 +777,10 @@ STOP1_EXIT: } CME_PUTSCOM(DIRECT_CONTROLS, CME_MASK_C0, CME_STOP_UPDATE_DLS(G_dsl[0], G_srr1[0])); - PK_TRACE("DLS C0: %x %x %x %x", + PK_TRACE("C0 DLS : %x %x %x %x", G_dsl[0].threads.t0, G_dsl[0].threads.t1, G_dsl[0].threads.t2, G_dsl[0].threads.t3); - PK_TRACE("SRR1 C0: %x %x %x %x", + PK_TRACE("C0 SRR1 : %x %x %x %x", G_srr1[0][0], G_srr1[0][1], G_srr1[0][2], G_srr1[0][3]); } @@ -720,13 +793,13 @@ STOP1_EXIT: pscrs.value = in32((CME_LCL_PSCRS10 + (thread << 2))); dsl = (G_dsl[1].vector & BITS16((thread << 2), 4)) >> SHIFT16((thread << 2) + 3); - PK_TRACE("PSCRS1%d %x, old dsl %d", thread, pscrs.value, dsl); + PK_TRACE("C1 PSCRS1%d %x, old dsl %d", thread, pscrs.value, dsl); dsl = MIN(pscrs.field.esl_a_n ? pscrs.fields.rl_a_n : 0, MAX(hist.fields.act_stop_level, dsl)); G_dsl[1].vector = ((G_dsl[1].vector & ~BITS16((thread << 2), 4)) | (dsl << SHIFT16((thread << 2) + 3))); - PK_TRACE("new dsl %d", dsl); + PK_TRACE("C1 new dsl %d", dsl); if (G_dsl[1][thread] >= STOP_LEVEL_8) { @@ -742,19 +815,23 @@ STOP1_EXIT: } CME_PUTSCOM(DIRECT_CONTROLS, CME_MASK_C1, CME_STOP_UPDATE_DLS(G_dsl[1], G_srr1[1])); - PK_TRACE("DLS C1: %x %x %x %x", + PK_TRACE("C1 DLS : %x %x %x %x", G_dsl[1].threads.t0, G_dsl[1].threads.t1, G_dsl[1].threads.t2, G_dsl[1].threads.t3); - PK_TRACE("SRR1 C0: %x %x %x %x", + PK_TRACE("C1 SRR1 : %x %x %x %x", G_srr1[1][0], G_srr1[1][1], G_srr1[1][2], G_srr1[1][3]); } #else + PK_TRACE_INF("SX0.E: Restore PSSCR.PLS+SRR1 back to actual level"); + if (core & CME_MASK_C0) { CME_GETSCOM(PPM_SSHSRC, CME_MASK_C0, CME_SCOM_AND, hist.value); + PK_TRACE("Set PLS+SRR1 for Core0"); + if (hist.fields.act_stop_level >= STOP_LEVEL_8) { CME_PUTSCOM(DIRECT_CONTROLS, CME_MASK_C0, CME_STOP_UPDATE_PLS_SRR1( @@ -790,6 +867,8 @@ STOP1_EXIT: { CME_GETSCOM(PPM_SSHSRC, CME_MASK_C1, CME_SCOM_AND, hist.value); + PK_TRACE("Set PLS+SRR1 for Core1"); + if (hist.fields.act_stop_level >= STOP_LEVEL_8) { CME_PUTSCOM(DIRECT_CONTROLS, CME_MASK_C1, CME_STOP_UPDATE_PLS_SRR1( @@ -823,19 +902,19 @@ STOP1_EXIT: #endif - PK_TRACE("XF: Now Wakeup the Core(pm_exit=1)"); + PK_TRACE_INF("SX0.F: Now Wakeup the Core[%d] (pm_exit=1) via SICR[4/5]", core); out32(CME_LCL_SICR_OR, core << SHIFT32(5)); - PK_TRACE("XF: Polling for Core Waking up(pm_active=0)"); + PK_TRACE_INF("SX0.G: Polling for Core Waking up(pm_active=0) via EINR[20/21]"); while((in32(CME_LCL_EINR)) & (core << SHIFT32(21))); - PK_TRACE("XF: Release PCB Mux back to Core"); + PK_TRACE_INF("SX0.H: Release PCB Mux back to Core via SICR[10/11]"); out32(CME_LCL_SICR_CLR, core << SHIFT32(11)); while((core & ~(in32(CME_LCL_SISR) >> SHIFT32(11))) != core); - PK_TRACE("XF: Update STOP History: STOP Exit Completed"); + PK_TRACE("Update STOP history: STOP exit completed, core ready"); CME_STOP_UPDATE_HISTORY(core, STOP_CORE_READY_RUN, STOP_TRANS_COMPLETE, @@ -859,31 +938,30 @@ STOP1_EXIT: G_cme_stop_record.core_running |= core; G_cme_stop_record.core_stopgpe &= ~core; - // HALTED_STOP_OVERRIDE_DISABLE = 0 + PK_TRACE("Drop halt STOP override disable via LMCR[14/15]"); out32(CME_LCL_LMCR_CLR, (core << SHIFT32(15))); - PK_TRACE("XF: Drop pm_exit to allow core to run if spwu is not present"); #if SPWU_AUTO - // clear auto spwu disable, enable auto spwu + PK_TRACE_INF("SX0.I: Drop auto spwu disable, enable auto spwu via LMCR[12/13]"); out32(CME_LCL_LMCR_CLR, core << SHIFT32(13)); - //clear pm_exit + PK_TRACE_INF("SX0.J: Drop pm_exit via SICR[4/5]"); out32(CME_LCL_SICR_CLR, core << SHIFT32(5)); #else if (spwu_stop) { + PK_TRACE_INF("SX0.K: Assert SPWU Done on Core[%d] via SICR[16/17]", spwu_stop); // done = spwu + !pm_active + !core_chiplet_fence + !pcbmux_req + !pcbmux_grant // chiplet fence forces pm_active to zero - PK_TRACE("XF: setting spwu done"); out32(CME_LCL_SICR_OR, spwu_stop << SHIFT32(17)); } if ((core = (core & (~spwu_stop)))) { - PK_TRACE("XF: drop pm_exit for not spwu core"); + PK_TRACE_INF("SX0.L: Drop PM_EXIT for NOT SPWU Core[%d] via SICR[4/5]", core); out32(CME_LCL_SICR_CLR, core << SHIFT32(5)); } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c index 624e1513..fcd938ee 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c @@ -29,41 +29,22 @@ extern CmeStopRecord G_cme_stop_record; -// Important: g_eimr_override at any time should mask wakeup interrupts of -// running core(s), the override vector should change after each -// entry and exit as core state is changed. -// For Entry, mask the following interrupts via unified interrupt handler: -// lower priority interrupts than pm_active, and both pm_active (catchup) -// wakeup interrupts of the entering core(s) should still be masked -// via g_eimr_override (abortion), stopped core can still exit any time -// as their wakeup interrupts should be unmasked -// After Entry, unmask the following interrupts via pk_irq_vec_restore: -// priority group on stack, likely at least both pm_active unmasked -// (stopped core cannot get extra pm_active, untouched core can enter) -// here needs to use g_eimr_override to mask wakeup of running core(s) -// wakeup of the stopped core(s) should be already unmasked by default -// (when restored, previous masked wakeups are being unmasked as well) -// For Exit, mask the following interrupts via unified interrupt handler: -// lower priority interrupts than wakeup, including DB2+pm_active(catchup) -// After Exit, unmask the following interrupts via pk_irq_vec_restore: -// priority group on stack, likely at least wakeup and DB2 unmasked -// here needs to use g_eimr_override to mask wakeup of exited core(s) void -p9_cme_stop_event_handler(void* arg, PkIrqId irq) +p9_cme_stop_exit_handler(void* arg, PkIrqId irq) { - MARK_TRAP(STOP_EVENT_HANDLER) - PK_TRACE("STOP-IRQ: %d", irq); + MARK_TRAP(STOP_EXIT_HANDLER) + PK_TRACE_INF("SX-IRQ: %d", irq); + out32(CME_LCL_EIMR_OR, BITS32(12, 6) | BITS32(20, 2)); + pk_semaphore_post((PkSemaphore*)arg); +} - if (in32(CME_LCL_EISR) & BITS32(12, 6)) - { - PK_TRACE("lanuch exit"); - pk_semaphore_post((PkSemaphore*)(&(G_cme_stop_record.sem[1]))); - } - else if (in32(CME_LCL_EISR) & BITS32(20, 2)) - { - PK_TRACE("lanuch entry"); - pk_semaphore_post((PkSemaphore*)(&(G_cme_stop_record.sem[0]))); - } +void +p9_cme_stop_enter_handler(void* arg, PkIrqId irq) +{ + MARK_TRAP(STOP_ENTER_HANDLER) + PK_TRACE_INF("SE-IRQ: %d", irq); + out32(CME_LCL_EIMR_OR, BITS32(12, 6) | BITS32(20, 2)); + pk_semaphore_post((PkSemaphore*)arg); } void @@ -71,7 +52,7 @@ p9_cme_stop_db1_handler(void* arg, PkIrqId irq) { PkMachineContext ctx; MARK_TRAP(STOP_DB1_HANDLER) - PK_TRACE("DB1-IRQ: %d", irq); + PK_TRACE_INF("DB1-IRQ: %d", irq); pk_irq_vec_restore(&ctx); } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c index 81a9e462..cae31546 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c @@ -32,8 +32,7 @@ p9_hcd_core_arrayinit(uint32_t core) int rc = CME_STOP_SUCCESS; uint64_t scom_data; - /// @todo add DD1 attribute control - PK_TRACE("DD1 only: set sdis_n(flushing LCBES condition workaround"); + PK_TRACE("Assert sdis_n(flushing LCBES condition) via CPLT_CONF0[34]"); CME_PUTSCOM(C_CPLT_CONF0_OR, core, BIT64(34)); PK_TRACE("Drop vital fence (moved to arrayinit from sacn0 module)"); @@ -99,8 +98,7 @@ p9_hcd_core_arrayinit(uint32_t core) p9_hcd_core_scan0(core, SCAN0_REGION_ALL_BUT_PLL, SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME); #endif - /// @todo add DD1 attribute control - PK_TRACE("DD1 only: reset sdis_n(flushing LCBES condition workaround"); + PK_TRACE("Drop sdis_n(flushing LCBES condition) via CPLT_CONF0[34]"); CME_PUTSCOM(C_CPLT_CONF0_CLEAR, core, BIT64(34)); return rc; diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c index 1e118429..0162011c 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c @@ -97,5 +97,12 @@ p9_hcd_core_chiplet_reset(uint32_t core) PK_TRACE("Assert vdm enable via CPPM_VDMCR[0]"); CME_PUTSCOM(PPM_VDMCR_OR, core, BIT64(0)); + /// content of p9_hcd_core_dcc_skewadjust below: + PK_TRACE("Drop core DCC bypass via NET_CTRL[1]"); + CME_PUTSCOM(CPPM_NC1INDIR_CLR, core, BIT64(1)); + + PK_TRACE("Drop core progdly bypass(skewadjust) via NET_CTRL1[2]"); + CME_PUTSCOM(CPPM_NC1INDIR_CLR, core, BIT64(2)); + return rc; } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c index fc6a81a5..e734b603 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c @@ -30,7 +30,7 @@ int p9_hcd_core_scan0(uint32_t core, uint64_t regions, uint64_t scan_type) { int rc = CME_STOP_SUCCESS; -#if BROADSIDE_SCAN0 +#if EPM_BROADSIDE_SCAN0 // clean up the scan region CME_PUTSCOM(PERV_SCAN_REGION_TYPE, core, 0); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c index 565f9fa7..7df59e00 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c @@ -35,8 +35,7 @@ p9_hcd_core_startclocks(uint32_t core) //FAPI_DBG("Set CPLT_CTRL0[AVP_MODE] for cache-contained execution"); //FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_OR, MASK_SET(5))); - /// @todo add DD1 attribute control - PK_TRACE("DD1 only: set sdis_n(flushing LCBES condition workaround"); + PK_TRACE("Assert sdis_n(flushing LCBES condition) via CPLT_CONF0[34]"); CME_PUTSCOM(C_CPLT_CONF0_OR, core, BIT64(34)); PK_TRACE("Set inop_align/wait/wait_cycles via OPCG_ALIGN[0-3,12-19,52-63]"); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c index 4ab1f196..32957704 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c @@ -32,8 +32,7 @@ p9_hcd_cache_arrayinit(uint32_t quad, uint32_t ex) int rc = SGPE_STOP_SUCCESS; uint64_t scom_data; - /// @todo add DD1 attribute control - PK_TRACE("DD1 only: set sdis_n(flushing LCBES condition workaround"); + PK_TRACE("Assert sdis_n(flushing LCBES condition) via CPLT_CONF0[34]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CONF0_OR, quad), BIT64(34)); PK_TRACE("Drop vital fence (moved to arrayinit from sacn0 module)"); @@ -114,8 +113,7 @@ p9_hcd_cache_arrayinit(uint32_t quad, uint32_t ex) // all but anep dpll all but gptr repr time #endif - /// @todo add DD1 attribute control - PK_TRACE("DD1 only: reset sdis_n(flushing LCBES condition workaround"); + PK_TRACE("Drop sdis_n(flushing LCBES condition) via CPLT_CONF0[34]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CONF0_CLEAR, quad), BIT64(34)); return rc; diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C new file mode 100644 index 00000000..22c858bc --- /dev/null +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C @@ -0,0 +1,70 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_l3_dcc_setup.C $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2016,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_hcd_cache_chiplet_l3_dcc_setup.C +/// +/// @brief Setup L3 DCC, Drop L3 DCC bypass +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#include "p9_sgpe_stop.h" +#include "p9_sgpe_stop_exit_marks.h" +#include "hw_access.H" +#include "p9_ringid_sgpe.H" +#include <fapi2.H> + + +extern "C" int p9_hcd_cache_chiplet_l3_dcc_setup(uint32_t quad) +{ + int rc = SGPE_STOP_SUCCESS; + fapi2::Target<fapi2::TARGET_TYPE_EQ> l_eqTarget + ( + fapi2::plat_getTargetHandleByChipletNumber((uint8_t)quad + EQ_CHIPLET_OFFSET) + ); + + FAPI_DBG(">>p9_hcd_cache_chiplet_l3_dcc_setup"); + + FAPI_DBG("Scan eq_ana_bndy_l3dcc_bucket_26 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, + eq_ana_bndy_l3dcc_bucket_26, fapi2::RING_MODE_SET_PULSE_NSL)); + + FAPI_DBG("Drop L3 DCC bypass"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL1_WAND, quad), ~BIT64(1)); + + FAPI_DBG("Check if VDMs are to be enabled. If so, power them on"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_VDMCR_OR, quad), BIT64(0)); + +fapi_try_exit: + + FAPI_DBG("<<p9_hcd_cache_chiplet_l3_dcc_setup"); + return rc; +} diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c index a8224000..519444e2 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c @@ -82,7 +82,11 @@ p9_hcd_cache_chiplet_reset(uint32_t quad, uint32_t ex) GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_PPM_CGCR, quad), (BIT64(0) | BIT64(3))); PK_TRACE("Flip L2 glsmux to DPLL via QPPM_EXCGCR[34:35]"); +#if !HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_OR, quad), BITS64(34, 2)); +#else + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_OR, quad), ((uint64_t)ex << SHIFT64(35))); +#endif PK_TRACE("Assert DPLL ff_bypass via QPPM_DPLL_CTRL[2]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_DPLL_CTRL_OR, quad), BIT64(2)); @@ -94,7 +98,11 @@ p9_hcd_cache_chiplet_reset(uint32_t quad, uint32_t ex) GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_PPM_CGCR, quad), BIT64(3)); PK_TRACE("Drop L2 glsmux reset via QPPM_EXCGCR[32:33]"); +#if !HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_CLR, quad), BITS64(32, 2)); +#else + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_CLR, quad), ((uint64_t)ex << SHIFT64(33))); +#endif // 40 ref cycles PPE_WAIT_CORE_CYCLES(loop, 1600); @@ -119,6 +127,7 @@ p9_hcd_cache_chiplet_reset(uint32_t quad, uint32_t ex) // Marker for scan0 MARK_TRAP(SX_CHIPLET_RESET_SCAN0) #if !SKIP_SCAN0 +#if !HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX uint64_t regions = SCAN0_REGION_ALL_BUT_EX; if (ex & FST_EX_IN_QUAD) @@ -132,16 +141,145 @@ p9_hcd_cache_chiplet_reset(uint32_t quad, uint32_t ex) } p9_hcd_cache_scan0(quad, regions, SCAN0_TYPE_GPTR_REPR_TIME); +#else + PK_TRACE_INF("DD1 VCS workaround:"); + uint32_t l_loop = 0; + uint64_t regions = SCAN0_REGION_ALL; + p9_hcd_cache_scan0(quad, regions, SCAN0_TYPE_GPTR_REPR_TIME); + + //Eq_fure + Ex_l2_fure(ex0) + Ex_l2_fure(ex1) +#define DD1_EQ_FURE_RING_LENGTH (46532+119192+119192) + uint64_t l_regions = CLK_REGION_PERV | CLK_REGION_EX0_L2 | CLK_REGION_EX1_L2; + + // ---------------------------------------------------- + // Scan1 initialize region:Perv/L20/L21 type:Fure rings + // Note: must also scan partial good "bad" L2 rings, + // and clock start&stop their latches, as well + // ---------------------------------------------------- + + PK_TRACE("Assert Vital clock regional fence via CPLT_CTRL1[3]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_OR, quad), BIT64(3)); + + PK_TRACE("Assert regional fences of scanned regions via CPLT_CTRL1[4,8,9]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_OR, quad), l_regions); + + PK_TRACE("Clear clock region register via CLK_REGION"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLK_REGION, quad), 0); + + PK_TRACE("Setup scan select register via SCAN_REGION_TYPE[4,8,9,48,51]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_SCAN_REGION_TYPE, quad), + (l_regions | SCAN_TYPE_FUNC | SCAN_TYPE_REGF)); + + PK_TRACE("Write scan data register via 0x1003E040"); + + for (l_loop = 0; l_loop <= DD1_EQ_FURE_RING_LENGTH / 64; l_loop++) + { + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x1003E040, quad), BITS64(0, 64)); + } + + PK_TRACE("Final Scan Loop Count: %d", l_loop); + + // ------------------------------- + // Start Perv/L20/L21 clocks + // ------------------------------- + + PK_TRACE("Clear all SCAN_REGION_TYPE bits"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_SCAN_REGION_TYPE, quad), 0); + + PK_TRACE("Start cache clocks(perv/l20/l21) via CLK_REGION"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLK_REGION, quad), + (CLK_START_CMD | CLK_THOLD_ARY | l_regions)); + + PK_TRACE("Poll for perv/l20/l21 clocks running via CPLT_STAT0[8]"); + + do + { + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_STAT0, quad), scom_data); + } + while((~scom_data) & BIT64(8)); + + PK_TRACE("Check perv/l20/l21 clocks running"); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLOCK_STAT_ARY, quad), scom_data); + + if (scom_data & l_regions) + { + PK_TRACE("Perv/l20/l21 clock start failed"); + pk_halt(); + } + + PK_TRACE("Perv/l20/l21 clocks running now"); + + // ------------------------------- + // Turn on power headers for VCS + // ------------------------------- + + // vcs_pfet_force_state = 11 (Force Von) + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_OR, quad), BITS64(2, 2)); + + do + { + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS, quad), scom_data); + } + while(!(scom_data & BIT64(50))); + + // vdd_pfet_force_state = 00 (Nop) + // vcs_pfet_force_state = 00 (Nop) + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_CLR, quad), BITS64(0, 4)); + + PK_TRACE("Powered On VCS"); + + // ------------------------------- + // Stop Perv/L20/L21 clocks + // ------------------------------- + + PK_TRACE("Clear all SCAN_REGION_TYPE bits"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_SCAN_REGION_TYPE, quad), 0); + + PK_TRACE("Stop perv/l20/l21 clocks via CLK_REGION"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLK_REGION, quad), + (CLK_STOP_CMD | CLK_THOLD_ARY | l_regions)); + + PK_TRACE("Poll for perv/l20/l21 clocks stopped via CPLT_STAT0[8]"); + + do + { + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_STAT0, quad), scom_data); + } + while((~scom_data) & BIT64(8)); + + PK_TRACE("Check perv/l20/l21 clocks stopped"); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLOCK_STAT_ARY, quad), scom_data); + + if (((~scom_data) & l_regions) != 0) + { + PK_TRACE("Perv/l20/l21 clock stop failed"); + pk_halt(); + } + + PK_TRACE("Perv/l20/l21 Clock Stopped"); + + // ------------------------------- + // Clean up + // ------------------------------- + + PK_TRACE("Drop Vital clock regional fence via CPLT_CTRL1[3]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_CLEAR, quad), BIT64(3)); + + PK_TRACE("Drop Perv/L20/L21 regional fences via CPLT_CTRL1[4,8,9]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_CLEAR, quad), l_regions); + +#endif + p9_hcd_cache_scan0(quad, regions, SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME); #endif - /// content below from p9_hcd_cache_chiplet_l3_dcc_setup + /// content of p9_hcd_cache_chiplet_l3_dcc_setup below: /// @todo scan_with_setpulse_module(l3 dcc) - PK_TRACE("Drop L3 DCC bypass via NET_CTRL1[1]"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL1_WAND, quad), ~BIT64(1)); + //PK_TRACE("Drop L3 DCC bypass via NET_CTRL1[1]"); + //GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL1_WAND, quad), ~BIT64(1)); /// @todo add VDM_ENABLE attribute control - PK_TRACE("Assert vdm enable via CPPM_VDMCR[0]"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_VDMCR_OR, quad), BIT64(0)); + //PK_TRACE("Assert vdm enable via CPPM_VDMCR[0]"); + //GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_VDMCR_OR, quad), BIT64(0)); return rc; } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C new file mode 100644 index 00000000..4cb35ecf --- /dev/null +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C @@ -0,0 +1,141 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dcc_skewadjust_setup.C $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2016,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_hcd_cache_dcc_skewadjust_setup.C +/// +/// @brief Drop DCCs reset and bypass, Drop skewadjust reset and bypass +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE:SGPE +//------------------------------------------------------------------------------ + +#include "p9_sgpe_stop.h" +#include "p9_sgpe_stop_exit_marks.h" +#include "hw_access.H" +#include "p9_ringid_sgpe.H" +#include <fapi2.H> + + + +extern "C" int p9_hcd_cache_dcc_skewadjust_setup(uint32_t quad) +{ + int rc = SGPE_STOP_SUCCESS; + fapi2::Target<fapi2::TARGET_TYPE_EQ> l_eqTarget + ( + fapi2::plat_getTargetHandleByChipletNumber((uint8_t)quad + EQ_CHIPLET_OFFSET) + ); + + FAPI_DBG(">>p9_hcd_cache_dcc_skewadjust_setup"); + + FAPI_DBG("Release L2-0, L2-1 DC Adjust reset"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_NET_CTRL1_WAND, quad), ~BITS64(23, 2)); + + ocb_ccsr_t ccsr; + + do + { + ccsr.value = in32(OCB_CCSR); + } + while (ccsr.fields.change_in_progress); + + for(int core = 0; core < CORES_PER_QUAD; core++) + { + if (ccsr.value & BIT32(((quad << 2) + core))) + { + FAPI_DBG("Release CORE DC Adjust reset"); + GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(C_NET_CTRL0_WAND, ((quad << 2) + core)), ~BIT64(2)); + } + } + + FAPI_DBG("Scan eq_ana_bndy_bucket_0 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_0, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_1 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_1, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_2 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_2, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_3 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_3, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_4 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_4, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_5 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_5, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_6 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_6, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_7 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_7, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_8 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_8, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_9 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_9, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_10 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_10, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_11 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_11, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_12 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_12, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_13 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_13, fapi2::RING_MODE_SET_PULSE_NSL)); + + FAPI_DBG("Release DCC bypass"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_NET_CTRL1_WAND, quad), ~BIT64(1)); + + FAPI_DBG("Scan eq_ana_bndy_bucket_14 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_14, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_15 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_15, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_16 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_16, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_17 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_17, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_18 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_18, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_19 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_19, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_20 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_20, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_21 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_21, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_22 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_22, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_23 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_23, fapi2::RING_MODE_SET_PULSE_NSL)); + + FAPI_DBG("Release Progdly bypass"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_NET_CTRL1_WAND, quad), ~BIT64(2)); + + FAPI_DBG("Scan eq_ana_bndy_bucket_24 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_24, fapi2::RING_MODE_SET_PULSE_NSL)); + FAPI_DBG("Scan eq_ana_bndy_bucket_25 ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_bndy_bucket_25, fapi2::RING_MODE_SET_PULSE_NSL)); + +fapi_try_exit: + + FAPI_DBG("<<p9_hcd_cache_dcc_skewadjust_setup"); + return rc; +} diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_initf.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_initf.C new file mode 100755 index 00000000..854aff03 --- /dev/null +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_initf.C @@ -0,0 +1,50 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_initf.C $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#include "p9_sgpe_stop.h" +#include "p9_sgpe_stop_exit_marks.h" +#include "hw_access.H" +#include "p9_ringid_sgpe.H" +#include <fapi2.H> + +extern "C" int p9_hcd_cache_dpll_initf(uint32_t quad) +{ + int rc = SGPE_STOP_SUCCESS; + fapi2::Target<fapi2::TARGET_TYPE_EQ> l_eqTarget + ( + fapi2::plat_getTargetHandleByChipletNumber((uint8_t)quad + EQ_CHIPLET_OFFSET) + ); + + FAPI_INF(">>p9_hcd_cache_dpll_initf"); + + FAPI_DBG("Scan eq_dpll_func ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_dpll_func)); + + // Markers needed for cache ininf +fapi_try_exit: + FAPI_INF("<<p9_hcd_cache_dpll_initf"); + + return rc; +} diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c index 540e4dfc..91cc9242 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c @@ -35,7 +35,7 @@ p9_hcd_cache_dpll_setup(uint32_t quad) // This is necessary to ensure that the DPLL is in Mode 1. // If not, the lock times will go from ~30us to 3-5ms PK_TRACE("Assert DPLL in mode 1,set slew rate via QPPM_DPLL_CTRL[2,6-15]"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_DPLL_CTRL_OR, quad), BIT64(2) | BIT64(8)); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_DPLL_CTRL_OR, quad), BIT64(2) | BIT64(9)); PK_TRACE("Drop DPLL test mode and reset via NET_CTRL0[3,4]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WAND, quad), ~BITS64(3, 2)); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c index 8322fbf0..889827b5 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c @@ -60,7 +60,7 @@ p9_hcd_cache_poweron(uint32_t quad) BITS64(4, 4) | BIT64(8)); // vdd_pfet_force_state = 11 (Force Von) - PK_TRACE("Power Off Cache VDD"); + PK_TRACE("Power On Cache VDD"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_OR, quad), BITS64(0, 2)); PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle)"); @@ -71,8 +71,9 @@ p9_hcd_cache_poweron(uint32_t quad) } while(!(scom_data & BIT64(42))); +#if !HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX // vcs_pfet_force_state = 11 (Force Von) - PK_TRACE("Power Off Cache VCS"); + PK_TRACE("Power On Cache VCS"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_OR, quad), BITS64(2, 2)); PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle)"); @@ -87,7 +88,7 @@ p9_hcd_cache_poweron(uint32_t quad) // vcs_pfet_force_state = 00 (Nop) PK_TRACE("Turn Off Force Von"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_CLR, quad), BITS64(0, 4)); - +#endif #endif return rc; diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scan0.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scan0.c index 972ca3c2..2bb2e2da 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scan0.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scan0.c @@ -30,7 +30,7 @@ int p9_hcd_cache_scan0(uint32_t quad, uint64_t regions, uint64_t scan_type) { int rc = SGPE_STOP_SUCCESS; -#if BROADSIDE_SCAN0 +#if EPM_BROADSIDE_SCAN0 // clean up the scan region GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PERV_SCAN_REGION_TYPE, quad), 0); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c index 77c37459..681a2e2d 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_scominit.c @@ -26,11 +26,39 @@ #include "p9_sgpe_stop.h" #include "p9_sgpe_stop_exit_marks.h" +extern SgpeStopRecord G_sgpe_stop_record; + int -p9_hcd_cache_scominit(uint32_t quad) +p9_hcd_cache_scominit(uint32_t quad, uint32_t ex) { int rc = SGPE_STOP_SUCCESS; - uint64_t scom_data; + uint64_t scom_data; + ocb_qcsr_t qcsr; + + PK_TRACE("Set L3_LCO_TARGET_ID/VICTIMS via EX_L3_MODE_REG1[2-5,6-21]"); + + // read partial good exes + do + { + qcsr.value = in32(OCB_QCSR); + } + while (qcsr.fields.change_in_progress); + + if (ex & FST_EX_IN_QUAD) + { + GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG1, quad, 0), scom_data); + scom_data |= (quad << SHIFT32((5 - 1))); + scom_data |= ((qcsr.value & BITS32(0, 12)) >> 6); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG1, quad, 0), scom_data); + } + + if (ex & SND_EX_IN_QUAD) + { + GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG1, quad, 1), scom_data); + scom_data |= ((quad << SHIFT32((5 - 1))) + 1); + scom_data |= ((qcsr.value & BITS32(0, 12)) >> 6); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_L3_MODE_REG1, quad, 1), scom_data); + } PK_TRACE("Enable DTS sampling via THERM_MODE_REG[5]"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_THERM_MODE_REG, quad), scom_data); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c index d7d0399f..82d7795a 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c @@ -114,7 +114,6 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme ) uint8_t l_cmeIndex = 0; uint8_t activeCmeList[MAX_CME_PER_CHIP] = {ZERO}; uint8_t activeCmeCnt = 0; - uint8_t cmeInitSuccessCnt = 0; uint8_t quadId = 0; uint32_t l_scomAddr = 0; @@ -280,6 +279,10 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme ) break; } + uint32_t cmeBootedList = 0; + + uint8_t cmeInitSuccessCnt = 0; + uint32_t l_copyStatus = 0; while(cmeInitSuccessCnt != activeCmeCnt) @@ -294,6 +297,14 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme ) continue; } + uint32_t l_cmeBootedBit = CHECK_BIT >> l_cmeIndex; + + if( cmeBootedList & l_cmeBootedBit ) + { + // CME Boot successful already + continue; + } + l_copyStatus = checkCmeBlockCopyStatus( l_cmeIndex, PLAT_SGPE ); if(BLOCK_COPY_IN_PROGRESS == l_copyStatus ) @@ -347,6 +358,7 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme ) // Writing to XCR to resume PPE operation PPE_PUTSCOM( l_scomAddr, RESUME_PPE_OPERATION ); cmeInitSuccessCnt++; + cmeBootedList = cmeBootedList | l_cmeBootedBit; } //for ( l_cmeIndex = 0 ....) diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C index 873793d9..5ac8b6c5 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C @@ -98,7 +98,7 @@ EXTERNAL_IRQ_TABLE_END #define KERNEL_STACK_SIZE 512 -#define SGPE_THREAD_STACK_SIZE_STOP_EXIT 512 +#define SGPE_THREAD_STACK_SIZE_STOP_EXIT 1024 #define SGPE_THREAD_STACK_SIZE_STOP_ENTRY 256 #define SGPE_THREAD_PRIORITY_STOP_EXIT 1 @@ -138,6 +138,7 @@ main(int argc, char** argv) { if (in32(OCB_OCCFLG) & BIT32(12)) { + PK_TRACE_INF("BREAK: Trap at SGPE Booted"); asm volatile ("trap"); } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h index 818765df..82932c62 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h @@ -59,6 +59,7 @@ extern "C" { #define EQ_SCAN_REGION_TYPE 0x10030005 #define EQ_CLK_REGION 0x10030006 #define EQ_CLOCK_STAT_SL 0x10030008 +#define EQ_CLOCK_STAT_ARY 0x1003000A #define EQ_THERM_MODE_REG 0x1005000F #define EQ_BIST 0x100F000B @@ -66,6 +67,7 @@ extern "C" { #define EQ_NET_CTRL0_WAND 0x100F0041 #define EQ_NET_CTRL0_WOR 0x100F0042 #define C_NET_CTRL0 0x200F0040 +#define C_NET_CTRL0_WAND 0x200F0041 #define C_NET_CTRL0_WOR 0x200F0042 #define EQ_NET_CTRL1_WAND 0x100F0045 #define EQ_NET_CTRL1_WOR 0x100F0046 @@ -93,6 +95,7 @@ extern "C" { #define EQ_QPPM_QCCR_WOR 0x100F01BF #define EX_NCU_STATUS_REG 0x1001100F +#define EX_L3_MODE_REG1 0x1001180A #define EX_DRAM_REF_REG 0x1001180F #define EX_PM_PURGE_REG 0x10011813 #define EX_PM_LCO_DIS_REG 0x10011816 @@ -111,6 +114,7 @@ extern "C" { #define PERV_OPCG_CAPT1 0x10030011 #define PERV_OPCG_CAPT2 0x10030012 #define PERV_CPLT_STAT0 0x10000100 +#define PERV_NET_CTRL1_WAND 0x000F0045 /// Macro to update STOP History #define SGPE_STOP_UPDATE_HISTORY(id,base,gated,trans,req_l,act_l,req_e,act_e) \ @@ -175,7 +179,7 @@ enum SGPE_STOP_VECTOR_INDEX VECTOR_CONFIG = 2 }; -#if HW386311_PBIE_RW_PTR_STOP11_FIX +#if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX #define EXTRACT_RING_BITS(mask, ring, save) save = (ring) & (mask); #define RESTORE_RING_BITS(mask, ring, save) ring = (((ring) & (~mask)) | (save)); #endif @@ -196,12 +200,12 @@ typedef struct typedef struct { - uint32_t core[3]; - uint32_t ex_l[3]; - uint32_t ex_r[3]; - uint32_t ex_b[3]; - uint32_t quad[3]; - uint32_t qswu[3]; + uint32_t core[3]; // 24 bits + uint32_t ex_l[3]; // 6 bits + uint32_t ex_r[3]; // 6 bits + uint32_t ex_b[3]; // 12 bits + uint32_t quad[3]; // 6 bits + uint32_t qswu[3]; // 6 bits } sgpe_group_t; /// SGPE Stop Score Board Structure @@ -228,14 +232,18 @@ int p9_sgpe_stop_exit(); int p9_hcd_cache_scan0(uint32_t, uint64_t, uint64_t); int p9_hcd_cache_poweron(uint32_t); int p9_hcd_cache_chiplet_reset(uint32_t, uint32_t); +int p9_hcd_cache_chiplet_l3_dcc_setup(uint32_t); int p9_hcd_cache_gptr_time_initf(uint32_t); +int p9_hcd_cache_dpll_initf(uint32_t); int p9_hcd_cache_dpll_setup(uint32_t); +int p9_hcd_cache_dcc_skewadjust_setup(uint32_t); int p9_hcd_cache_chiplet_init(uint32_t); int p9_hcd_cache_repair_initf(uint32_t); int p9_hcd_cache_arrayinit(uint32_t, uint32_t ex); +int p9_hcd_cache_initf(uint32_t); int p9_hcd_cache_startclocks(uint32_t, uint32_t); int p9_hcd_cache_l2_startclocks(uint32_t, uint32_t, uint32_t); -int p9_hcd_cache_scominit(uint32_t); +int p9_hcd_cache_scominit(uint32_t, uint32_t); int p9_hcd_cache_scomcust(uint32_t); int p9_hcd_cache_ras_runtime_scom(uint32_t); int p9_hcd_cache_occ_runtime_scom(uint32_t); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c index d924d196..58bfaf67 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c @@ -27,7 +27,9 @@ #include "p9_sgpe_stop_enter_marks.h" extern SgpeStopRecord G_sgpe_stop_record; -#if HW386311_PBIE_RW_PTR_STOP11_FIX + +#if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX + uint64_t G_ring_save[MAX_QUADS][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, @@ -37,6 +39,7 @@ uint64_t G_ring_save[MAX_QUADS][8] = {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} }; + uint64_t G_ring_spin[10][2] = { {0, 0}, @@ -50,6 +53,7 @@ uint64_t G_ring_spin[10][2] = {6343, 0xC1E061FFED5F0000}, //29 {17871, 0} //128 }; + #endif int @@ -67,10 +71,14 @@ p9_sgpe_stop_entry() uint64_t scom_data; uint64_t temp_data; ppm_sshsrc_t hist; -#if HW386311_PBIE_RW_PTR_STOP11_FIX +#if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX int spin; #endif + //-------------------------------------------------------------------------- + PK_TRACE_INF("+++++ +++++ BEGIN OF STOP ENTRY +++++ +++++"); + //-------------------------------------------------------------------------- + //================================ MARK_TAG(BEGINSCOPE_STOP_ENTRY, 0) //================================ @@ -130,21 +138,21 @@ p9_sgpe_stop_entry() if (G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY] || G_sgpe_stop_record.group.quad[VECTOR_ENTRY]) { - PK_TRACE("clv[%d][%d][%d][%d]", - G_sgpe_stop_record.level[qloop][0], - G_sgpe_stop_record.level[qloop][1], - G_sgpe_stop_record.level[qloop][2], - G_sgpe_stop_record.level[qloop][3]); + PK_TRACE_INF("Actual: clv[%d][%d][%d][%d]", + G_sgpe_stop_record.level[qloop][0], + G_sgpe_stop_record.level[qloop][1], + G_sgpe_stop_record.level[qloop][2], + G_sgpe_stop_record.level[qloop][3]); - PK_TRACE("act: qlv[%d]x0lv[%d]x1lv[%d]", - G_sgpe_stop_record.state[qloop].act_state_q, - G_sgpe_stop_record.state[qloop].act_state_x0, - G_sgpe_stop_record.state[qloop].act_state_x1); + PK_TRACE_INF("Actual: qlv:[%d]x0lv[%d]x1lv[%d]", + G_sgpe_stop_record.state[qloop].act_state_q, + G_sgpe_stop_record.state[qloop].act_state_x0, + G_sgpe_stop_record.state[qloop].act_state_x1); - PK_TRACE("req: qlv[%d]x0lv[%d]x1lv[%d]", - G_sgpe_stop_record.state[qloop].req_state_q, - G_sgpe_stop_record.state[qloop].req_state_x0, - G_sgpe_stop_record.state[qloop].req_state_x1); + PK_TRACE_INF("Request: qlv[%d]x0lv[%d]x1lv[%d]", + G_sgpe_stop_record.state[qloop].req_state_q, + G_sgpe_stop_record.state[qloop].req_state_x0, + G_sgpe_stop_record.state[qloop].req_state_x1); } } @@ -157,11 +165,11 @@ p9_sgpe_stop_entry() G_sgpe_stop_record.group.quad[VECTOR_ENTRY] &= G_sgpe_stop_record.group.quad[VECTOR_CONFIG]; - PK_TRACE("Core Entry Vectors: X[%x] X0[%x] X1[%x] Q[%x]", - G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY], - G_sgpe_stop_record.group.ex_l[VECTOR_ENTRY], - G_sgpe_stop_record.group.ex_r[VECTOR_ENTRY], - G_sgpe_stop_record.group.quad[VECTOR_ENTRY]); + PK_TRACE_INF("Core Entry Vectors: X[%x] X0[%x] X1[%x] Q[%x]", + G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY], + G_sgpe_stop_record.group.ex_l[VECTOR_ENTRY], + G_sgpe_stop_record.group.ex_r[VECTOR_ENTRY], + G_sgpe_stop_record.group.quad[VECTOR_ENTRY]); //TODO: message pgpe to suspend Pstate only if stop level >= 8 if (G_sgpe_stop_record.group.quad[VECTOR_ENTRY]) @@ -178,9 +186,7 @@ p9_sgpe_stop_entry() } - // ------------------------------------------------------------------------ - // EX STOP ENTRY [LEVEL 8-10] - // ------------------------------------------------------------------------ + // only stop 8 sets x_in for(xentry = G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY], qloop = 0; xentry > 0; @@ -192,17 +198,29 @@ p9_sgpe_stop_entry() continue; } - PK_TRACE("q[%d]exmask[%d] starts entry", qloop, ex); + // ------------------------------------------------------------------------ + PK_TRACE_INF("+++++ +++++ EX STOP ENTRY [LEVEL 8-10] +++++ +++++"); + // ------------------------------------------------------------------------ - // Update QSSR: stop_entry_ongoing + PK_TRACE_INF("Check: q[%d]ex[%d] start ex entry", qloop, ex); + + PK_TRACE("Update QSSR: stop_entry_ongoing"); out32(OCB_QSSR_OR, BIT32(qloop + 20)); - // Update History for ongoing stop 8 entry cloop = (ex & FST_EX_IN_QUAD) ? 0 : CORES_PER_EX; climit = (ex & SND_EX_IN_QUAD) ? CORES_PER_QUAD : CORES_PER_EX; for(; cloop < climit; cloop++) { + // Check partial good core + if (!(G_sgpe_stop_record.group.core[VECTOR_CONFIG] & + BIT32(((qloop << 2) + cloop)))) + { + continue; + } + + PK_TRACE("Update STOP history on core[%d]: in transition of entry", + ((qloop << 2) + cloop)); SGPE_STOP_UPDATE_HISTORY(((qloop << 2) + cloop), CORE_ADDR_BASE, STOP_CORE_IS_GATED, @@ -217,9 +235,8 @@ p9_sgpe_stop_entry() MARK_TAG(SE_STOP_L2_CLKS, ((ex << 6) | (32 >> qloop))) //==================================================== - PK_TRACE("SE8.a"); + PK_TRACE("Drop L2 Snoop(quiesce L2-L3 interface) via EX_PM_L2_RCMD_DIS_REG[0]"); - // Disable L2 Snoop(quiesce L2-L3 interface, what about NCU?) if (ex & FST_EX_IN_QUAD) GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_L2_RCMD_DIS_REG, qloop, 0), BIT64(0)); @@ -230,7 +247,7 @@ p9_sgpe_stop_entry() PPE_WAIT_CORE_CYCLES(loop, 256) - PK_TRACE("set partial bad l2/l3 and stopping/stoped l2 pscom masks"); + PK_TRACE("Assert partial bad L2/L3 and stopping/stoped l2 pscom masks via RING_FENCE_MASK_LATCH"); scom_data = 0; if (!(G_sgpe_stop_record.group.ex_l[VECTOR_CONFIG] & BIT32(qloop))) @@ -255,18 +272,17 @@ p9_sgpe_stop_entry() GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_RING_FENCE_MASK_LATCH, qloop), scom_data); - PK_TRACE("SE8.b"); - // Set all bits to zero prior stop cache clocks + + + PK_TRACE("Clear SCAN_REGION_TYPE prior to stop L2 clocks"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_SCAN_REGION_TYPE, qloop), 0); - PK_TRACE("SE8.c"); - // Stop L2 Clocks + PK_TRACE("Stop L2 clocks via CLK_REGION[8/9]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLK_REGION, qloop), (CLK_STOP_CMD | CLK_THOLD_ALL | ((uint64_t)ex << SHIFT64(9)))); - PK_TRACE("SE8.d"); - // Poll for L2 clocks stopped + PK_TRACE("Poll for L2 clocks stopped via CPLT_STAT0[8]"); do { @@ -274,44 +290,40 @@ p9_sgpe_stop_entry() } while((~scom_data) & BIT64(8)); + PK_TRACE("Check L2 clock is stopped via CLOCK_STAT_SL[4-13]"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLOCK_STAT_SL, qloop), scom_data); if (((~scom_data) & ((uint64_t)ex << SHIFT64(9))) != 0) { - PK_TRACE("L2 clock stop failed"); + PK_TRACE("ERROR: L2 clock stop failed. HALT SGPE!"); pk_halt(); } // MF: verify compiler generate single rlwmni // MF: delay may be needed for stage latch to propagate thold - PK_TRACE("SE8: L2 Clock Stopped"); + PK_TRACE_INF("SE8.A: L2 Clock Stopped"); //======================== MARK_TRAP(SE_STOP_L2_GRID) //======================== - PK_TRACE("SE8.e"); - // Drop clock sync enable before switch to refclk + PK_TRACE("Drop clock sync enable before switch to refclk via EXCGCR[36/37]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_CLR, qloop), ((uint64_t)ex << SHIFT64(37))); - PK_TRACE("SE8.f"); + PK_TRACE("Poll for clock sync done to drop via QACSR[36/37]"); - // Poll for clock sync done to drop do { GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QACSR, qloop), scom_data); } while(((~scom_data >> SHIFT64(37)) & ex) != ex); - PK_TRACE("SE8.g"); - // Switch glsmux to refclk to save clock grid power + PK_TRACE("Switch glsmux to refclk to save clock grid power via EXCGCR[34/35]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_CLR, qloop), ((uint64_t)ex << SHIFT64(35))); - PK_TRACE("SE8.h"); - if (ex & FST_EX_IN_QUAD) { cloop = 0; @@ -340,8 +352,17 @@ p9_sgpe_stop_entry() for(; cloop < climit; cloop++) { + // Check partial good core + if (!(G_sgpe_stop_record.group.core[VECTOR_CONFIG] & + BIT32(((qloop << 2) + cloop)))) + { + continue; + } + // request levle already set by CME // shift by 2 == times 4, which is cores per quad + PK_TRACE("Update STOP history on core[%d]: in stop level 8", + ((qloop << 2) + cloop)); SGPE_STOP_UPDATE_HISTORY(((qloop << 2) + cloop), CORE_ADDR_BASE, STOP_CORE_IS_GATED, @@ -352,19 +373,19 @@ p9_sgpe_stop_entry() STOP_ACT_ENABLE); } - // Update QSSR: l2_stopped, drop stop_entry_ongoing + PK_TRACE("Update QSSR: l2_stopped, drop stop_entry_ongoing"); out32(OCB_QSSR_CLR, BIT32(qloop + 20)); out32(OCB_QSSR_OR, (ex << SHIFT32((qloop << 1) + 1))); + PK_TRACE_INF("SE8.B: L2 Clock Sync Dropped"); + //================================================== MARK_TAG(SE_STOP8_DONE, ((ex << 6) | (32 >> qloop))) //================================================== }; - // ------------------------------------------------------------------------ - // QUAD STOP ENTRY [LEVEL 11-15] - // ------------------------------------------------------------------------ + for(qentry = G_sgpe_stop_record.group.quad[VECTOR_ENTRY], qloop = 0, ex = 0; qentry > 0; @@ -376,6 +397,10 @@ p9_sgpe_stop_entry() continue; } + // ------------------------------------------------------------------------ + PK_TRACE("+++++ +++++ QUAD STOP ENTRY [LEVEL 11-15] +++++ +++++"); + // ------------------------------------------------------------------------ + if (G_sgpe_stop_record.group.ex_l[VECTOR_CONFIG] & BIT32(qloop)) { ex |= FST_EX_IN_QUAD; @@ -386,12 +411,12 @@ p9_sgpe_stop_entry() ex |= SND_EX_IN_QUAD; } - PK_TRACE("q[%d]x[%d] starts quad entry", qloop, ex); + PK_TRACE_INF("Check: q[%d]ex[%d] starts quad entry", qloop, ex); - // Update QSSR: stop_entry_ongoing + PK_TRACE("Update QSSR: stop_entry_ongoing"); out32(OCB_QSSR_OR, BIT32(qloop + 20)); - // Update Quad STOP History + PK_TRACE("Update STOP history on quad[%d]: update request stop level", qloop); SGPE_STOP_UPDATE_HISTORY(qloop, QUAD_ADDR_BASE, STOP_CACHE_IS_GATED, @@ -405,9 +430,8 @@ p9_sgpe_stop_entry() MARK_TAG(SE_PURGE_L3, (32 >> qloop)) //================================== - PK_TRACE("SE11.a"); + PK_TRACE("Drop LCO prior to purge via EX_PM_LCO_DIS_REG[0]"); - // Disable LCO prior to purge if(ex & FST_EX_IN_QUAD) { GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_LCO_DIS_REG, qloop, 0), @@ -421,9 +445,9 @@ p9_sgpe_stop_entry() } #if !SKIP_L3_PURGE - PK_TRACE("SE11.b"); - // Assert Purge L3 + PK_TRACE("Assert purge L3 via EX_PM_PURGE_REG[0]"); + if(ex & FST_EX_IN_QUAD) { GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 0), BIT64(0)); @@ -436,21 +460,22 @@ p9_sgpe_stop_entry() // todo: stop debug trace, attribute may be needed - PK_TRACE("SE11.d"); + PK_TRACE("Poll for L3 purge done via EX_PM_PURGE_REG[0]"); - // Poll for purge done on the same request bit thus no need to deassert + // Poll on the same request bit thus no need to deassert do { + #if !SKIP_L3_PURGE_ABORT if (in32(OCB_OISR1) & (BITS32(15, 2) | BIT32(19))) { - PK_TRACE("SE: interrupt detected"); + PK_TRACE_INF("Abort: interrupt detected"); if ((in32(OCB_OPITNPRA(2)) & BITS32((qloop << 2), 4)) || (in32(OCB_OPITNPRA(3)) & BITS32((qloop << 2), 4))) { - PK_TRACE("SE: core interrupt detected"); + PK_TRACE_INF("Abort: core interrupt detected"); for(cloop = 0; cloop < CORES_PER_QUAD; cloop++) { @@ -459,7 +484,7 @@ p9_sgpe_stop_entry() (in32(OCB_OPIT3CN(((qloop << 2) + cloop))) & TYPE3_PAYLOAD_EXIT_EVENT)) { - PK_TRACE("SE: core wakeup detected"); + PK_TRACE_INF("Abort: core wakeup detected"); l3_purge_aborted = 1; break; } @@ -469,7 +494,7 @@ p9_sgpe_stop_entry() if ((in32(OCB_OPIT6PRB) & BIT32(qloop)) && (in32(OCB_OPIT6QN(qloop)) & TYPE6_PAYLOAD_EXIT_EVENT)) { - PK_TRACE("SE: quad wakeup detected"); + PK_TRACE_INF("Abort: quad wakeup detected"); l3_purge_aborted = 1; } @@ -480,7 +505,8 @@ p9_sgpe_stop_entry() MARK_TAG(SE_PURGE_L3_ABORT, (32 >> qloop)) //======================================== - // Assert Purge L3 Abort + PK_TRACE_INF("Abort: assert purge L3 abort"); + if (ex & FST_EX_IN_QUAD) GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 0), BIT64(2)); @@ -489,7 +515,8 @@ p9_sgpe_stop_entry() GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 1), BIT64(2)); - // Poll for Abort Done + PK_TRACE_INF("Abort: poll for abort done"); + if(ex & FST_EX_IN_QUAD) { do @@ -514,7 +541,8 @@ p9_sgpe_stop_entry() MARK_TAG(SE_PURGE_L3_ABORT_DONE, (32 >> qloop)) //============================================= - // Deassert LCO Disable + PK_TRACE_INF("Abort: Drop LCO Disable"); + if (ex & FST_EX_IN_QUAD) GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_LCO_DIS_REG, qloop, 0), 0); @@ -523,7 +551,7 @@ p9_sgpe_stop_entry() GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_LCO_DIS_REG, qloop, 1), 0); - // Notify PGPE to resume + // TODO Notify PGPE to resume } } @@ -547,44 +575,48 @@ p9_sgpe_stop_entry() if (l3_purge_aborted) { + PK_TRACE_INF("Abort: L3 Purge Aborted"); continue; } + PK_TRACE_INF("SE11.A: L3 Purged"); + #endif //================================== MARK_TAG(SE_PURGE_PB, (32 >> qloop)) //================================== - PK_TRACE("SE11.g"); - // Assert PowerBus purge + PK_TRACE("Assert powerbus purge via QCCR[30]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WOR, qloop), BIT64(30)); - PK_TRACE("SE11.h"); + PK_TRACE("Poll PowerBus purge done via QCCR[31]"); - // Poll PowerBus purge done do { GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR, qloop), scom_data); } while(!(scom_data & BIT64(31))); - PK_TRACE("SE11.i"); - // Deassert PowerBus purge + PK_TRACE("Drop powerbus purge via QCCR[30]"); // todo may need to move this to wakeup GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(30)); + PK_TRACE_INF("SE11.B: PowerBus Purged"); + //=========================================== MARK_TAG(SE_WAIT_PGPE_SUSPEND, (32 >> qloop)) //=========================================== + // TODO: Poll PGPE Suspend Ack //====================================== MARK_TAG(SE_QUIESCE_QUAD, (32 >> qloop)) //====================================== - // todo halt cme here - PK_TRACE("SE11.j"); + // TODO halt cme here + + PK_TRACE("Assert refresh quiesce prior to L3 (refresh domain) stop clk via EX_DRAM_REF_REG[7]"); // Assert refresh quiesce prior to L3 (refresh domain) stop clk // Edram quiesce is asserted by hardware when l3 thold is asserted in cc @@ -602,7 +634,8 @@ p9_sgpe_stop_entry() GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, qloop, 1), scom_data); } - // Check NCU_SATUS_REG[0:3] for all zeros + PK_TRACE("Check NCU_SATUS_REG[0:3] for all zeros"); + if (ex & FST_EX_IN_QUAD) { do @@ -623,29 +656,26 @@ p9_sgpe_stop_entry() while((~scom_data & BITS64(0, 4)) != BITS64(0 , 4)); } + PK_TRACE_INF("SE11.C: NCU Status Clean"); + //=========================== MARK_TRAP(SE_STOP_CACHE_CLKS) //=========================== - PK_TRACE("SE11.k"); - // Raise Cache Logical fence + PK_TRACE("Assert cache chiplet fence via NET_CTRL0[18]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, qloop), BIT64(18)); - // clock off cache chiplet - PK_TRACE("SE11.l"); - // Set all bits to zero prior stop core clocks + PK_TRACE("Clear SCAN_REGION prior to stop cache clocks"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_SCAN_REGION_TYPE, qloop), 0); - PK_TRACE("SE11.m"); - // Stop Cache Clocks + PK_TRACE("Stop cache clocks via CLK_REGION"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLK_REGION, qloop), (CLK_STOP_CMD | CLK_THOLD_ALL | CLK_REGION_ALL_BUT_EX | ((uint64_t)ex << SHIFT64(7)) | ((uint64_t)ex << SHIFT64(13)))); - PK_TRACE("SE11.n"); - // Poll for Cache clocks stopped + PK_TRACE("Poll for cache clocks stopped via CPLT_STAT0[8]"); do { @@ -653,27 +683,27 @@ p9_sgpe_stop_entry() } while((~scom_data) & BIT64(8)); + PK_TRACE("Check core clock is stopped via CLOCK_STAT_SL[4-13]"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLOCK_STAT_SL, qloop), scom_data); if (((~scom_data) & (CLK_REGION_ALL_BUT_EX | ((uint64_t)ex << SHIFT64(7)) | ((uint64_t)ex << SHIFT64(13)))) != 0) { - PK_TRACE("Cache clock stop failed"); + PK_TRACE("ERROR: Cache clock stop failed. HALT SGPE!"); pk_halt(); } // MF: verify compiler generate single rlwmni // MF: delay may be needed for stage latch to propagate thold - PK_TRACE("SE11: Cache Clock Stopped"); - - PK_TRACE("SE11.o"); - // Switch glsmux to refclk to save clock grid power + PK_TRACE("Switch glsmux to refclk to save clock grid power via CGCR[3]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_PPM_CGCR, qloop), 0); - // Assert Vital Fence + + PK_TRACE("Assert vital fence via CPLT_CTRL1[3]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_OR, qloop), BIT64(3)); - // Raise Partial Good Fences + + PK_TRACE("Assert partial good regional fences via CPLT_CTRL1[4-14]"); // Must cover partial bad fences as well or powerbus error will raise // Note: Stop11 will lose all the fences so here needs to assert them GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_OR, qloop), @@ -681,30 +711,36 @@ p9_sgpe_stop_entry() ((uint64_t)ex << SHIFT64(7)) | ((uint64_t)ex << SHIFT64(9)) | ((uint64_t)ex << SHIFT64(13)))); + /// @todo add VDM_ENABLE attribute control - PK_TRACE("Assert vdm enable via CPPM_VDMCR[0]"); + PK_TRACE("Drop vdm enable via CPPM_VDMCR[0]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_VDMCR_CLR, qloop), BIT64(0)); + PK_TRACE_INF("SE11.D: Cache Clock Stopped"); + //========================================= MARK_TAG(SE_POWER_OFF_CACHE, (32 >> qloop)) //========================================= -#if HW386311_PBIE_RW_PTR_STOP11_FIX +#if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX + + PK_TRACE_INF("FCMS: Engage with PBIE Read/Write Pointer Scan Workaround"); + // bit4,5,11 = perv/eqpb/pbieq, bit59 = inex - PK_TRACE("SE: Setup scan register to select the ring"); + PK_TRACE("FCMS: Setup scan register to select the ring"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10030005, qloop), BITS64(4, 2) | BIT64(11) | BIT64(59)); - PK_TRACE("SE: checkword set"); + PK_TRACE("FCMS: checkword set"); scom_data = 0xa5a5a5a5a5a5a5a5; GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); for(spin = 1;; spin++) { - PK_TRACE("SE: spin ring loop%d", spin); + PK_TRACE("FCMS: spin ring loop%d", spin); scom_data = (G_ring_spin[spin][0] - G_ring_spin[spin - 1][0]) << 32; GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10039000, qloop), scom_data); - PK_TRACE("SE: Poll OPCG done for ring spin"); + PK_TRACE("FCMS: Poll OPCG done for ring spin"); do { @@ -714,47 +750,51 @@ p9_sgpe_stop_entry() if (spin == 9) { - PK_TRACE("SE: checkword check"); + PK_TRACE("FCMS: checkword check"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); if (scom_data != 0xa5a5a5a5a5a5a5a5) { - PK_TRACE("checkword[%x%x] failed", UPPER32(scom_data), LOWER32(scom_data)); + PK_TRACE("ERROR: checkword[%x%x] failed. HALT SGPE!", + UPPER32(scom_data), LOWER32(scom_data)); pk_halt(); } break; } - PK_TRACE("SE: save pbie read ptr"); + PK_TRACE("FCMS: save pbie read ptr"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); EXTRACT_RING_BITS(G_ring_spin[spin][1], scom_data, G_ring_save[qloop][spin - 1]); - PK_TRACE("SE: mask: %8x %8x", + PK_TRACE("FCMS: mask: %8x %8x", UPPER32(G_ring_spin[spin][1]), LOWER32(G_ring_spin[spin][1])); - PK_TRACE("SE: ring: %8x %8x", + PK_TRACE("FCMS: ring: %8x %8x", UPPER32(scom_data), LOWER32(scom_data)); - PK_TRACE("SE: save: %8x %8x", + PK_TRACE("FCMS: save: %8x %8x", UPPER32(G_ring_save[qloop][spin - 1]), LOWER32(G_ring_save[qloop][spin - 1])); } GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10030005, qloop), 0); + #endif - // DD: Assert Cache Vital Thold/PCB Fence/Electrical Fence - PK_TRACE("SE11.q"); + PK_TRACE("Assert PCB fence via NET_CTRL0[25]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, qloop), BIT64(25)); + + PK_TRACE("Assert electrical fence via NET_CTRL0[26]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, qloop), BIT64(26)); + + PK_TRACE("Assert vital thold via NET_CTRL0[16]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, qloop), BIT64(16)); - // L3 edram shutdown + PK_TRACE("Shutdown L3[%d] EDRAM via QCCR[0-3/4-7]", ex); // QCCR[0/4] EDRAM_ENABLE_DC // QCCR[1/5] EDRAM_VWL_ENABLE_DC // QCCR[2/6] L3_EX0/1_EDRAM_VROW_VBLH_ENABLE_DC // QCCR[3/7] EDRAM_VPP_ENABLE_DC - PK_TRACE("SE11.r"); if (ex & SND_EX_IN_QUAD) { @@ -781,23 +821,20 @@ p9_sgpe_stop_entry() } #if !STOP_PRIME - // todo needed? - // Prepare PFET Controls + + PK_TRACE("Drop vdd/vcs_pfet_val/sel_override/regulation_finger_en via PFCS[4-7,8]"); // vdd_pfet_val/sel_override = 0 (disbaled) // vcs_pfet_val/sel_override = 0 (disbaled) // vdd_pfet_regulation_finger_en = 0 (controled by FSM) - PK_TRACE("SE11.t"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_CLR, qloop), BITS64(4, 4) | BIT64(8)); - // Power Off Cache VDS then VDD + PK_TRACE("Power off VCS via PFCS[2-3]"); // vcs_pfet_force_state = 01 (Force Voff) - PK_TRACE("SE11.u"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_OR, qloop), BIT64(3)); + PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle) via PFCS[50]"); // todo: poll the sense line instead - // Poll for power gate sequencer state: 0x8 (FSM Idle) - PK_TRACE("SE11.v"); do { @@ -805,13 +842,12 @@ p9_sgpe_stop_entry() } while(!(scom_data & BIT64(50))); + PK_TRACE("Power off VDD via PFCS[0-1]"); // vdd_pfet_force_state = 01 (Force Voff) - PK_TRACE("SE11.u"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_OR, qloop), BIT64(1)); + PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle) via PFCS[42]"); // todo: poll the sense line instead - // Poll for power gate sequencer state: 0x8 (FSM Idle) - PK_TRACE("SE11.v"); do { @@ -819,19 +855,31 @@ p9_sgpe_stop_entry() } while(!(scom_data & BIT64(42))); - // Turn Off Force Voff + PK_TRACE("Turn off force voff via PFCS[0-3]"); // vdd_pfet_force_state = 00 (Nop) // vcs_pfet_force_state = 00 (Nop) - PK_TRACE("SE11.x"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_CLR, qloop), BITS64(0, 4)); + PK_TRACE_INF("SE11.E: Cache Powered Off"); + #endif - PK_TRACE("SE11.y"); + PK_TRACE("Drop CME_INTERPPM_DPLL_ENABLE after DPLL is stopped via QPMMR[26]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QPMMR_CLR, qloop), BIT64(20) | BIT64(22) | BIT64(24) | BIT64(26)); + G_sgpe_stop_record.state[qloop].act_state_q = STOP_LEVEL_11; for(cloop = 0; cloop < CORES_PER_QUAD; cloop++) { + // Check partial good core + if (!(G_sgpe_stop_record.group.core[VECTOR_CONFIG] & + BIT32(((qloop << 2) + cloop)))) + { + continue; + } + + PK_TRACE("Update STOP history on core[%d]: in stop level 11", + ((qloop << 2) + cloop)); SGPE_STOP_UPDATE_HISTORY(((qloop << 2) + cloop), CORE_ADDR_BASE, STOP_CORE_IS_GATED, @@ -842,6 +890,7 @@ p9_sgpe_stop_entry() STOP_ACT_ENABLE); } + PK_TRACE("Update STOP history on quad[%d]: in stop level 11", qloop); SGPE_STOP_UPDATE_HISTORY(qloop, QUAD_ADDR_BASE, STOP_CACHE_IS_GATED, @@ -851,10 +900,10 @@ p9_sgpe_stop_entry() STOP_REQ_DISABLE, STOP_ACT_ENABLE); - // Update QSSR: quad_stopped + PK_TRACE("Update QSSR: quad_stopped"); out32(OCB_QSSR_OR, BIT32(qloop + 14)); - // Update QSSR: drop stop_entry_ongoing + PK_TRACE("Update QSSR: drop stop_entry_ongoing"); out32(OCB_QSSR_CLR, BIT32(qloop + 20)); //===================================== @@ -862,7 +911,11 @@ p9_sgpe_stop_entry() //===================================== } - //loop quad to drop spwu done + clear qswu + //-------------------------------------------------------------------------- + PK_TRACE_INF("+++++ +++++ END OF STOP ENTRY +++++ +++++"); + //-------------------------------------------------------------------------- + + //loop quad to clear qswu record for(qloop = 0; qloop < MAX_QUADS; qloop++) { if (G_sgpe_stop_record.group.qswu[VECTOR_ENTRY] & BIT32(qloop)) @@ -874,5 +927,6 @@ p9_sgpe_stop_entry() //============================ MARK_TRAP(ENDSCOPE_STOP_ENTRY) //============================ + return SGPE_STOP_SUCCESS; } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c index 2b9c3b25..dea77fff 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c @@ -26,16 +26,21 @@ #include "p9_sgpe_stop.h" #include "p9_sgpe_stop_exit_marks.h" #include "p9_hcd_sgpe_boot_cme.h" -#include "p9_hcd_cache_initf.h" +//#include "p9_dd1_doorbell_wr.h" extern SgpeStopRecord G_sgpe_stop_record; -#if HW386311_PBIE_RW_PTR_STOP11_FIX + +#if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX + extern uint64_t G_ring_save[MAX_QUADS][8]; extern uint64_t G_ring_spin[10][2]; + #endif #if FUSED_CORE_MODE_SCAN_FIX + uint32_t G_fcm_spin[4] = {0, 435, 1402, 2411}; + #endif int @@ -53,23 +58,26 @@ p9_sgpe_stop_exit() uint64_t cme_flags; ppm_sshsrc_t hist; ocb_ccsr_t ccsr; -#if HW386311_PBIE_RW_PTR_STOP11_FIX +#if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX int spin; #endif + //=============================== MARK_TAG(BEGINSCOPE_STOP_EXIT, 0) //=============================== - PK_TRACE("Core Exit Vectors: X[%x] X0[%x] X1[%x] Q[%x]", - G_sgpe_stop_record.group.ex_b[VECTOR_EXIT], - G_sgpe_stop_record.group.ex_l[VECTOR_EXIT], - G_sgpe_stop_record.group.ex_r[VECTOR_EXIT], - G_sgpe_stop_record.group.quad[VECTOR_EXIT]); + PK_TRACE_INF("Core Exit Vectors: X[%x] X0[%x] X1[%x] Q[%x]", + G_sgpe_stop_record.group.ex_b[VECTOR_EXIT], + G_sgpe_stop_record.group.ex_l[VECTOR_EXIT], + G_sgpe_stop_record.group.ex_r[VECTOR_EXIT], + G_sgpe_stop_record.group.quad[VECTOR_EXIT]); + + for(cexit = G_sgpe_stop_record.group.core[VECTOR_EXIT], qspwu = G_sgpe_stop_record.group.qswu[VECTOR_EXIT], qloop = 0, m_l2 = 0, m_pg = 0; - cexit > 0 || qspwu > 0; + (cexit > 0 || qspwu > 0) && (qloop < MAX_QUADS); cexit = cexit << 4, qspwu = qspwu << 1, qloop++, m_l2 = 0, m_pg = 0) { @@ -78,6 +86,10 @@ p9_sgpe_stop_exit() continue; } + //-------------------------------------------------------------------------- + PK_TRACE_INF("+++++ +++++ BEGIN OF STOP EXIT +++++ +++++"); + //-------------------------------------------------------------------------- + if (G_sgpe_stop_record.group.ex_l[VECTOR_CONFIG] & BIT32(qloop)) { m_pg |= FST_EX_IN_QUAD; @@ -102,9 +114,11 @@ p9_sgpe_stop_exit() m_l2 = m_l2 & m_pg; - PK_TRACE("quad[%d]m_l2[%d]m_pg[%d]", qloop, m_l2, m_pg); + PK_TRACE_INF("Check: quad[%d] m_l2[%d] m_pg[%d]", qloop, m_l2, m_pg); - // Update QSSR: stop_exit_ongoing + + + PK_TRACE("Update QSSR: stop_exit_ongoing"); out32(OCB_QSSR_OR, BIT32(qloop + 26)); for(cloop = 0; cloop < CORES_PER_QUAD; cloop++) @@ -114,6 +128,8 @@ p9_sgpe_stop_exit() continue; } + PK_TRACE("Update STOP history on core[%d]: in transition of exit", + ((qloop << 2) + cloop)); SGPE_STOP_UPDATE_HISTORY(((qloop << 2) + cloop), CORE_ADDR_BASE, STOP_CORE_IS_GATED, @@ -124,8 +140,17 @@ p9_sgpe_stop_exit() STOP_ACT_DISABLE); } + + if(m_l2 && G_sgpe_stop_record.state[qloop].act_state_q >= STOP_LEVEL_11) { + + //-------------------------------------------------------------------------- + PK_TRACE_INF("+++++ +++++ QUAD STOP EXIT [LEVEL 11-15] +++++ +++++"); + //-------------------------------------------------------------------------- + + PK_TRACE("Update STOP history on quad[%d]: in transition of exit", + qloop); SGPE_STOP_UPDATE_HISTORY(qloop, QUAD_ADDR_BASE, STOP_CACHE_IS_GATED, @@ -139,66 +164,110 @@ p9_sgpe_stop_exit() MARK_TAG(SX_POWERON, (32 >> qloop)) //================================= - PK_TRACE("Cache Poweron"); + // NOTE: it is required to serialize power on quad PFETs to prevent droop + PK_TRACE_INF("SX11.A: Cache[%d] Poweron", qloop); p9_hcd_cache_poweron(qloop); //========================= MARK_TRAP(SX_CHIPLET_RESET) //========================= - PK_TRACE("Cache Chiplet Reset m_pg[%d]", m_pg); + PK_TRACE_INF("SX11.B: Cache[%d] Chiplet Reset with PG[%d]", qloop, m_pg); p9_hcd_cache_chiplet_reset(qloop, m_pg); +#if !STOP_INITF + + PK_TRACE_INF("SX11.C: Cache[%d] Chiplet L3 DCC Setup", qloop); + p9_hcd_cache_chiplet_l3_dcc_setup(qloop); + +#endif + + #if !STOP_PRIME - PK_TRACE("Cache Gptr Time Initf"); +#if !STOP_INITF + + PK_TRACE_INF("SX11.D: Cache[%d] Gptr Time Initf", qloop); p9_hcd_cache_gptr_time_initf(qloop); + #endif //==================================== MARK_TAG(SX_DPLL_SETUP, (32 >> qloop)) //==================================== - ///@todo dpll_initf +#if !STOP_INITF + + PK_TRACE_INF("SX11.E: Cache[%d] Dpll Initf", qloop); + p9_hcd_cache_dpll_initf(qloop); + +#endif - PK_TRACE("Cache Dpll Setup"); + PK_TRACE_INF("SX11.F: Cache[%d] Dpll Setup", qloop); p9_hcd_cache_dpll_setup(qloop); -#if !STOP_PRIME +#if !STOP_INITF + + PK_TRACE_INF("SX11.G: Cache[%d] DCC Skewadjust Setup", qloop); + p9_hcd_cache_dcc_skewadjust_setup(qloop); + +#endif + + // set 20, 22, 24 and 26 during Stop11 Exit after setting up the DPLL + scom_data = BIT64(20) | BIT64(22) | BIT64(24) | BIT64(26); + + // set 21, 23, 25, and 27 if EX0 is bad (not partial good) + if ((~m_pg) & FST_EX_IN_QUAD) + { + scom_data |= BIT64(21) | BIT64(23) | BIT64(25) | BIT64(27); + } + + PK_TRACE("Assert inter-ppm settings via QPMMR[22,24,26,EX0PB:21,23,25]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QPMMR_OR, qloop), scom_data); + //======================================= MARK_TAG(SX_CHIPLET_INITS, (32 >> qloop)) //======================================= - PK_TRACE("Cache Chiplet Init"); + PK_TRACE_INF("SX11.H: Cache[%d] Chiplet Init", qloop); p9_hcd_cache_chiplet_init(qloop); - PK_TRACE("Cache Repair Initf"); +#if !STOP_INITF + + PK_TRACE_INF("SX11.I: Cache[%d] Repair Initf", qloop); p9_hcd_cache_repair_initf(qloop); +#endif + //==================================== MARK_TAG(SX_ARRAY_INIT, (32 >> qloop)) //==================================== + #if !SKIP_ARRAYINIT - PK_TRACE("Cache Arrayinit"); + PK_TRACE_INF("SX11.J: Cache[%d] Arrayinit", qloop); p9_hcd_cache_arrayinit(qloop, m_pg); + #endif #if FUSED_CORE_MODE_SCAN_FIX + + PK_TRACE_INF("FCMS: Engage with Fused Mode Scan Workaround"); + // bit8/9 = l2-0/1, bit49 = cfg - PK_TRACE("FC: Setup scan register to select the ring"); + PK_TRACE("FCMS: Setup scan register to select the ring"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10030005, qloop), BITS64(8, 2) | BIT64(49)); - PK_TRACE("FC: checkword set"); + PK_TRACE("FCMS: checkword set"); scom_data = 0xa5a5a5a5a5a5a5a5; GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); for(spin = 1;; spin++) { - PK_TRACE("FC: spin ring loop%d", spin); + PK_TRACE("FCMS: spin ring loop%d", spin); scom_data = (G_fcm_spin[spin] - G_fcm_spin[spin - 1]) << 32; GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10039000, qloop), scom_data); - PK_TRACE("FC: Poll OPCG done for ring spin"); + PK_TRACE("FCMS: Poll OPCG done for ring spin"); do { @@ -208,43 +277,48 @@ p9_sgpe_stop_exit() if (spin == 3) { - PK_TRACE("FC: checkword check"); + PK_TRACE("FCMS: checkword check"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); if (scom_data != 0xa5a5a5a5a5a5a5a5) { - PK_TRACE("FC: checkword[%x%x] failed", UPPER32(scom_data), LOWER32(scom_data)); + PK_TRACE("ERROR: checkword[%x%x] failed. HALT SGPE!", + UPPER32(scom_data), LOWER32(scom_data)); pk_halt(); } break; } - PK_TRACE("FC: restore fused core mode bit"); + PK_TRACE("FCMS: restore fused core mode bit"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); RESTORE_RING_BITS(BIT64(0), scom_data, BIT64(0)); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); } GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10030005, qloop), 0); + #endif -#if HW386311_PBIE_RW_PTR_STOP11_FIX +#if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX + + PK_TRACE_INF("FCMS: Engage with PBIE Read/Write Pointer Scan Workaround"); + // bit4,5,11 = perv/eqpb/pbieq, bit59 = inex - PK_TRACE("SX: Setup scan register to select the ring"); + PK_TRACE("PBRW: Setup scan register to select the ring"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10030005, qloop), BITS64(4, 2) | BIT64(11) | BIT64(59)); - PK_TRACE("SX: checkword set"); + PK_TRACE("PBRW: checkword set"); scom_data = 0xa5a5a5a5a5a5a5a5; GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); for(spin = 1;; spin++) { - PK_TRACE("SX: spin ring loop%d", spin); + PK_TRACE("PBRW: spin ring loop%d", spin); scom_data = (G_ring_spin[spin][0] - G_ring_spin[spin - 1][0]) << 32; GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x10039000, qloop), scom_data); - PK_TRACE("SX: Poll OPCG done for ring spin"); + PK_TRACE("PBRW: Poll OPCG done for ring spin"); do { @@ -254,38 +328,39 @@ p9_sgpe_stop_exit() if (spin == 9) { - PK_TRACE("SX: checkword check"); + PK_TRACE("PBRW: checkword check"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); if (scom_data != 0xa5a5a5a5a5a5a5a5) { - PK_TRACE("checkword[%x%x] failed", UPPER32(scom_data), LOWER32(scom_data)); + PK_TRACE_INF("ERROR: checkword[%x%x] failed. HALT SGPE!", + UPPER32(scom_data), LOWER32(scom_data)); pk_halt(); } break; } - PK_TRACE("SX: restore pbie read ptr"); + PK_TRACE("PBRW: restore pbie read ptr"); GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); - PK_TRACE("SE: mask: %8x %8x", + PK_TRACE("PBRW: mask: %8x %8x", UPPER32(G_ring_spin[spin][1]), LOWER32(G_ring_spin[spin][1])); - PK_TRACE("SE: ring: %8x %8x", + PK_TRACE("PBRW: ring: %8x %8x", UPPER32(scom_data), LOWER32(scom_data)); - PK_TRACE("SE: save: %8x %8x", + PK_TRACE("PBRW: save: %8x %8x", UPPER32(G_ring_save[qloop][spin - 1]), LOWER32(G_ring_save[qloop][spin - 1])); RESTORE_RING_BITS(G_ring_spin[spin][1], scom_data, G_ring_save[qloop][spin - 1]); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(0x1003E000, qloop), scom_data); - PK_TRACE("SE: mask: %8x %8x", + PK_TRACE("PBRW: mask: %8x %8x", UPPER32(G_ring_spin[spin][1]), LOWER32(G_ring_spin[spin][1])); - PK_TRACE("SE: ring: %8x %8x", + PK_TRACE("PBRW: ring: %8x %8x", UPPER32(scom_data), LOWER32(scom_data)); - PK_TRACE("SE: save: %8x %8x", + PK_TRACE("PBRW: save: %8x %8x", UPPER32(G_ring_save[qloop][spin - 1]), LOWER32(G_ring_save[qloop][spin - 1])); @@ -298,42 +373,41 @@ p9_sgpe_stop_exit() MARK_TRAP(SX_FUNC_INIT) //===================== - PK_TRACE("Cache Initf"); +#if !SKIP_INITF + + PK_TRACE_INF("SX11.K: Cache[%d] Func Scan", qloop); p9_hcd_cache_initf(qloop); -#if !ISTEP15_HACK - asm volatile ("nop"); -#else - asm volatile ("tw 31, 0, 0"); -#endif #endif +#endif //=========================================== MARK_TAG(SX_CACHE_STARTCLOCKS, (32 >> qloop)) //=========================================== - PK_TRACE("Cache Startclocks m_pg[%d]", m_pg); + PK_TRACE_INF("SX11.L: Cache[%d] Startclocks with PG[%d]", qloop, m_pg); p9_hcd_cache_startclocks(qloop, m_pg); } if (m_l2) { + + //-------------------------------------------------------------------------- + PK_TRACE_INF("+++++ +++++ EX STOP EXIT [LEVEL 8-10] +++++ +++++"); + //-------------------------------------------------------------------------- + //======================================================== MARK_TAG(SX_L2_STARTCLOCKS, ((m_l2 << 6) | (32 >> qloop))) //======================================================== // do this again here for stop8 in addition to dpll_setup - PK_TRACE("4S8: Switch L2 glsmux select to DPLL output"); + PK_TRACE("Switch L2 glsmux select to DPLL output via EXCGCR[34,35]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_OR, qloop), BITS64(34, 2)); - PK_TRACE("Cache L2 Startclocks"); + PK_TRACE_INF("SX8.A: Cache[%d] L2[%d] Startclocks with PG[%d]", + qloop, m_l2, m_pg); p9_hcd_cache_l2_startclocks(qloop, m_l2, m_pg); -#if !ISTEP15_HACK - asm volatile ("nop"); -#else - asm volatile ("tw 31, 0, 0"); -#endif // reset ex actual state if ex is exited. if (m_l2 & FST_EX_IN_QUAD) @@ -346,14 +420,17 @@ p9_sgpe_stop_exit() G_sgpe_stop_record.state[qloop].act_state_x1 = 0; } - - - // Update QSSR: drop l2_stopped, + PK_TRACE("Update QSSR: drop l2_stopped"); out32(OCB_QSSR_CLR, (m_l2 << SHIFT32((qloop << 1) + 1))); } if(m_l2 && G_sgpe_stop_record.state[qloop].act_state_q >= STOP_LEVEL_11) { + + //-------------------------------------------------------------------------- + PK_TRACE_INF("+++++ +++++ QUAD STOP EXIT CONTINUE +++++ +++++"); + //-------------------------------------------------------------------------- + for(cme = 0; cme < EXES_PER_QUAD; cme += 2) { @@ -364,12 +441,14 @@ p9_sgpe_stop_exit() continue; } - // Raise Core-L2 + Core-CC Quiesces + PK_TRACE("Assert core[%d]-L2/CC quiesces via SICR[6/7,8/9]", core); GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SICR_OR, qloop, (cme >> 1)), ((uint64_t)core << SHIFT64(7) | (uint64_t)core << SHIFT64(9))); + PK_TRACE("Poll for interface quiesced via CME[%d] SISR[30,31]", cme); + do { GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SISR, @@ -379,14 +458,15 @@ p9_sgpe_stop_exit() } #if !STOP_PRIME + //==================================== MARK_TAG(SX_SCOM_INITS, (32 >> qloop)) //==================================== - PK_TRACE("Cache Scom Init"); - p9_hcd_cache_scominit(qloop); + PK_TRACE_INF("SX11.M: Cache[%d] Scom Init with PG[%d]", qloop, m_pg); + p9_hcd_cache_scominit(qloop, m_pg); - PK_TRACE("Cache Scom Cust"); + PK_TRACE_INF("SX11.N: Cache[%d] Scom Cust", qloop); p9_hcd_cache_scomcust(qloop); //================================== @@ -401,11 +481,17 @@ p9_sgpe_stop_exit() continue; } - PK_TRACE("Doorbell1 the CME %d", ((qloop << 2) + cloop)); + PK_TRACE_INF("SX11.O: Core[%d] DB1 to CME", ((qloop << 2) + cloop)); GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CMEMSG, ((qloop << 2) + cloop)), BIT64(0)); GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CMEDB1_OR, ((qloop << 2) + cloop)), BIT64(7)); + /* + p9_dd1_db_unicast_wr(GPE_SCOM_ADDR_CORE(CPPM_CMEMSG, + ((qloop << 2) + cloop)), BIT64(0)); + p9_dd1_db_unicast_wr(GPE_SCOM_ADDR_CORE(CPPM_CMEDB1_OR, + ((qloop << 2) + cloop)), BIT64(7)); + */ } // Setting up cme_flags @@ -481,31 +567,38 @@ p9_sgpe_stop_exit() if (in32(OCB_OCCFLG) & BIT32(13)) { + PK_TRACE_INF("BREAK: Trap Before CME Boot"); asm volatile ("trap"); } #if !SKIP_CME_BOOT_STOP11 + uint16_t cmeBootList = (m_pg << SHIFT16(((qloop << 1) + 1))); - PK_TRACE("Boot CME [%x]", cmeBootList); + PK_TRACE_INF("SX11.P: Boot CME[%x]", cmeBootList); boot_cme( cmeBootList ); + #endif //======================================= MARK_TAG(SX_RUNTIME_INITS, (32 >> qloop)) //======================================= - PK_TRACE("Cache RAS Runtime Scom"); + PK_TRACE_INF("SX11.Q: Cache[%d] RAS Runtime Scom", qloop); p9_hcd_cache_ras_runtime_scom(qloop); - PK_TRACE("Cache OCC Runtime Scom"); + PK_TRACE_INF("SX11.R: Cache[%d] OCC Runtime Scom", qloop); p9_hcd_cache_occ_runtime_scom(qloop); //========================= MARK_TRAP(SX_ENABLE_ANALOG) //========================= + #endif + G_sgpe_stop_record.state[qloop].act_state_q = 0; + PK_TRACE("Update STOP history on quad[%d]: \ + STOP exit completed, cache ready", qloop); SGPE_STOP_UPDATE_HISTORY(qloop, QUAD_ADDR_BASE, STOP_CACHE_READY_RUN, @@ -515,14 +608,19 @@ p9_sgpe_stop_exit() STOP_REQ_DISABLE, STOP_ACT_DISABLE); - // Update QSSR: drop quad_stopped - out32(OCB_QSSR_CLR, BIT32(qloop + 26)); + PK_TRACE("Update QSSR: drop quad_stopped"); + out32(OCB_QSSR_CLR, BIT32(qloop + 14)); } - // assert quad special wakeup done + //-------------------------------------------------------------------------- + PK_TRACE_INF("+++++ +++++ END OF STOP EXIT +++++ +++++"); + //-------------------------------------------------------------------------- + if (qspwu & BIT32(0)) { + PK_TRACE_INF("SX0.A: Assert Quad[%d] SPWU Done", qloop); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_GPMMR_OR, qloop), BIT64(0)); + G_sgpe_stop_record.group.qswu[VECTOR_CONFIG] |= BIT32(qloop); G_sgpe_stop_record.group.qswu[VECTOR_EXIT] &= ~BIT32(qloop); } @@ -537,12 +635,14 @@ p9_sgpe_stop_exit() // reset clevel to 0 if core is going to wake up G_sgpe_stop_record.level[qloop][cloop] = 0; - // Change PPM Wakeup to CME + + PK_TRACE_INF("SX0.B: Switch Core[%d]PPM Wakeup back to CME via CPMMR[13]", + ((qloop << 2) + cloop)); GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CPMMR_CLR, ((qloop << 2) + cloop)), BIT64(13)); } - // Update QSSR: drop stop_exit_ongoing + PK_TRACE("Update QSSR: drop stop_exit_ongoing"); out32(OCB_QSSR_CLR, BIT32(qloop + 26)); } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c index 721c7544..1bcf8f55 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c @@ -26,7 +26,35 @@ #include "p9_sgpe_stop.h" #include "p9_sgpe_stop_enter_marks.h" -SgpeStopRecord G_sgpe_stop_record; +SgpeStopRecord G_sgpe_stop_record = +{ + // core levels + { {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0} + }, + // quad states + { {0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0} + }, + // group vectors + { {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0} + }, + // semaphores + {{0, 0}} +}; // PCB Interrupt Type2 // Payload @@ -68,7 +96,7 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) MARK_TRAP(STOP_PIG_HANDLER) //========================= - PK_TRACE("PIG-IRQ: %d", irq); + PK_TRACE_INF("PIG-IRQ: %d", irq); // Disable type2/3/6 interrupt out32(OCB_OIMR1_OR, (BITS32(15, 2) | BIT32(19))); // Read type2/3/6 interrupt status @@ -83,21 +111,21 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) { cpending_t2 = in32(OCB_OPITNPRA(2)); out32(OCB_OPITNPRA_CLR(2), cpending_t2); - PK_TRACE("Type2: %x", cpending_t2); + PK_TRACE_INF("Type2: %x", cpending_t2); } if (cirq & BIT32(16)) { cpending_t3 = in32(OCB_OPITNPRA(3)); out32(OCB_OPITNPRA_CLR(3), cpending_t3); - PK_TRACE("Type3: %x", cpending_t3); + PK_TRACE_INF("Type3: %x", cpending_t3); } if (qirq) { qpending_t6 = in32(OCB_OPIT6PRB); out32(OCB_OPIT6PRB_CLR, qpending_t6); - PK_TRACE("Type6: %x", qpending_t6); + PK_TRACE_INF("Type6: %x", qpending_t6); } // clear group before analyzing input @@ -121,15 +149,15 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) // read payload on quad has interrupt pending payload = in32(OCB_OPIT6QN(qloop)); - PK_TRACE("q[%d] payload [%x]", qloop, payload); + PK_TRACE_INF("Q[%d] Payload [%x]", qloop, payload); if (payload & TYPE6_PAYLOAD_EXIT_EVENT) { - PK_TRACE("q[%d] request special wakeup", qloop); + PK_TRACE_INF("Q[%d] Request Special Wakeup", qloop); if (G_sgpe_stop_record.group.qswu[VECTOR_CONFIG] & BIT32(qloop)) { - PK_TRACE("q[%d] already in special wakeup", qloop); + PK_TRACE_INF("Q[%d] Already in Special Wakeup", qloop); } else { @@ -143,8 +171,9 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) } else { - PK_TRACE("q[%d] drop special wakeup, clearing done", qloop); + PK_TRACE_INF("Q[%d] Drop Special Wakeup, Clearing Done", qloop); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_GPMMR_CLR, qloop), BIT64(0)); + G_sgpe_stop_record.group.qswu[VECTOR_ENTRY] |= BIT32(qloop); G_sgpe_stop_record.group.qswu[VECTOR_CONFIG] &= ~BIT32(qloop); } @@ -157,12 +186,12 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) continue; } - PK_TRACE("q[%d] has core request:", qloop); - PK_TRACE("now clv[%d][%d][%d][%d]", - G_sgpe_stop_record.level[qloop][0], - G_sgpe_stop_record.level[qloop][1], - G_sgpe_stop_record.level[qloop][2], - G_sgpe_stop_record.level[qloop][3]); + PK_TRACE_INF("Q[%d] Has Core Request:", qloop); + PK_TRACE_INF("Now clv[%d][%d][%d][%d]", + G_sgpe_stop_record.level[qloop][0], + G_sgpe_stop_record.level[qloop][1], + G_sgpe_stop_record.level[qloop][2], + G_sgpe_stop_record.level[qloop][3]); // then loop all cores in the quad for(cloop = 0; cloop < CORES_PER_QUAD; cloop++) @@ -182,12 +211,12 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) payload = in32(OCB_OPIT3CN(((qloop << 2) + cloop))); } - PK_TRACE("c[%d] payload [%x]", cloop, payload); + PK_TRACE_INF("C[%d] Payload [%x]", cloop, payload); // check if exit request if (payload & TYPE2_PAYLOAD_EXIT_EVENT) { - PK_TRACE("c[%d] request exit", cloop); + PK_TRACE_INF("C[%d] Request Exit", cloop); // Due to some wakeup signal sources can be "fake" // as they are triggered regardless of the state of the core, @@ -199,21 +228,21 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) if (scom_data & BIT64(18)) { - PK_TRACE("c[%d] confirmed stopped", cloop); + PK_TRACE_INF("C[%d] Considered Stopped, Will Wakeup", cloop); if (cloop < CORES_PER_EX) { G_sgpe_stop_record.group.ex_l[VECTOR_EXIT] |= BIT32(qloop); G_sgpe_stop_record.group.ex_b[VECTOR_EXIT] |= - BIT32(qloop << 1); + BIT32((qloop << 1)); } else { G_sgpe_stop_record.group.ex_r[VECTOR_EXIT] |= BIT32(qloop); G_sgpe_stop_record.group.ex_b[VECTOR_EXIT] |= - BIT32((qloop << 1) + 1); + BIT32(((qloop << 1) + 1)); } G_sgpe_stop_record.group.quad[VECTOR_EXIT] |= @@ -221,12 +250,16 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) G_sgpe_stop_record.group.core[VECTOR_EXIT] |= BIT32(((qloop << 2) + cloop)); } + else + { + PK_TRACE_INF("C[%d] is Considered Running, Ignore Wakeup", cloop); + } } // otherwise it is entry request with stop level in payload else { - PK_TRACE("c[%d] request enter to lv[%d]", cloop, - (payload & TYPE2_PAYLOAD_STOP_LEVEL)); + PK_TRACE_INF("C[%d] Request Enter to lv[%d]", cloop, + (payload & TYPE2_PAYLOAD_STOP_LEVEL)); // read stop level on core asking to enter G_sgpe_stop_record.level[qloop][cloop] = @@ -236,11 +269,11 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) } } - PK_TRACE("new clv[%d][%d][%d][%d]", - G_sgpe_stop_record.level[qloop][0], - G_sgpe_stop_record.level[qloop][1], - G_sgpe_stop_record.level[qloop][2], - G_sgpe_stop_record.level[qloop][3]); + PK_TRACE_INF("New clv[%d][%d][%d][%d]", + G_sgpe_stop_record.level[qloop][0], + G_sgpe_stop_record.level[qloop][1], + G_sgpe_stop_record.level[qloop][2], + G_sgpe_stop_record.level[qloop][3]); } G_sgpe_stop_record.group.ex_b[VECTOR_EXIT] &= @@ -250,19 +283,19 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) G_sgpe_stop_record.group.ex_r[VECTOR_EXIT] &= G_sgpe_stop_record.group.ex_r[VECTOR_CONFIG]; - PK_TRACE("Quad Special Wakeup: Raise[%x], Drop[%x]", - G_sgpe_stop_record.group.qswu[VECTOR_EXIT], - G_sgpe_stop_record.group.qswu[VECTOR_ENTRY]); - PK_TRACE("Core Request Stop: Entry[%x], Exit[%x]", - G_sgpe_stop_record.group.core[VECTOR_ENTRY], - G_sgpe_stop_record.group.core[VECTOR_EXIT]); + PK_TRACE_INF("Quad Special Wakeup: Raise[%x], Drop[%x]", + G_sgpe_stop_record.group.qswu[VECTOR_EXIT], + G_sgpe_stop_record.group.qswu[VECTOR_ENTRY]); + PK_TRACE_INF("Core Request Stop: Entry[%x], Exit[%x]", + G_sgpe_stop_record.group.core[VECTOR_ENTRY], + G_sgpe_stop_record.group.core[VECTOR_EXIT]); if ((!G_sgpe_stop_record.group.core[VECTOR_EXIT]) && (!G_sgpe_stop_record.group.core[VECTOR_ENTRY]) && (!G_sgpe_stop_record.group.qswu[VECTOR_EXIT]) && (!G_sgpe_stop_record.group.qswu[VECTOR_ENTRY])) { - PK_TRACE("Nothing to do, clear masks"); + PK_TRACE_INF("Nothing to do, Clear Masks"); out32(OCB_OIMR1_CLR, (BITS32(15, 2) | BIT32(19))); } else @@ -270,17 +303,17 @@ p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) if (G_sgpe_stop_record.group.core[VECTOR_EXIT] || G_sgpe_stop_record.group.qswu[VECTOR_EXIT]) { - PK_TRACE("unblock exit"); + PK_TRACE_INF("Unblock Exit"); pk_semaphore_post(&(G_sgpe_stop_record.sem[1])); } if (G_sgpe_stop_record.group.core[VECTOR_ENTRY] || G_sgpe_stop_record.group.qswu[VECTOR_ENTRY]) { - PK_TRACE("unblock entry"); + PK_TRACE_INF("Unblock Entry"); pk_semaphore_post(&(G_sgpe_stop_record.sem[0])); } - PK_TRACE("RFI"); + PK_TRACE_INF("RFI"); } } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h index 4064e663..287c4bb1 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h @@ -34,14 +34,7 @@ /// \brief Application specific overrides go here. /// -// @todo RTC 161182 -#define HW386311_PBIE_RW_PTR_STOP11_FIX 1 -#define BROADSIDE_SCAN0 0 -#define FUSED_CORE_MODE_SCAN_FIX 0 - -#define SIMICS_TUNING 0 -#define USE_SIMICS_IO 0 -#define DEV_DEBUG 1 +// -------------------- #ifndef EPM_P9_TUNING #define EPM_P9_TUNING 0 @@ -50,28 +43,58 @@ #define STOP_PRIME 0 #define SKIP_L3_PURGE 0 #define SKIP_L3_PURGE_ABORT 0 -#define ISTEP15_HACK 0 +#define SKIP_ARRAYINIT 0 +#define SKIP_SCAN0 0 +#define SKIP_INITF 0 #if EPM_P9_TUNING + // @todo RTC 161182 + #define HW386311_DD1_PBIE_RW_PTR_STOP11_FIX 0 + #define HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX 0 + #define FUSED_CORE_MODE_SCAN_FIX 0 + #define SKIP_CME_BOOT_STOP11 1 #define SKIP_CME_BOOT_IPL_HB 1 - #define SKIP_ARRAYINIT 0 - #define SKIP_SCAN0 0 + #define EPM_BROADSIDE_SCAN0 0 #else + #define HW386311_DD1_PBIE_RW_PTR_STOP11_FIX 1 + #define HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX 1 + #define FUSED_CORE_MODE_SCAN_FIX 0 + #define SKIP_CME_BOOT_STOP11 0 #define SKIP_CME_BOOT_IPL_HB 1 - #define SKIP_ARRAYINIT 0 - #define SKIP_SCAN0 0 + #define EPM_BROADSIDE_SCAN0 0 #endif -#define SKIP_INITF 0 // -------------------- +#define PK_TRACE_LEVEL 2 + +#if PK_TRACE_LEVEL == 0 /*No TRACEs*/ + #define PK_TRACE_ENABLE 0 + #define PK_KERNEL_TRACE_ENABLE 0 +#elif PK_TRACE_LEVEL == 1 /*only PK_TRACE_INF*/ + #define PK_TRACE_ENABLE 1 + #define PK_TRACE_CRIT_ENABLE 1 + #define PK_TRACE_DBG_SUPPRESS 1 + #define PK_KERNEL_TRACE_ENABLE 0 +#else /*All TRACEs*/ + #define PK_TRACE_ENABLE 1 + #define PK_TRACE_CRIT_ENABLE 1 + #define PK_TRACE_DBG_SUPPRESS 0 + #define PK_KERNEL_TRACE_ENABLE 1 +#endif + #if EPM_P9_TUNING #define PK_TRACE_BUFFER_WRAP_MARKER 1 #endif -#define PK_TRACE_TIMER_OUTPUT 0 -#define PK_TRACE_ENABLE 1 +#define PK_TRACE_TIMER_OUTPUT 0 + +// -------------------- + +#define SIMICS_TUNING 0 +#define USE_SIMICS_IO 0 +#define DEV_DEBUG 1 // -------------------- diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk index 621e1842..61eded4b 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk @@ -50,6 +50,9 @@ TOP-S-SOURCES = p9_sgpe_image_header.S TOP-CPP-SOURCES = p9_sgpe_main.C TOP-CPP-SOURCES += p9_hcd_cache_initf.C +TOP-CPP-SOURCES += p9_hcd_cache_dpll_initf.C +TOP-CPP-SOURCES += p9_hcd_cache_chiplet_l3_dcc_setup.C +TOP-CPP-SOURCES += p9_hcd_cache_dcc_skewadjust_setup.C UTILS_OBJECTS = $(UTILS-SRC:.C=.o) TOP_OBJECTS = $(TOP-C-SOURCES:.c=.o) $(TOP-S-SOURCES:.S=.o) $(TOP-CPP-SOURCES:.C=.o) |
