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| author | Yue Du <daviddu@us.ibm.com> | 2019-06-13 14:36:47 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2019-07-13 14:32:44 -0500 |
| commit | 0f71cc0dd5afb62889bb02c96fbda806f5bc4ce2 (patch) | |
| tree | 851ef8fd122c8cca7a67c74b3f23e77286755a7a /import/chips | |
| parent | ec0d8bb47f67880480b9d340dd251774144ed0c9 (diff) | |
| download | talos-hcode-0f71cc0dd5afb62889bb02c96fbda806f5bc4ce2.tar.gz talos-hcode-0f71cc0dd5afb62889bb02c96fbda806f5bc4ce2.zip | |
Axone: Fix PPE PVR expectation checks and SMF build flag
Change-Id: Ib3734137c6e16d4d8cbe579492df56ec9149146e
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78920
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com>
Dev-Ready: YUE DU <daviddu@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips')
4 files changed, 7 insertions, 7 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c index be6e5eda..5f420caf 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2018 */ +/* COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -170,7 +170,7 @@ main(int argc, char** argv) #elif (CUMULUS_DD_LEVEL != 0) #define PVR_CONST (0x42090800 | (((CUMULUS_DD_LEVEL ) / 10) << 8) | (CUMULUS_DD_LEVEL % 10)) #elif (AXONE_DD_LEVEL != 0) -#define PVR_CONST (0x42091000 | (((AXONE_DD_LEVEL ) / 10) << 8) | (AXONE_DD_LEVEL % 10)) +#define PVR_CONST (0x42090000 | (((AXONE_DD_LEVEL ) / 10) << 8) | (AXONE_DD_LEVEL % 10)) #else #define PVR_CONST 0 #endif diff --git a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h index f11d4639..5a953734 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h +++ b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h @@ -58,7 +58,7 @@ #define DISABLE_CME_DUAL_CAST 0 // NDD22 Secure Memory Support: RAM URMOR -#if NIMBUS_DD_LEVEL >= 22 || CUMULUS_DD_LEVEL >= 13 +#if NIMBUS_DD_LEVEL >= 22 || CUMULUS_DD_LEVEL >= 13 || AXONE_DD_LEVEL >= 10 #define SMF_SUPPORT_ENABLE 1 diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c index 8488b442..271c25fc 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2018 */ +/* COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -214,7 +214,7 @@ main(int argc, char** argv) #elif (CUMULUS_DD_LEVEL != 0) #define PVR_CONST (0x42090800 | (((CUMULUS_DD_LEVEL ) / 10) << 8) | (CUMULUS_DD_LEVEL % 10)) #elif (AXONE_DD_LEVEL != 0) -#define PVR_CONST (0x42091000 | (((AXONE_DD_LEVEL ) / 10) << 8) | (AXONE_DD_LEVEL % 10)) +#define PVR_CONST (0x42090000 | (((AXONE_DD_LEVEL ) / 10) << 8) | (AXONE_DD_LEVEL % 10)) #else #define PVR_CONST 0 #endif diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C index dce81d17..45c7e7d4 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2018 */ +/* COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -184,7 +184,7 @@ main(int argc, char** argv) #elif (CUMULUS_DD_LEVEL != 0) #define PVR_CONST (0x42090800 | (((CUMULUS_DD_LEVEL ) / 10) << 8) | (CUMULUS_DD_LEVEL % 10)) #elif (AXONE_DD_LEVEL != 0) -#define PVR_CONST (0x42091000 | (((AXONE_DD_LEVEL ) / 10) << 8) | (AXONE_DD_LEVEL % 10)) +#define PVR_CONST (0x42090000 | (((AXONE_DD_LEVEL ) / 10) << 8) | (AXONE_DD_LEVEL % 10)) #else #define PVR_CONST 0 #endif |
