STOP: Enable CHTM

CHTM traces use Homer CpmrBase + 0x80000 + 16KB*cme_id
When enabled, the CHTM traces are hard coded to
0x20000000 + 16MB*EX

Change-Id: I80256273a0b7fc31c2f8b5119108ca34e1599106
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38437
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

7 files changed, 149 insertions, 25 deletions

diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
index 66922333..27159965 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
+++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
@@ -204,9 +204,10 @@ HCD_CONST(SGPE_QUAD_SPECIFIC_RING_SRAM_OFF_BYTE, 0x30)
 HCD_CONST(SGPE_QUAD_SCOM_RESTORE_SRAM_OFF_BYTE, 0x34)
 HCD_CONST(SGPE_QUAD_SCOM_RESTORE_MEM_OFF_BYTE,  0x38)
 HCD_CONST(SGPE_QUAD_SCOM_RESTORE_LENGTH_BYTE,   0x3C)
-HCD_CONST(SGPE_AUX_DATA_OFFSET_BYTE,       0x40)
-HCD_CONST(SGPE_AUX_DATA_LENGTH_BYTE,       0x44)
-HCD_CONST(PGPE_AUX_CTRL_BYTE,              0x48)
+HCD_CONST(SGPE_AUX_DATA_OFFSET_BYTE,            0x40)
+HCD_CONST(SGPE_AUX_DATA_LENGTH_BYTE,            0x44)
+HCD_CONST(SGPE_AUX_CTRL_BYTE,                   0x48)
+HCD_CONST(SGPE_CHTM_MEM_CFG_BYTE,               0x50)
 
 HCD_CONST(SGPE_RESET_ADDR_IMAGE_OFFSET,         (SGPE_HEADER_IMAGE_OFFSET + SGPE_SYSTEM_RESET_ADDR_BYTE))
 HCD_CONST(SGPE_BUILD_DATE_IMAGE_OFFSET,         (SGPE_HEADER_IMAGE_OFFSET + SGPE_BUILD_DATE_BYTE))
@@ -216,7 +217,8 @@ HCD_CONST(SGPE_STOP_4_TO_2_BIT_POS,             0x80000000)
 HCD_CONST(SGPE_STOP_5_TO_4_BIT_POS,             0x40000000)
 HCD_CONST(SGPE_STOP_8_TO_5_BIT_POS,             0x20000000)
 HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS,            0x10000000)
-HCD_CONST(SGPE_CME_INSTRUCTION_TRACE_BIT_POS,   0x08000000)
+HCD_CONST(SGPE_ENABLE_CME_TRACE_ARRAY_BIT_POS,  0x08000000)
+HCD_CONST(SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS,   0x04000000)
 HCD_CONST(SGPE_PROC_FAB_ADDR_BAR_MODE_POS,      0x00008000)
 
 ///24x7
@@ -358,7 +360,7 @@ HCD_CONST(CME_STOP_4_TO_2_BIT_POS,              0x40000000)
 HCD_CONST(CME_STOP_5_TO_4_BIT_POS,              0x20000000)
 HCD_CONST(CME_STOP_8_TO_5_BIT_POS,              0x10000000)
 HCD_CONST(CME_STOP_11_TO_8_BIT_POS,             0x08000000)
-HCD_CONST(CME_QUEUED_SCAN_DISABLE,              0x00000002)
+HCD_CONST(CME_QUEUED_SCAN_DISABLE_BIT_POS,      0x00000002)
 HCD_CONST(CME_SKIP_CORE_POWEROFF_BIT_POS,       0x00000001)
 
 /// CME Hcode
@@ -385,6 +387,16 @@ HCD_CONST(CME_QUAD_PSTATE_SIZE,                 HALF_KB)
 
 HCD_CONST(CME_REGION_SIZE,                      (64 * ONE_KB))
 
+// Debug
+
+HCD_CONST(CPMR_TRACE_REGION_OFFSET,             (512 * ONE_KB))
+HCD_CONST(CME_TRACE_REGION_SIZE,                (16 * ONE_KB))
+HCD_CONST(CPMR_TRACE_REGION_SIZE,               (CME_TRACE_REGION_SIZE* MAX_CMES_PER_CHIP)) // 192K
+HCD_CONST(CPMR_DEBUG_REGION_OFFSET,             CPMR_TRACE_REGION_OFFSET + CPMR_TRACE_REGION_SIZE)
+HCD_CONST(CPMR_DEBUG_REGION_SIZE,               (64 * ONE_KB)) // 192K + 64K = 256K
+
+
+
 //---------------------------------------------------------------------------------------
 
 /// PPMR Header
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H
index 2e6062f3..1a1a2953 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H
+++ b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H
@@ -66,6 +66,9 @@ HCD_CONST(HOMER_AUX_BASE_ADDR, (HOMER_QPMR_BASE_ADDR + QPMR_AUX_OFFSET))
 
 HCD_CONST(HOMER_CPMR_BASE_ADDR,            (HOMER_BASE_ADDR + (CPMR_HOMER_OFFSET)))
 HCD_CONST(HOMER_CPMR_HEADER_ADDR,          HOMER_CPMR_BASE_ADDR)
+HCD_CONST(HOMER_CPMR_TRACE_ADDR,           (HOMER_CPMR_BASE_ADDR + CPMR_TRACE_REGION_OFFSET))
+HCD_CONST(HOMER_CPMR_DEBUG_ADDR,           (HOMER_CPMR_BASE_ADDR + CPMR_DEBUG_REGION_OFFSET))
+
 
 
 /// PPMR
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
index 69529f76..9b107915 100644
--- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
+++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
@@ -235,6 +235,7 @@ HCD_HDR_UINT32(g_sgpe_aux_offset, 0);
 HCD_HDR_UINT32(g_sgpe_aux_length, 0);
 HCD_HDR_UINT32(g_sgpe_aux_control, 0);
 HCD_HDR_UINT32(g_sgpe_reserve4, 0);
+HCD_HDR_UINT64(g_sgpe_chtm_mem_cfg, 0);
 HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE);
 #ifdef __ASSEMBLER__
 .endm
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
index ed2c535d..1f8eea82 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
@@ -546,7 +546,7 @@ p9_cme_stop_exit()
     PK_TRACE_DBG("Check: core[%d] target_lv[%d], deeper_lv[%d], deeper_c[%d]",
                  core, target_level, deeper_level, deeper_core);
 
-    PK_TRACE("Clear chtm purge done via ESIR[24/25]");
+    PK_TRACE("Clear chtm purge done via EISR[24/25]");
     out32(CME_LCL_EISR_CLR, (core << SHIFT32(25)));
 
     PK_TRACE("Update STOP history: in transition of exit");
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
index b06bc27f..0392559b 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
@@ -64,6 +64,7 @@ extern "C" {
 #define RESTORE_RING_BITS(mask, ring, save) ring = (((ring) & (~mask)) | (save));
 #endif
 
+
 #define DEBUG_TRACE_CONTROL         0x100107D0
 #define L3TRA_TRACE_TRCTRL_CONFIG   0x10010402
 #define L3TRA_TRACE_TRDATA_CONFIG_0 0x10010403
@@ -139,6 +140,19 @@ extern "C" {
 #define EX_PM_LCO_DIS_REG        0x10011816
 #define EX_PM_L2_RCMD_DIS_REG    0x10011818
 
+#define EX_CHTM0_MODE_REG        0x10012200
+#define EX_CHTM1_MODE_REG        0x10012300
+#define EX_CHTM0_MEM_REG         0x10012201
+#define EX_CHTM1_MEM_REG         0x10012301
+#define EX_CHTM0_STAT_REG        0x10012202
+#define EX_CHTM1_STAT_REG        0x10012302
+#define EX_CHTM0_LAST_REG        0x10012203
+#define EX_CHTM1_LAST_REG        0x10012303
+#define EX_CHTM0_TRIG_REG        0x10012204
+#define EX_CHTM1_TRIG_REG        0x10012304
+#define EX_CHTM0_CTRL_REG        0x10012205
+#define EX_CHTM1_CTRL_REG        0x10012305
+
 #define PERV_CPLT_CTRL0_OR       0x10000010
 #define PERV_CPLT_CTRL0_CLEAR    0x10000020
 #define PERV_CPLT_CTRL1_OR       0x10000011
@@ -205,6 +219,7 @@ enum SGPE_STOP_EVENT_LEVELS
 enum SGPE_STOP_CME_FLAGS
 {
     CME_TRACE_ENABLE                  = BIT32(4),
+    CME_CHTM_ENABLE                   = BIT32(4),
     CME_EX1_INDICATOR                 = BIT32(26),
     CME_SIBLING_FUNCTIONAL            = BIT32(27),
     CME_CORE0_ENTRY_FIRST             = BIT32(28),
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
index 56444e6d..3ed71e8d 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
@@ -51,6 +51,7 @@ p9_sgpe_stop_entry()
     int          l3_purge_aborted = 0;
     uint32_t     ex               = 0;
     uint32_t     ex_mask          = 0;
+    uint32_t     ex_index         = 0;
     uint32_t     bitloc           = 0;
     uint32_t     qloop            = 0;
     uint32_t     cloop            = 0;
@@ -574,26 +575,33 @@ p9_sgpe_stop_entry()
 
 #if !SKIP_L3_PURGE
 
-        PK_TRACE("Assert purge L3 via EX_PM_PURGE_REG[0]");
-
-        if(ex & FST_EX_IN_QUAD)
+        for (ex_mask = 2; ex_mask; ex_mask--)
         {
-            GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 0), BIT64(0));
-        }
+            if (ex & ex_mask)
+            {
+                ex_index = ex_mask & 1;
 
-        if(ex & SND_EX_IN_QUAD)
-        {
-            GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 1), BIT64(0));
-        }
+                PK_TRACE("Assert purge L3 on EX[%d] via EX_PM_PURGE_REG[0]", ex_index);
+                GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, ex_index), BIT64(0));
 
-        // disable cme trace array
-        sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(OCC_SRAM_SGPE_HEADER_ADDR);
+                PK_TRACE("Halt CHTM[0+1] on EX[%d] via HTM_TRIG[1]", ex_index);
+                GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_CHTM0_TRIG_REG, qloop, ex_index), BIT64(1));
+                GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_CHTM1_TRIG_REG, qloop, ex_index), BIT64(1));
 
-        if (pSgpeImgHdr->g_sgpe_reserve_flags & BIT32(4))
-        {
-            GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(DEBUG_TRACE_CONTROL, qloop), BIT64(1));
+                // Disable PMISC and IMA - Bits 1,2,4
+                GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_CHTM0_CTRL_REG, qloop, ex_index), 0);
+                GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_CHTM1_CTRL_REG, qloop, ex_index), 0);
+
+                // Disable Tracing
+                GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_CHTM0_MODE_REG, qloop, ex_index), 0);
+                GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_CHTM1_MODE_REG, qloop, ex_index), 0);
+
+            }
         }
 
+        PK_TRACE("Disable cme trace array via DEBUG_TRACE_CONTROL[1]");
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(DEBUG_TRACE_CONTROL, qloop), BIT64(1));
+
         PK_TRACE("Poll for L3 purge done via EX_PM_PURGE_REG[0]");
 
         // Poll on the same request bit thus no need to deassert
@@ -807,7 +815,8 @@ p9_sgpe_stop_entry()
             GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, qloop, 1), scom_data.value);
         }
 
-        PK_TRACE("Check NCU_SATUS_REG[0:3] for all zeros");
+        PK_TRACE("Check NCU_STATUS_REG[0:3] for all zeros");
+        // HW407207 - can only check bit 0:2
 
         if (ex & FST_EX_IN_QUAD)
         {
@@ -815,8 +824,9 @@ p9_sgpe_stop_entry()
             {
                 GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_NCU_STATUS_REG, qloop, 0),
                             scom_data.value);
+                PKTRACE("Polling NCU_STATUS_REG 0");
             }
-            while(((~(scom_data.words.upper)) & BITS32(0, 4)) != BITS32(0, 4));
+            while(((~(scom_data.words.upper)) & BITS32(0, 3)) != BITS32(0, 3));
         }
 
         if (ex & SND_EX_IN_QUAD)
@@ -825,8 +835,9 @@ p9_sgpe_stop_entry()
             {
                 GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_NCU_STATUS_REG, qloop, 1),
                             scom_data.value);
+                PKTRACE("Polling NCU_STATUS_REG 1");
             }
-            while(((~(scom_data.words.upper)) & BITS32(0, 4)) != BITS32(0, 4));
+            while(((~(scom_data.words.upper)) & BITS32(0, 3)) != BITS32(0, 3));
         }
 
         PK_TRACE_DBG("NCU Status Clean");
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
index 29aa14c5..131ca7c5 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
@@ -303,6 +303,8 @@ p9_sgpe_stop_exit()
     uint32_t     ec_mask         = 0;
     uint32_t     ex_index        = 0;
     uint32_t     ec_index        = 0;
+    uint32_t     chtm_mask       = 0;
+    uint64_t     chtm_size       = 0;
     data64_t     scom_data       = {0};
 #if !STOP_PRIME
     ocb_ccsr_t   ccsr            = {0};
@@ -910,9 +912,12 @@ p9_sgpe_stop_exit()
             // 7: LCL_EN_WAIT_CYCLES
             // 8: LCL_EN_FULL_SPEED
             // inst: 3D20C000 | addis r9, 0, 0xC000 | R9 = 0xC0000000
-            // inst: 3C208F80 | addis r1, 0, 0x8F80 | R1 = 0x88800000
+            // inst: 3C208F80 | addis r1, 0, 0x8F80 | R1 = 0x8F800000
+            // HTM mode, if enabled, forces only 64 bits of data
+            // inst: 38210300 | addi  r1, r1, 0x300 | R1 = 0x8F800300
             // inst: 90290120 | stw   r1, 0x120(r9) | 0xC0000120 = R1
             //
+            // This configures L3 Trace array to receive CME data
             // 1. The trace array has to be stopped to configure it
             // 2. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRCTRL_CONFIG
             //    bit0: store_trig_mode_lt = 1
@@ -940,7 +945,7 @@ p9_sgpe_stop_exit()
 
             sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(OCC_SRAM_SGPE_HEADER_ADDR);
 
-            if (pSgpeImgHdr->g_sgpe_reserve_flags & CME_TRACE_ENABLE)
+            if (pSgpeImgHdr->g_sgpe_reserve_flags & SGPE_ENABLE_CME_TRACE_ARRAY_BIT_POS)
             {
                 // Stop the trace to configure it
                 GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(DEBUG_TRACE_CONTROL, qloop), BIT64(1));
@@ -949,11 +954,23 @@ p9_sgpe_stop_exit()
                 {
                     if (m_pg & ex_mask)
                     {
+                        ex_index = ex_mask & 1;
+
+                        PK_TRACE("Configure and Enable L3[%d] Trace Array to receive CME data",
+                                 ex_index);
 
                         GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, ex_index),
                                     0x3D20C00000000000);
                         GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, ex_index),
                                     0x3C20888000000000);
+
+                        if (pSgpeImgHdr->g_sgpe_reserve_flags & SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS)
+                        {
+                            PK_TRACE("Puttng PPE in 64 bit data mode before enable CHTM");
+                            GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_XIRAMEDR, qloop, 0),
+                                        0x3821030000000000);
+                        }
+
                         GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, ex_index),
                                     0x9029012000000000);
 
@@ -982,6 +999,71 @@ p9_sgpe_stop_exit()
                 GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(DEBUG_TRACE_CONTROL, qloop), BIT64(0));
             }
 
+            // Enable CHTM
+            //
+            // This configures CHTM to receive CME data
+            // Set up HTM_MODE: [0] = start, [1:2] = 0b10 PPE Trace
+            // Set up HTM_CTRL
+            // Clear memory allocated in HTM_MEM
+            // Allocate memory in HTM_MEM
+            //   allow the user to have full control over size and starting address
+            // Reset triggers
+            // Start triggers
+
+            if (pSgpeImgHdr->g_sgpe_reserve_flags & SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS)
+            {
+                for (ex_mask = 2; ex_mask; ex_mask--)
+                {
+                    if (m_pg & ex_mask)
+                    {
+                        ex_index = ex_mask & 1;
+
+                        PK_TRACE("Configure and Enable EX[%d] CHTM to receive CME data",
+                                 ex_index);
+
+                        chtm_mask = (uint32_t)pSgpeImgHdr->g_sgpe_chtm_mem_cfg;
+                        chtm_mask = chtm_mask & BITS64SH(40, 9) >> SHIFT64SH(48);
+
+                        //bit[5] size_small = 1, mask base[31:39,9] with size[40:48,9]
+                        if (pSgpeImgHdr->g_sgpe_chtm_mem_cfg & BIT64(5))
+                        {
+                            chtm_size = BIT64(39); // Base of 16M;
+                        }
+                        //bit[5] size_small = 0, mask base[26:34,9] with size[40:48,9]
+                        else
+                        {
+                            chtm_size = BIT64(34); // Base of 512M
+                        }
+
+                        // Note: it isn't 100% because it only uses the # of bits in the mask,
+                        //       but it isn't valid to configure the mask other ways
+                        while (chtm_mask != 0)
+                        {
+                            chtm_size = chtm_size << 1;
+                            chtm_mask = chtm_mask >> 1;
+                        }
+
+                        scom_data.value = BIT64(0) +
+                                          pSgpeImgHdr->g_sgpe_chtm_mem_cfg +
+                                          chtm_size * ((qloop << 1) + ex_index);
+
+                        // CME Trace is routed through CHTM1
+                        GPE_PUTSCOM(GPE_SCOM_ADDR_EX((EX_CHTM1_MODE_REG),
+                                                     qloop, ex_index), 0xC00F000000000000);
+                        GPE_PUTSCOM(GPE_SCOM_ADDR_EX((EX_CHTM1_CTRL_REG),
+                                                     qloop, ex_index), 0x7404000000000000);
+                        GPE_PUTSCOM(GPE_SCOM_ADDR_EX((EX_CHTM1_MEM_REG),
+                                                     qloop, ex_index), 0);
+                        GPE_PUTSCOM(GPE_SCOM_ADDR_EX((EX_CHTM1_MEM_REG),
+                                                     qloop, ex_index), scom_data.value);
+                        GPE_PUTSCOM(GPE_SCOM_ADDR_EX((EX_CHTM1_TRIG_REG),
+                                                     qloop, ex_index), BIT64(4));
+                        GPE_PUTSCOM(GPE_SCOM_ADDR_EX((EX_CHTM1_TRIG_REG),
+                                                     qloop, ex_index), BIT64(0));
+                    }
+                }
+            }
+
             if (in32(OCB_OCCS2) & BIT32(CME_DEBUG_TRAP_ENABLE))
             {
                 PK_TRACE_INF("BREAK: Trap Before CME Boot");