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| author | Yue Du <daviddu@us.ibm.com> | 2016-11-17 00:32:33 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 16:53:49 -0500 |
| commit | d92c32ce5cc6e6b3eb7bf03935794bcc0d0dedd4 (patch) | |
| tree | 5c305e97582c95b48e05647f35c56c1e53660f73 /import/chips/p9 | |
| parent | 74a33c16f67c734477594c9d9d6ac40b493ca019 (diff) | |
| download | talos-hcode-d92c32ce5cc6e6b3eb7bf03935794bcc0d0dedd4.tar.gz talos-hcode-d92c32ce5cc6e6b3eb7bf03935794bcc0d0dedd4.zip | |
STOP: enable cme trace array before cme boot in SGPE
Change-Id: If54189d3fcb17cb3b59019c62eb389ef01fc58cb
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32749
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: ADAM S. HALE <ashale@us.ibm.com>
Dev-Ready: ADAM S. HALE <ashale@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9')
4 files changed, 96 insertions, 3 deletions
diff --git a/import/chips/p9/common/pmlib/include/p9_stop_common.h b/import/chips/p9/common/pmlib/include/p9_stop_common.h index 27a76bce..c87eea9d 100644 --- a/import/chips/p9/common/pmlib/include/p9_stop_common.h +++ b/import/chips/p9/common/pmlib/include/p9_stop_common.h @@ -118,6 +118,9 @@ enum P9_STOP_HISTORY_CTRL_STATUS /// Homer Layout enum P9_HOMER_REGION_CONSTANTS { + OCC_SRAM_BASE = 0xFFF00000, + SGPE_IMAGE_SRAM_BASE = 0xFFF2C000, + SGPE_HEADER_IMAGE_OFFSET = 0x180, CME_SRAM_BASE = 0xFFFF8000, // CPMR_BASE (HOMER_BASE + 2MB) CPMR_BASE_HOMER_OFFSET = 0x200000, diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 5efacc75..61e883ad 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -176,7 +176,8 @@ HCD_HDR_UINT32(g_sgpe_ivpr_address, 0); HCD_HDR_UINT32(g_sgpe_reserve2, 0); HCD_HDR_UINT32(g_sgpe_build_date, 0); HCD_HDR_UINT32(g_sgpe_build_ver, 0); -HCD_HDR_UINT64(g_sgpe_reserve_flags, 0); +HCD_HDR_UINT32(g_sgpe_reserve_flags, 0); +HCD_HDR_UINT32(g_sgpe_reserve3, 0); HCD_HDR_UINT32(g_sgpe_cmn_ring_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_cmn_ring_ovrd_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_spec_ring_occ_offset, 0); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h index 50bb06a0..3d014d48 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h @@ -59,6 +59,14 @@ extern "C" { #define RESTORE_RING_BITS(mask, ring, save) ring = (((ring) & (~mask)) | (save)); #endif +#define DEBUG_TRACE_CONTROL 0x100107D0 +#define L3TRA_TRACE_TRCTRL_CONFIG 0x10010402 +#define L3TRA_TRACE_TRDATA_CONFIG_0 0x10010403 +#define L3TRA_TRACE_TRDATA_CONFIG_1 0x10010404 +#define L3TRA_TRACE_TRDATA_CONFIG_4 0x10010407 +#define L3TRA_TRACE_TRDATA_CONFIG_5 0x10010408 +#define L3TRA_TRACE_TRDATA_CONFIG_9 0x10010409 + #define EQ_RING_FENCE_MASK_LATCH 0x10010008 #define EQ_SYNC_CONFIG 0x10030000 #define EQ_OPCG_ALIGN 0x10030001 diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c index 687942c6..1ae3d079 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c @@ -27,7 +27,7 @@ #include "p9_sgpe_stop_exit_marks.h" #include "p9_hcd_sgpe_boot_cme.h" #include "p9_dd1_doorbell_wr.h" -#include "p9_stop_util.H" +#include "p9_hcode_image_defines.H" extern SgpeStopRecord G_sgpe_stop_record; @@ -251,7 +251,7 @@ p9_sgpe_stop_exit() // Reading fused core mode flag in cpmr header // To access memory, need to set MSB of homer address - HomerImgDesc_t* pCpmrHdrAddr = (HomerImgDesc_t*)(CPMR_BASE_HOMER_OFFSET | BIT32(0)); + cpmrHeader_t* pCpmrHdrAddr = (cpmrHeader_t*)(CPMR_BASE_HOMER_OFFSET | BIT32(0)); if (pCpmrHdrAddr->fusedModeStatus == 0xBB) { @@ -599,6 +599,87 @@ p9_sgpe_stop_exit() cme_flags); } + // enable cme trace array + sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(SGPE_IMAGE_SRAM_BASE + SGPE_HEADER_IMAGE_OFFSET); + + if (pSgpeImgHdr->g_sgpe_reserve_flags & BIT32(4)) + { + // Trace configuration + // CME_LCL_DBG + // 0: LCL_EN_DBG + // 4: LCL_EN_INTR_ADDR + // 5: LCL_EN_TRACE_EXTRA + // 6: LCL_EN_TRACE_STALL + // 7: LCL_EN_WAIT_CYCLES + // 8: LCL_EN_FULL_SPEED + // inst: 3D20C000 | addis r9, 0, 0xC000 | R9 = 0xC0000000 + // inst: 3C208F80 | addis r1, 0, 0x8F80 | R1 = 0x8F800000 + // inst: 90290120 | stw r1, 0x120(r9) | 0xC0000120 = R1 + + // 1. The trace array has to be stopped to configure it + // 2. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRCTRL_CONFIG + // bit0: store_trig_mode_lt = 1 + // bit 11 enh_trace_mode = 1 + // bit 14:15 = trace_select_lt = 10 for CME0 + // 3. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_0 + // Set trace data compare mask to 0 (0:63) + // 4. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_1 + // Set trace data compare mask to 0 (64:87) + // 5. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_4 + // Clear MSKa, MSKb + // 6. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_5 + // Clear MSKc, MSKd + // 7. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_9 + // bit 0 = disable compression: + // bit 1 = error_bit_compresion_care_mask + // (default is zero so should be enabled) + // 32 msk_err_q <= error_mode_lt(0); + // 33 pat_err_q <= error_mode_lt(1); + // 34 trig0_err_msk <= error_mode_lt(2); + // 35 trig1_err_msk <= error_mode_lt(3); + // match_err <= (msk_err_q or not pat_err_q) + // xor error_stage_lt(0); + // mask = 0 and pattern = 1 and may be trigger 0 + + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(DEBUG_TRACE_CONTROL, qloop), BIT64(1)); + + if (m_pg & FST_EX_IN_QUAD) + { + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, 0), 0x3D20C00000000000); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, 0), 0x3C208F8000000000); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, 0), 0x9029012000000000); + + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(L3TRA_TRACE_TRCTRL_CONFIG, qloop), + (BIT64(0) | BIT64(11) | BIT64(14))); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(L3TRA_TRACE_TRDATA_CONFIG_0, qloop), 0); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(L3TRA_TRACE_TRDATA_CONFIG_1, qloop), 0); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(L3TRA_TRACE_TRDATA_CONFIG_4, qloop), 0); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(L3TRA_TRACE_TRDATA_CONFIG_5, qloop), 0); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(L3TRA_TRACE_TRDATA_CONFIG_9, qloop), + BITS64(33, 2)); + } + + if (m_pg & SND_EX_IN_QUAD) + { + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, 1), 0x3D20C00000000000); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, 1), 0x3C208F8000000000); + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, qloop, 1), 0x9029012000000000); + + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD((L3TRA_TRACE_TRCTRL_CONFIG | 0x80), + qloop), (BIT64(0) | BIT64(11) | BIT64(14))); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD((L3TRA_TRACE_TRDATA_CONFIG_0 | 0x80), + qloop), 0); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD((L3TRA_TRACE_TRDATA_CONFIG_1 | 0x80), + qloop), 0); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD((L3TRA_TRACE_TRDATA_CONFIG_4 | 0x80), + qloop), 0); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD((L3TRA_TRACE_TRDATA_CONFIG_5 | 0x80), + qloop), 0); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD((L3TRA_TRACE_TRDATA_CONFIG_9 | 0x80), + qloop), BITS64(33, 2)); + } + } + if (in32(OCB_OCCS2) & BIT32(CME_DEBUG_TRAP_ENABLE)) { PK_TRACE_INF("BREAK: Trap Before CME Boot"); |
