STOP: Remove sdisn dd1 workaround from dd2, add sync

Change-Id: I1cd4a9ac567e723165cc4f709c23948b38d669aa
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43128
Reviewed-by: JAMES DEZELLE <jdezelle@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: BRIAN D. VICTOR <brian.d.victor1@ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

3 files changed, 27 insertions, 6 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index 20073443..a324436e 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -722,6 +722,8 @@ p9_cme_stop_entry()
             PK_TRACE("Assert core chiplet fence via NET_CTRL0[18]");
             CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(18));
 
+            sync();
+
             PK_TRACE("Clear SCAN_REGION_TYPE prior to stop core clocks");
             CME_PUTSCOM(C_SCAN_REGION_TYPE, core, 0);
 
@@ -781,6 +783,8 @@ p9_cme_stop_entry()
             MARK_TRAP(SE_STOP_CORE_GRID)
             //==============================
 
+            sync();
+
             PK_TRACE("Drop clock sync enable before switch to refclk via CACCR[15]");
             CME_PUTSCOM(CPPM_CACCR_CLR, core, BIT64(15));
 
@@ -800,6 +804,8 @@ p9_cme_stop_entry()
             PK_TRACE("Assert skew sense to skewadjust fence via NET_CTRL0[22]");
             CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(22));
 
+            sync();
+
             PK_TRACE("Drop ABIST_SRAM_MODE_DC to support ABIST Recovery via BIST[1]");
             CME_GETSCOM(C_BIST, core, scom_data.value);
             scom_data.words.upper &= ~BIT32(1);
@@ -811,12 +817,16 @@ p9_cme_stop_entry()
             PK_TRACE("Assert regional fences via CPLT_CTRL1[4-13]");
             CME_PUTSCOM(C_CPLT_CTRL1_OR, core, BITS64(4, 11));
 
-            // Allow queued scoms to complete to Core EPS before switching to Core PPM
-            sync();
+#if NIMBUS_DD_LEVEL == 10
 
             PK_TRACE("Drop sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
             CME_PUTSCOM(C_CPLT_CONF0_CLEAR, core, BIT64(34));
 
+#endif
+
+            // Allow queued scoms to complete to Core EPS before switching to Core PPM
+            sync();
+
             PK_TRACE("Copy PECE CME sample to PPM Shadow via PECES");
 
             if (core & CME_MASK_C0)
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
index 24df2a1a..c11bcb94 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
@@ -75,7 +75,7 @@ p9_cme_stop_pcwu_handler(void* arg, PkIrqId irq)
     // if still wakeup for core with notify_select == cme, go exit
     if (core)
     {
-        out32(CME_LCL_EIMR_OR, BITS32(12, 6) | BITS32(20, 2));
+        out32(CME_LCL_EIMR_OR, BITS32(12, 10));
 #if defined(__IOTA__)
         wrteei(1);
         p9_cme_stop_exit();
@@ -173,7 +173,7 @@ p9_cme_stop_spwu_handler(void* arg, PkIrqId irq)
 
     if (sem_post)
     {
-        out32(CME_LCL_EIMR_OR, BITS32(12, 6) | BITS32(20, 2));
+        out32(CME_LCL_EIMR_OR, BITS32(12, 10));
         PK_TRACE_INF("Launching exit thread");
 #if defined(__IOTA__)
         wrteei(1);
@@ -199,7 +199,7 @@ p9_cme_stop_rgwu_handler(void* arg, PkIrqId irq)
 {
     MARK_TRAP(STOP_RGWU_HANDLER)
     PK_TRACE_INF("RGWU Handler Trigger %d", irq);
-    out32(CME_LCL_EIMR_OR, BITS32(12, 6) | BITS32(20, 2));
+    out32(CME_LCL_EIMR_OR, BITS32(12, 10));
 #if defined(__IOTA__)
     wrteei(1);
     p9_cme_stop_exit();
@@ -219,7 +219,7 @@ p9_cme_stop_enter_handler(void* arg, PkIrqId irq)
 {
     MARK_TRAP(STOP_ENTER_HANDLER)
     PK_TRACE_INF("PM_ACTIVE Handler Trigger %d", irq);
-    out32(CME_LCL_EIMR_OR, BITS32(12, 6) | BITS32(20, 2));
+    out32(CME_LCL_EIMR_OR, BITS32(12, 10));
 #if defined(__IOTA__)
     wrteei(1);
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
index 7f306c49..ed14c782 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
@@ -34,9 +34,13 @@ p9_hcd_core_startclocks(uint32_t core)
     cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_HEADER_ADDR);
     uint32_t     id_vector  = pCmeImgHdr->g_cme_location_id;
 
+#if NIMBUS_DD_LEVEL == 10
+
     PK_TRACE("Assert sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
     CME_PUTSCOM(C_CPLT_CONF0_OR, core, BIT64(34));
 
+#endif
+
     PK_TRACE("Set inop_align/wait/wait_cycles via OPCG_ALIGN[0-3,12-19,52-63]");
 
     // this register requires unicast, dual cast with eq check will fail
@@ -57,6 +61,8 @@ p9_hcd_core_startclocks(uint32_t core)
     PK_TRACE("Drop vital fences via CPLT_CTRL1[3]");
     CME_PUTSCOM(C_CPLT_CTRL1_CLEAR, core, BIT64(3));
 
+    sync();
+
     PK_TRACE("Drop skew sense to skew adjust fence via NET_CTRL0[22]");
     CME_PUTSCOM(CPPM_NC0INDIR_CLR, core, BIT64(22));
 
@@ -73,6 +79,8 @@ p9_hcd_core_startclocks(uint32_t core)
 
     MARK_TRAP(SX_STARTCLOCKS_ALIGN)
 
+    sync();
+
     PK_TRACE("Assert ABIST_SRAM_MODE_DC to support ABIST Recovery via BIST[1]");
     CME_GETSCOM(C_BIST, core, scom_data.value);
     scom_data.words.upper |= BIT32(1);
@@ -153,8 +161,11 @@ p9_hcd_core_startclocks(uint32_t core)
     }
 
     PK_TRACE("Core clock is now running");
+
     MARK_TRAP(SX_STARTCLOCKS_DONE)
 
+    sync();
+
     PK_TRACE("Drop chiplet fence via NC0INDIR[18]");
     CME_PUTSCOM(CPPM_NC0INDIR_CLR, core, BIT64(18));