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| author | Yue Du <daviddu@us.ibm.com> | 2018-09-06 13:46:21 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-10-18 10:39:42 -0500 |
| commit | 933b1b1214c583c5e7fadf08d3d36e27c878bbb0 (patch) | |
| tree | 37a5bf281e490ca36feb99d370dd401a5c95146f /import/chips/p9 | |
| parent | 94a83e1f90a78203b6e27638d074b6411d975bb8 (diff) | |
| download | talos-hcode-933b1b1214c583c5e7fadf08d3d36e27c878bbb0.tar.gz talos-hcode-933b1b1214c583c5e7fadf08d3d36e27c878bbb0.zip | |
STOP: Change cme init to avoid using sisr block wakeup status
Key_Cronus_Test=PM_REGRESS
Change-Id: Id49bfd96af3db195b4b205deb8f3fd9222257c57
CQ: SW444858
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65779
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9')
3 files changed, 3 insertions, 1 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h b/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h index 69e313ee..314889f7 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme.h @@ -55,6 +55,7 @@ extern uint32_t G_CME_LCL_ICCR_OR; extern uint32_t G_CME_LCL_SISR; extern uint32_t G_CME_LCL_SICR_CLR; extern uint32_t G_CME_LCL_SICR_OR; +extern uint32_t G_CME_LCL_SICR; extern uint32_t G_CME_LCL_PSCRS00; extern uint32_t G_CME_LCL_PSCRS10; extern uint32_t G_CME_LCL_PSCRS20; diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c index 8c508e5f..f9632f45 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c @@ -72,6 +72,7 @@ uint32_t G_CME_LCL_ICCR_OR = CME_LCL_ICCR_OR; uint32_t G_CME_LCL_SISR = CME_LCL_SISR; uint32_t G_CME_LCL_SICR_CLR = CME_LCL_SICR_CLR; uint32_t G_CME_LCL_SICR_OR = CME_LCL_SICR_OR; +uint32_t G_CME_LCL_SICR = CME_LCL_SICR; uint32_t G_CME_LCL_PSCRS00 = CME_LCL_PSCRS00; uint32_t G_CME_LCL_PSCRS10 = CME_LCL_PSCRS10; uint32_t G_CME_LCL_PSCRS20 = CME_LCL_PSCRS20; diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c index e714ddf1..ff2be8c0 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_init.c @@ -64,7 +64,7 @@ p9_cme_stop_init() G_cme_stop_record.core_stopgpe = 0; // use SISR[2:3] PM_BLOCK_INTERRUPTS to init block wakeup status - G_cme_stop_record.core_blockpc = ((in32(G_CME_LCL_SISR) & BITS32(2, 2)) >> SHIFT32(3)); + G_cme_stop_record.core_blockpc = ((in32(G_CME_LCL_SICR) & BITS32(2, 2)) >> SHIFT32(3)); G_cme_stop_record.core_blockwu = G_cme_stop_record.core_blockpc; G_cme_stop_record.core_blockey = 0; G_cme_stop_record.core_suspendwu = G_cme_stop_record.core_blockpc; |
