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| author | Claus Michael Olsen <cmolsen@us.ibm.com> | 2017-08-23 10:23:28 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 19:06:02 -0500 |
| commit | 14856420b44e5fb7babfc9e2e87e0dbd9b4668fe (patch) | |
| tree | 5b045b16fe937f883ed8f2bf1fe3dd23f06ef4bd /import/chips/p9/utils | |
| parent | b0961c2da7b71d7f1008b9f368128a92a43f43dc (diff) | |
| download | talos-hcode-14856420b44e5fb7babfc9e2e87e0dbd9b4668fe.tar.gz talos-hcode-14856420b44e5fb7babfc9e2e87e0dbd9b4668fe.zip | |
TOR magic header commit: Primer for commit 35372
To prevent a co-req situation between the HW image and the SBE
image in connection with the merging of the TOR magic header
commit 35372, the following code updates have been made:
- Updated the TOR header file to define the data and structures
needed on the ppe side in plat_ring_traverse.C to make
SBE putRing code backward HW image compatible.
Change-Id: I14cae65911938c4ae8e853ea9149f10e0d2fe9b8
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45046
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/utils')
| -rw-r--r-- | import/chips/p9/utils/imageProcs/p9_tor.H | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/import/chips/p9/utils/imageProcs/p9_tor.H b/import/chips/p9/utils/imageProcs/p9_tor.H index 57177929..aeb7db51 100644 --- a/import/chips/p9/utils/imageProcs/p9_tor.H +++ b/import/chips/p9/utils/imageProcs/p9_tor.H @@ -38,6 +38,37 @@ extern const char* ringVariantName[]; #define TOR_VERSION 2 +// +// TOR Magic values for top-level TOR image and TOR sub-images +// +enum TorMagicNum +{ + TOR_MAGIC = (uint32_t)0x544F52 , // "TOR" + TOR_MAGIC_HW = (uint32_t)0x544F5248, // "TORH" + TOR_MAGIC_SBE = (uint32_t)0x544F5242, // "TORB" + TOR_MAGIC_SGPE = (uint32_t)0x544F5247, // "TORG" + TOR_MAGIC_CME = (uint32_t)0x544F524D, // "TORM" + TOR_MAGIC_OVRD = (uint32_t)0x544F5252, // "TORR" + TOR_MAGIC_OVLY = (uint32_t)0x544F524C, // "TORL" + TOR_MAGIC_CEN = (uint32_t)0x544F524E, // "TORN" +}; + +typedef uint8_t ChipType_t; + +// +// TOR header field (appears in top of every HW, SBE, CEN, OVRD, etc ring section) +// +typedef struct +{ + uint32_t magic; + uint8_t version; + ChipType_t chipType; // Value from ChipType enum + uint8_t ddLevel; // =0xff if MAGIC_HW, >0 all other MAGICs + uint8_t numDdLevels; // >0 if MAGIC_HW, =1 all other MAGICs + uint32_t size; // Size of the TOR ringSection. +} TorHeader_t; + + typedef struct { uint32_t TorNumDdLevels; |
