PGPE Boot Fixes

- Setup OCC SRAM pointers
- Performed read-mod-write to OCC SCRATCH2 reg
- Fixed debug trap insertion
- Refined some traces for debug
- Added linker script fix for .pgpe_image_header

Change-Id: Id49de48d1cb1ca9ffc1cb343f3a8cb99a7803eca
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35181
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

14 files changed, 125 insertions, 61 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/link.cmd b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/link.cmd
index 5d686564..5876d922 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/link.cmd
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/link.cmd
@@ -35,7 +35,9 @@ OUTPUT_FORMAT(elf32-powerpc);
 // GPE2 is loaded at 0xfff20000
 #define SRAM_START 0xfff20000
 #define SRAM_LENGTH 0x10000
-#define PPE_DEBUG_PTRS_OFFSET 0x1E0
+#define PGPE_HEADER_OFFSET    0x180
+//debug pointer offset at an offset of 0x200
+#define PPE_DEBUG_PTRS_OFFSET PGPE_HEADER_OFFSET + 0x80
 
 MEMORY
 {
@@ -58,6 +60,14 @@ SECTIONS
     .vectors  _VECTOR_START  : { *(.vectors) } > sram
 
     ///////////////////////////////////////////////////////////////////////////
+    //
+    // PGPE Image Header
+    //
+    ///////////////////////////////////////////////////////////////////////////
+    _PGPE_IMG_HEADER = _VECTOR_START + PGPE_HEADER_OFFSET;
+    .pgpe_image_header _PGPE_IMG_HEADER : { *(.pgpe_image_header) } > sram
+
+    ///////////////////////////////////////////////////////////////////////////
     // Debug Pointers Table
     //
     // We want the debug pointers table to always appear at
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_boot_temp.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_boot_temp.c
index 789f5b8b..e00ed8f1 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_boot_temp.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_boot_temp.c
@@ -26,7 +26,7 @@
 #include "p9_pstates_pgpe.h"
 #include "p9_pgpe_header.h"
 
-extern pgpe_header_data_t* G_pgpe_header_data;
+extern PgpeHeader_t* G_pgpe_header_data;
 
 //
 //Local function prototypes
@@ -54,23 +54,25 @@ void p9_pgpe_boot_temp()
 void p9_pgpe_boot_pgpe_header_init()
 {
     //fill it in
-    G_pgpe_header_data->magic_number[0] =  0x32323232;//magic
-    G_pgpe_header_data->_system_reset_addr  = (uint32_t*)0xffff2040;//system_reset_address
-    G_pgpe_header_data->IVPR_address = (uint32_t*)0xffff2000;//IVPR address
+    G_pgpe_header_data->g_pgpe_magic_number[0] =  0x32323232;//magic
+    G_pgpe_header_data->g_pgpe_sys_reset_addr  = (uint32_t*)0xffff2040;//system_reset_address
+    G_pgpe_header_data->g_pgpe_ivpr_addr = (uint32_t*)0xffff2000;//IVPR address
 #if !BOOT_TEMP_SET_FULL_OCC_IPC_FUNC
-    G_pgpe_header_data->pgpeflags = (uint16_t)(0x0080); //OCC IPC Immediate Response
+    G_pgpe_header_data->g_pgpe_qm_flags = (uint16_t)(0x0080); //OCC IPC Immediate Response
 #else
-    G_pgpe_header_data->pgpeflags = (uint16_t)(0x0000); //OCC IPC Full Functionality
+    G_pgpe_header_data->g_pgpe_qm_flags = (uint16_t)(0x0000); //OCC IPC Full Functionality
 #endif //BOOT_TEMP_SET_FULL_OCC_IPC_FUNC
-    G_pgpe_header_data->gppb_sram_addr  = (uint32_t*)0xfff27000;//GPPB Sram Offset
-    G_pgpe_header_data->gppb_memory_offset = 0;//GPPB Memory Offset
-    G_pgpe_header_data->gppb_block_length  = 0x2000;//GPPB Block Length
-    G_pgpe_header_data->pstate_tbl_mem_offset  = (uint32_t*)0x80308000;//Pstate Tables Memory Offset
-    G_pgpe_header_data->pstate_tbl_length  = 0x6000;//Pstate Tables Length
-    G_pgpe_header_data->occ_pstate_tbl_addr  = (uint32_t*)0xfff29000;//OCC Pstate table address
-    G_pgpe_header_data->occ_pstate_tbl_length  = 0x100;//OCC Pstate table length
-    G_pgpe_header_data->pgpe_beacon = (uint32_t*)(0xfff26fe0 + 4);
-    G_pgpe_header_data->actual_quad_status_addr = (uint32_t*)(0xfff26fe0 + 8);
+    G_pgpe_header_data->g_pgpe_gppb_mem_offset = 0;//GPPB Memory Offset
+    G_pgpe_header_data->g_pgpe_gppb_length  = 0x2000;//GPPB Block Length
+    G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset  = (uint32_t*)0x80308000;//Pstate Tables Memory Offset
+    G_pgpe_header_data->g_pgpe_gen_pstables_length  = 0x6000;//Pstate Tables Length
+
+    /*
+    G_pgpe_header_data->g_pgpe_gppb_sram_addr  = (uint32_t*)0xfff27000;//GPPB Sram Offset
+    G_pgpe_header_data->g_pgpe_occ_pstables_sram_addr = (uint32_t*)0xfff29000;//OCC Pstate table address
+    G_pgpe_header_data->g_pgpe_occ_pstables_len  = 0x100;//OCC Pstate table length
+    G_pgpe_header_data->g_pgpe_beacon_addr = (uint32_t*)(0xfff26fe0 + 4);
+    G_pgpe_header_data->g_quad_status_addr = (uint32_t*)(0xfff26fe0 + 8);*/
 }
 
 //
@@ -83,7 +85,7 @@ void p9_pgpe_boot_gppb_init()
     int32_t i;
 
     //read value of symbol pstate_parameter_block
-    void* gppb_sram_offset = G_pgpe_header_data->gppb_sram_addr;//GPPB Sram Offset
+    void* gppb_sram_offset = G_pgpe_header_data->g_pgpe_gppb_sram_addr;//GPPB Sram Offset
 
     GlobalPstateParmBlock* gppb = (GlobalPstateParmBlock*)gppb_sram_offset;
     gppb->magic = PSTATE_PARMSBLOCK_MAGIC;
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
index b267c38c..7d4d652a 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
@@ -29,7 +29,7 @@
 uint8_t G_fit_count_threshold;
 uint8_t G_fit_count;
 extern GlobalPstateParmBlock* G_gppb;
-extern pgpe_header_data_t* G_pgpe_header_data;
+extern PgpeHeader_t* G_pgpe_header_data;
 
 //
 //Local function declarations
@@ -84,7 +84,7 @@ void p9_pgpe_fit_handler(void* arg, PkIrqId irq)
     if (G_fit_count == G_fit_count_threshold)
     {
         //write to SRAM
-        *(G_pgpe_header_data->pgpe_beacon) = *(G_pgpe_header_data->pgpe_beacon) + 1;
+        *(G_pgpe_header_data->g_pgpe_beacon_addr) = *(G_pgpe_header_data->g_pgpe_beacon_addr) + 1;
         G_fit_count = 0;
     }
     else
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
index 7cb1c9dc..f366fcca 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
@@ -31,7 +31,7 @@
 
 //Generated PState Table in SRAM
 GeneratedPstateInfo G_gpi;
-extern pgpe_header_data_t* G_pgpe_header_data;
+extern PgpeHeader_t* G_pgpe_header_data;
 extern VpdOperatingPoint G_operating_points[NUM_VPD_PTS_SET][VPD_PV_POINTS];
 
 //
@@ -48,9 +48,9 @@ void p9_pgpe_gen_pstate_info()
 {
     int p;
     //Get GlobalPstateParmBlock offset from pgpe_header
-    uint32_t* pstate_tbl_memory_offset  = G_pgpe_header_data->pstate_tbl_mem_offset;
-    uint32_t pstate_tbl_length = G_pgpe_header_data->pstate_tbl_length;
-    void* gppb_sram_offset = G_pgpe_header_data->gppb_sram_addr;//GPPB Sram Offset
+    uint32_t* pstate_tbl_memory_offset  = G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset;
+    uint32_t pstate_tbl_length = G_pgpe_header_data->g_pgpe_gen_pstables_length;
+    void* gppb_sram_offset = G_pgpe_header_data->g_pgpe_gppb_sram_addr;//GPPB Sram Offset
     GlobalPstateParmBlock* gppb = (GlobalPstateParmBlock*)gppb_sram_offset;
 
     //Fill out GeneratedPstateInfo structure
@@ -153,8 +153,8 @@ void p9_pgpe_gen_biased_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo
 void p9_pgpe_gen_occ_pstate_tbl(GeneratedPstateInfo* gpi)
 {
     int p;
-    OCCPstateTable_t* opst = (OCCPstateTable_t*)G_pgpe_header_data->occ_pstate_tbl_addr;
-    opst->entries = (G_pgpe_header_data->occ_pstate_tbl_length) / sizeof(OCCPstateTable_entry_t);
+    OCCPstateTable_t* opst = (OCCPstateTable_t*)G_pgpe_header_data->g_pgpe_occ_pstables_sram_addr;
+    opst->entries = (G_pgpe_header_data->g_pgpe_occ_pstables_len) / sizeof(OCCPstateTable_entry_t);
 
     for (p = 0; p <= opst->entries; p++)
     {
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c
index 0242fd42..177d5875 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c
@@ -33,7 +33,7 @@ VpdOperatingPoint G_operating_points[NUM_VPD_PTS_SET][VPD_PV_POINTS];
 uint8_t G_pstate0_dpll_value;
 uint32_t G_ext_vrm_inc_rate_mult_usperus;
 uint32_t G_ext_vrm_dec_rate_mult_usperus;
-extern pgpe_header_data_t* G_pgpe_header_data;
+extern PgpeHeader_t* G_pgpe_header_data;
 
 //
 //Private function prototypes
@@ -52,7 +52,7 @@ uint8_t p9_pgpe_gppb_get_ps_region(Pstate ps, uint8_t vpt_pt_set);
 //Note: In future, the slope calculation might be done offline
 void p9_pgpe_gppb_init()
 {
-    void* gppb_sram_offset = G_pgpe_header_data->gppb_sram_addr;//GPPB Sram Offset
+    void* gppb_sram_offset = G_pgpe_header_data->g_pgpe_gppb_sram_addr;//GPPB Sram Offset
     G_gppb = (GlobalPstateParmBlock*)gppb_sram_offset;
 
     //Apply Biases and System Parameters
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c
index c819b021..5178f0c9 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c
@@ -23,8 +23,13 @@
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 #include "p9_pgpe_header.h"
+#include "pstate_pgpe_occ_api.h"
 
-pgpe_header_data_t* G_pgpe_header_data;
+//OCC Shared SRAM starts at bottom 2K of PGPE OCC SRAM space
+#define OCC_SHARED_SRAM_ADDR_START (0xfff20000 + 0x10000 - 0x800)
+
+PgpeHeader_t* G_pgpe_header_data;
+extern PgpeHeader_t* _PGPE_IMG_HEADER __attribute__ ((section (".pgpe_image_header")));
 
 //
 //Set the pgpe_header_data struct to point to PGPE HEADER in SRAM
@@ -34,5 +39,17 @@ pgpe_header_data_t* G_pgpe_header_data;
 //
 void p9_pgpe_header_init()
 {
-    G_pgpe_header_data = (pgpe_header_data_t*)0xfff20180;
+    G_pgpe_header_data = (PgpeHeader_t*)&_PGPE_IMG_HEADER;
+}
+
+void p9_pgpe_header_fill()
+{
+    HcodeOCCSharedData_t* occ_shared_data = (HcodeOCCSharedData_t*)
+                                            OCC_SHARED_SRAM_ADDR_START; //Bottom 2K of PGPE OCC Sram Space
+    G_pgpe_header_data->g_pgpe_occ_pstables_sram_addr = (uint32_t*)&occ_shared_data->pstate_table;//OCC Pstate table address
+    G_pgpe_header_data->g_pgpe_occ_pstables_len  = sizeof(OCCPstateTable_t);//OCC Pstate table length
+    G_pgpe_header_data->g_pgpe_beacon_addr = (uint32_t*)&occ_shared_data->pgpe_beacon;
+    G_pgpe_header_data->g_quad_status_addr = (uint32_t*)&occ_shared_data->quad_pstate_0;
+
+    G_pgpe_header_data->g_pgpe_gppb_sram_addr  = (uint32_t*)0xfff27000;//GPPB Sram Offset
 }
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.h
index 1c91be93..a39a9910 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.h
@@ -32,7 +32,7 @@
 //\todo RTC: 164335 Use the structure from p9_hcode_image_defines.H
 //when it's updated
 //
-typedef struct pgpe_header_data
+/*typedef struct pgpe_header_data
 {
     uint32_t magic_number[2];
     uint32_t* _system_reset_addr;
@@ -55,8 +55,35 @@ typedef struct pgpe_header_data
     uint32_t* actual_quad_status_addr;
     uint32_t* wof_tbl_addr;
     uint32_t wof_tbl_lengh;
-} pgpe_header_data_t;
+} PgpeHeader_t;*/
+
+typedef struct
+{
+    uint32_t  g_pgpe_magic_number[2];            // PGPE_1.0
+    uint32_t* g_pgpe_sys_reset_addr;          // Fully qualified OCC address where pk_init resides
+    uint32_t* g_pgpe_shared_sram_addr;        // SRAM address where shared SRAM begins
+    uint32_t* g_pgpe_ivpr_addr;               // Beginning of PGPE region in OCC SRAM
+    uint32_t  g_pgpe_shared_sram_len;         // Length of shared SRAM area
+    uint32_t  g_pgpe_build_date;              // Build date for PGPE Image
+    uint32_t  g_pgpe_build_ver;               // Build Version
+    uint16_t  g_pgpe_qm_flags;                // QM Flags
+    uint16_t  g_pgpe_reserve1;                // Reserve field
+    uint32_t  g_pgpe_reserve2;                // Reserve field
+    uint32_t* g_pgpe_gppb_sram_addr;          // Offset to Global P State Parameter Block
+    uint32_t  g_pgpe_reserve3;                // Reserve field
+    uint32_t* g_pgpe_gppb_mem_offset;         // Offset to start of Global PS Param Block wrt start of HOMER.
+    uint32_t  g_pgpe_gppb_length;             // Length of Global P State Parameter Block
+    uint32_t* g_pgpe_gen_pstables_mem_offset; // Offset to PState Table wrt start of HOMER
+    uint32_t  g_pgpe_gen_pstables_length;     // Length of P State table
+    uint32_t* g_pgpe_occ_pstables_sram_addr;  // Offset to start of OCC P-State table
+    uint32_t  g_pgpe_occ_pstables_len;        // Length of OCC P-State table
+    uint32_t* g_pgpe_beacon_addr;             // SRAM addr where PGPE beacon is located
+    uint32_t* g_quad_status_addr;             // Actual Quad address
+    uint32_t* g_wof_table_addr;               // WOF Table Address
+    uint32_t  g_wof_table_length;             // WOF Table Length
+} PgpeHeader_t;
 
 void p9_pgpe_header_init();
+void p9_pgpe_header_fill();
 
 #endif //_P9_PGPE_HEADER_H_
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ipc_handlers.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ipc_handlers.c
index c025196e..0540dc26 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ipc_handlers.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ipc_handlers.c
@@ -49,7 +49,7 @@ extern uint8_t G_pstatesEnabled;
 extern PgpePstateRecord G_pgpe_pstate_record;
 extern uint32_t G_already_sem_posted;
 extern uint8_t G_pmcrOwner;
-extern pgpe_header_data_t* G_pgpe_header_data;
+extern PgpeHeader_t* G_pgpe_header_data;
 
 //
 //p9_pgpe_ipc_init
@@ -86,7 +86,7 @@ void p9_pgpe_ipc_405_start_stop(ipc_msg_t* cmd, void* arg)
     ipc_async_cmd_t* async_cmd = (ipc_async_cmd_t*)cmd;
     ipcmsg_start_stop_t* args = (ipcmsg_start_stop_t*)async_cmd->cmd_data;
 
-    if(G_pgpe_header_data->pgpeflags & OCC_IPC_IMMEDIATE_RESP)
+    if(G_pgpe_header_data->g_pgpe_qm_flags & OCC_IPC_IMMEDIATE_RESP)
     {
         args->msg_cb.rc = PGPE_RC_SUCCESS;
         ipc_send_rsp(cmd, IPC_RC_SUCCESS);
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
index df7820f4..70152a19 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
@@ -78,8 +78,7 @@ IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_STRM2_PUSH
 IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_STRM3_PULL
 IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_STRM3_PUSH
 IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_PCB_INTR_TYPE0_PENDING
-IRQ_HANDLER(p9_pgpe_irq_handler_pcb_type1, (void*) & G_pgpe_pstate_record.sem_process_req)
-//OCCHW_IRQ_PMC_PCB_INTR_TYPE1_PENDING
+IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_PCB_INTR_TYPE1_PENDING
 IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING
 IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_PCB_INTR_TYPE3_PENDING
 IRQ_HANDLER_DEFAULT            //OCCHW_IRQ_PMC_PCB_INTR_TYPE4_PENDING
@@ -122,13 +121,6 @@ void __eabi()
 int
 main(int argc, char** argv)
 {
-    //Read OCC_SCRATCH[PGPE_DEBUG_TRAP_ENABLE]]
-    uint32_t occScr2 = in32(OCB_OCCS2);
-
-    if (occScr2 & BIT32(PGPE_DEBUG_TRAP_ENABLE))
-    {
-        asm volatile ("tw 0, 31, 0");
-    }
 
     // Initializes kernel data (stack, threads, timebase, timers, etc.)
     pk_initialize((PkAddress)G_kernel_stack,
@@ -136,6 +128,15 @@ main(int argc, char** argv)
                   0,
                   PPE_TIMEBASE_HZ);
 
+    // Read OCC_SCRATCH[PGPE_DEBUG_TRAP_ENABLE]
+    uint32_t occScr2 = in32(OCB_OCCS2);
+
+    if (occScr2 & BIT32(PGPE_DEBUG_TRAP_ENABLE))
+    {
+        PK_TRACE_DBG("MAIN: Debug trap detected");
+        asm volatile ("trap");
+    }
+
     // Initialize the thread control block for G_p9_pgpe_thread_process_requests
     pk_thread_create(&G_p9_pgpe_thread_process_requests,
                      (PkThreadRoutine)p9_pgpe_thread_process_requests,
@@ -166,6 +167,10 @@ main(int argc, char** argv)
 
     //Do initialization
     p9_pgpe_header_init();
+
+    PK_TRACE_DBG("Update PGPE Header with pertinent OCC SRAM information");
+    p9_pgpe_header_fill();
+
 #if USE_BOOT_TEMP
     //This is to be used for development and testing/verif
     //if Global Pstate Parameter Block is not initialized through other means.
@@ -176,19 +181,21 @@ main(int argc, char** argv)
     p9_pgpe_boot_temp(); //This is just temporary
 #endif
 
+    PK_TRACE_DBG("Initializing from Global Pstate Parameter Block");
     p9_pgpe_gppb_init();
 
 #if GEN_PSTATE_TBL
+    PK_TRACE_DBG("Generating Pstate Tables to memory");
     p9_pgpe_gen_pstate_info();
 #endif
 
-    //Setup FIT(Fixed-Interval Timer)
+    PK_TRACE_DBG("Setup FIT(Fixed-Interval Timer)");
     p9_pgpe_fit_init();
 
-    //Initialize all pstate related data to some default values
+    PK_TRACE_DBG("Initialize all pstate related data to some default values");
     p9_pgpe_pstate_init();
 
-    PK_TRACE_DBG("Starting PK Threads\n");
+    PK_TRACE_DBG("Starting PK Threads");
 
     // Start running the highest priority thread.
     // This function never returns
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
index 12c93b9c..f5fc3a3b 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
@@ -38,7 +38,7 @@
 //
 //Global External Data
 //
-extern pgpe_header_data_t* G_pgpe_header_data;
+extern PgpeHeader_t* G_pgpe_header_data;
 
 //
 //Global Data
@@ -106,8 +106,8 @@ void p9_pgpe_pstate_init()
         G_globalPSNext  = G_operating_points[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate;
     }
 
-    G_quadState0 = (quad_state0_t*)G_pgpe_header_data->actual_quad_status_addr;
-    G_quadState1 = (quad_state1_t*)(G_pgpe_header_data->actual_quad_status_addr + 2);
+    G_quadState0 = (quad_state0_t*)G_pgpe_header_data->g_quad_status_addr;
+    G_quadState1 = (quad_state1_t*)(G_pgpe_header_data->g_quad_status_addr + 2);
 }
 
 //
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
index 2bdd43ee..9d20558a 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c
@@ -61,7 +61,6 @@ extern uint8_t G_quadPSNext[MAX_QUADS];      //target Pstate per quad
 extern uint8_t G_globalPSNext;
 extern uint32_t G_eVidCurr, G_eVidNext;
 extern GlobalPstateParmBlock* G_gppb;
-extern pgpe_header_data_t* G_pgpe_header_data;
 extern uint8_t G_psClipMax[MAX_QUADS],
        G_psClipMin[MAX_QUADS];         //pmin and pmax clips
 extern uint8_t G_pmcrOwner;
@@ -94,9 +93,14 @@ void p9_pgpe_thread_actuate_pstates(void* arg)
     //Initialize Shared SRAM to a known state
     p9_pgpe_thread_actuate_init_actual_quad();
 
+    // Set OCC Scratch2[PGPE_ACTIVE]
+    uint32_t occScr2 = in32(OCB_OCCS2);
+    occScr2 |= BIT32(PGPE_ACTIVE);
 #if PGPE_UNIT_TEST
-    out32(OCB_OCCS2, BIT32(30));
+    occScr2 |= BIT32(30);
 #endif
+    PK_TRACE_DBG("Setting PGPE_ACTIVE in OCC SCRATCH2 addr %X = %X\n", OCB_OCCS2, occScr2);
+    out32(OCB_OCCS2, occScr2);
 
     //Thread Loop
     while(1)
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
index a800ab97..ef9896f9 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
@@ -36,8 +36,8 @@
 //External Global Data
 //
 extern PgpePstateRecord G_pgpe_pstate_record;
-extern pgpe_header_data_t* G_pgpe_header_data;
 extern uint8_t G_pstatesEnabled;               //pstates_enabled/disable
+extern PgpeHeader_t* G_pgpe_header_data;
 extern uint8_t G_wofEnabled;               //pstates_enabled/disable
 extern uint8_t G_wofPending;                   //wof enable pending
 extern VFRT_Hcode_t* G_vfrt_ptr;
@@ -48,7 +48,6 @@ extern uint8_t G_coresPSRequest[MAX_CORES];    //per core requested pstate
 extern uint32_t G_already_sem_posted;
 extern quad_state0_t* G_quadState0;
 extern quad_state1_t* G_quadState1;
-extern pgpe_header_data_t* G_pgpe_header_data;
 extern ipc_async_cmd_t G_ipc_msg_pgpe_sgpe;
 GPE_BUFFER(extern ipcmsg_p2s_ctrl_stop_updates_t G_sgpe_control_updt);
 
@@ -78,13 +77,11 @@ void p9_pgpe_thread_process_requests(void* arg)
     //IPC Init
     p9_pgpe_ipc_init();
 
-    //Set OCC_FLAG[PGPE_ACTIVE]
-    out32(OCB_OCCFLG_OR, BIT32(4));
 #if EPM_P9_TUNING
     asm volatile ("tw 0, 31, 0");
 #endif
 
-    PK_TRACE_DBG("PROCTH:Inited\n");
+    PK_TRACE_DBG("PROCTH:Inited; PGPE_ACTIVE set\n");
 
     while(1)
     {
@@ -293,7 +290,7 @@ void p9_pgpe_process_clip_updt()
 
     G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].pending_processing = 0;
 
-    if(G_pgpe_header_data->pgpeflags & OCC_IPC_IMMEDIATE_RESP)
+    if(G_pgpe_header_data->g_pgpe_qm_flags & OCC_IPC_IMMEDIATE_RESP)
     {
         PK_TRACE_DBG("PROCTH: Clip Updt Imme\n");
         G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].pending_ack = 0;
@@ -343,7 +340,7 @@ void p9_pgpe_process_wof_ctrl()
 
     G_ipc_pend_tbl[IPC_PEND_WOF_CTRL].pending_processing = 0;
 
-    if(G_pgpe_header_data->pgpeflags & OCC_IPC_IMMEDIATE_RESP)
+    if(G_pgpe_header_data->g_pgpe_qm_flags & OCC_IPC_IMMEDIATE_RESP)
     {
         G_ipc_pend_tbl[IPC_PEND_WOF_CTRL].pending_ack = 0;
         args->msg_cb.rc = PGPE_RC_SUCCESS;
@@ -438,7 +435,7 @@ void p9_pgpe_process_wof_vfrt()
 
     G_ipc_pend_tbl[IPC_PEND_WOF_VFRT].pending_processing = 0;
 
-    if(G_pgpe_header_data->pgpeflags & OCC_IPC_IMMEDIATE_RESP)
+    if(G_pgpe_header_data->g_pgpe_qm_flags & OCC_IPC_IMMEDIATE_RESP)
     {
         G_ipc_pend_tbl[IPC_PEND_WOF_VFRT].pending_ack = 0;
         args->msg_cb.rc = PGPE_RC_SUCCESS;
@@ -531,7 +528,7 @@ void p9_pgpe_process_set_pmcr_req()
 
     G_ipc_pend_tbl[IPC_PEND_SET_PMCR_REQ].pending_processing = 0;
 
-    if(G_pgpe_header_data->pgpeflags & OCC_IPC_IMMEDIATE_RESP)
+    if(G_pgpe_header_data->g_pgpe_qm_flags & OCC_IPC_IMMEDIATE_RESP)
     {
         G_ipc_pend_tbl[IPC_PEND_SET_PMCR_REQ].pending_ack = 0;
         args->msg_cb.rc = PGPE_RC_SUCCESS;
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
index 818abb00..b4e73f1e 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
@@ -38,7 +38,7 @@
 #define EPM_P9_TUNING 1
 #define SIMICS_TUNING 0
 #define GEN_PSTATE_TBL 0
-#define USE_BOOT_TEMP 1
+#define USE_BOOT_TEMP 0
 #define BOOT_TEMP_SET_FULL_OCC_IPC_FUNC 1
 #define DEV_DEBUG     1
 #define PGPE_UNIT_TEST 1
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
index 73eee021..c878a223 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
@@ -80,7 +80,7 @@ $(IMAGE)_TRACE_HASH_PREFIX := $(shell echo $(IMAGE) | md5sum | cut -c1-4 \
 	| xargs -i printf "%d" 0x{})
 
 # Options for PK_TRACE
-$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=0
+$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=3
 $(IMAGE)_COMMONFLAGS+= -DPK_TRACE_TIMER_OUTPUT=0