diff options
author | Christopher M. Riedl <cmriedl@us.ibm.com> | 2017-04-06 16:57:06 -0500 |
---|---|---|
committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:24:22 -0500 |
commit | 71c1ab3670cd08dbe37524131c599027065d0b2b (patch) | |
tree | 21df870caffc99e6dab94e4d28bc35cf67ca79d3 /import/chips/p9/procedures | |
parent | 289df58cd61f8c933b230f99755e9afbb5f38219 (diff) | |
download | talos-hcode-71c1ab3670cd08dbe37524131c599027065d0b2b.tar.gz talos-hcode-71c1ab3670cd08dbe37524131c599027065d0b2b.zip |
PM: Resonant Clocking Enablement - Infrastructure
- update/implement resonant clocking pstate parameter block procedure
- implement a function to initialize resclk attributes to defaults from
a header file (header to be updated by clocking team)
- update/fix resclk attributes in xml
Change-Id: I0bb83303cdc5452931a72fb970931c6aff43c03b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38954
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures')
-rw-r--r-- | import/chips/p9/procedures/hwp/lib/p9_resclk_defines.H | 139 |
1 files changed, 139 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_resclk_defines.H b/import/chips/p9/procedures/hwp/lib/p9_resclk_defines.H index 69d7da9c..9ba17158 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_resclk_defines.H +++ b/import/chips/p9/procedures/hwp/lib/p9_resclk_defines.H @@ -22,3 +22,142 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// +/// @file p9_resclk_defines.H +/// @brief Defines Resonant Clocking default values (provided by clock team). +/// +// *HWP HWP Owner: +// *HWP FW Owner: +// *HWP Team: PM +// *HWP Level: +// *HWP Consumed by: + +#ifndef __P9_RESCLK_DEFINES_H__ +#define __P9_RESCLK_DEFINES_H__ + +#include <vector> + +namespace p9_resclk_defines +{ +typedef struct +{ + uint16_t freq; + uint8_t idx; +} rsclk_freq_idx_t; +//############################################################################### +// Table 1: Resonant Clocking Control Index +// consists of 8 entries consisting of a comma-delimited pair. +// Freq(in Mhz), Index(decimal number between 0 & 63, index into the next table) +// The first entry is always 0 Mhz. Entries are in ascending order of frequency. +// Algorithm will search starting at the bottom of the index until it +// finds the first entry at or below target frequency, then walk to that index. +//############################################################################### +std::vector<rsclk_freq_idx_t> const RESCLK_INDEX_VEC = +{ + // { Freq, Idx} + { 0, 3 }, + { 1500, 3 }, + { 2000, 24 }, + { 3000, 24 }, + { 3400, 24 }, + { 3700, 24 }, + { 3900, 24 }, + { 4100, 24 } +}; +//############################################################################### +// Table 2: Resonant (Core & L2) Grids Control Data +// 64 entries,each entry a 16-bit hex value. +// First row corresponds to Index 0 from Table 1. Last row is Index 63. +// Left aligned hex value corresponding to the first 13-bits of the QACCR register +// 0:3 SB_STRENGTH; 4 SB_SPARE; 6:7 SB_PULSE_MODE; 8:11 SW_RESCLK; 12 SW_SPARE +//############################################################################### +std::vector<uint16_t> const RESCLK_TABLE_VEC = +{ + 0x2000, + 0x3000, + 0x1000, + 0x0000, + 0x0010, + 0x0030, + 0x0020, + 0x0060, + 0x0070, + 0x0050, + 0x0040, + 0x00C0, + 0x00D0, + 0x00F0, + 0x00E0, + 0x00A0, + 0x00B0, + 0x0090, + 0x0080, + 0x8080, + 0x9080, + 0xB080, + 0xA080, + 0xE080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080, + 0xF080 +}; +//############################################################################### +// Table 3: L3 Grid Control Data +// 4 entries, each a 8-bit hex value to transition between two modes +// Entry 0 is the "Full Power" setting +// Entry 3 is the "Low Power" setting, for use above voltages defined by +// L3_VOLTAGE_THRESHOLD_MV (ATTR_SYSTEM_RESCLK_L3_VOLTAGE_THRESHOLD_MV) +// Hex value corresponding to L3 control bits in the QACCR(16:23) +// 0:3 SB_STRENGTH; (Not supported: 4 SB_SPARE; 5:7 SB_PULSE_MODE) +//############################################################################### +std::vector<uint8_t> const L3CLK_TABLE_VEC +{ + 0, + 1, + 3, + 2 +}; +//############################################################################### +// L3 Voltage Threshold (millivolts) +//############################################################################### +uint16_t const L3_VOLTAGE_THRESHOLD_MV = 600; +} + +#endif //__P9_RESCLK_DEFINES_H__ |