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| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2016-11-15 11:46:20 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 16:55:35 -0500 |
| commit | 9eaca9f4f4f72f1e76fb6bbfa92393b20f43fb6c (patch) | |
| tree | 325188199e80d6db83ed67abac583505f5b3b4ec /import/chips/p9/procedures/utils | |
| parent | df4b3eb17a95d06517e156e5b715ec4043dd61c7 (diff) | |
| download | talos-hcode-9eaca9f4f4f72f1e76fb6bbfa92393b20f43fb6c.tar.gz talos-hcode-9eaca9f4f4f72f1e76fb6bbfa92393b20f43fb6c.zip | |
PM: Corrected restoration of HRMOR in self restore sequence.
Self restore code was restoring HRMOR from an incorrect GPR.
Instead of R10, it was using R9 as a source of HRMOR value.
Self Restore code now determines the status of fused core using SPRC
and SPRD register pair. Before this change, fused core status was
determined using CPMR header's fuse mode status byte.
Change-Id: Ie1a624be3d39c34f10704a675cd3b3505a5b0ff1
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32666
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: ADAM S. HALE <ashale@us.ibm.com>
Dev-Ready: ADAM S. HALE <ashale@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/utils')
| -rwxr-xr-x | import/chips/p9/procedures/utils/stopreg/p9_core_restore_routines.S | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/import/chips/p9/procedures/utils/stopreg/p9_core_restore_routines.S b/import/chips/p9/procedures/utils/stopreg/p9_core_restore_routines.S index 7e7277ea..8ba35f39 100755 --- a/import/chips/p9/procedures/utils/stopreg/p9_core_restore_routines.S +++ b/import/chips/p9/procedures/utils/stopreg/p9_core_restore_routines.S @@ -147,11 +147,10 @@ .set THREAD_ID_REG, r6 .set CORE_RESTORE_BASE_ADDR_REG, r7 .set TEMP_REG, r8 - .set HRMOR_REST_REG, r9 .set FUSED_MODE_CONST, 0xBB #Chose this flag to be an arbitrary unique value - .set NEXT_INST_ADDRESS_REG, r10 + .set HRMOR_RESTORE_REG, r10 .set THREAD_ACTIVE_STATE_REG, r11 - .set CORE_SCOPE_RESTORE_ADDR_REG, r12 + .set CORE_SCOPE_RESTORE_ADDR_REG, r12 .set STOP, 0x4C0002E4 .set ATTN, 0x00000200 #--------------------------------------------------------------------# @@ -297,7 +296,7 @@ thread_launcher_start: mfspr PIR_VAL_REG, PIR #Processor Identification Register #Select to read the Thread State Status register in PC using SPRC & SPRD -li TEMP_REG, CORE_THREAD_STATE_REG_ID_CONST +li TEMP_REG, CORE_THREAD_STATE_REG_ID_CONST mtspr SPRC, TEMP_REG mfspr FUSED_STATUS_REG, SPRD extrdi. FUSED_STATUS_REG, FUSED_STATUS_REG, 1, 63 @@ -397,7 +396,7 @@ blrl # branch to core register restore area .align 4 core_reg_restore_return: #so far core reg restored except HRMOR -mtspr HRMOR, HRMOR_REST_REG +mtspr HRMOR, HRMOR_RESTORE_REG enter_stop_state: |
