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| author | Amit Kumar <akumar3@us.ibm.com> | 2016-06-02 23:57:06 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 16:10:33 -0500 |
| commit | 740c115ff0ee4b0bf0b26e0f1b49356ded5a2bd0 (patch) | |
| tree | 4370a5b96156c4a8b2dec2c1d737cf71522968ff /import/chips/p9/procedures/utils | |
| parent | b63b14870c61a5bc68ebb67030760ffb64fddd51 (diff) | |
| download | talos-hcode-740c115ff0ee4b0bf0b26e0f1b49356ded5a2bd0.tar.gz talos-hcode-740c115ff0ee4b0bf0b26e0f1b49356ded5a2bd0.zip | |
Core restore routine change
-Change to use SPR instead of load instruction to figure fused vs unfused mode
Change-Id: I913b03df459589d5d098e20ef8c9b2d7aab1dc7f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25328
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Dev-Ready: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/utils')
| -rwxr-xr-x | import/chips/p9/procedures/utils/stopreg/p9_core_restore_routines.S | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/import/chips/p9/procedures/utils/stopreg/p9_core_restore_routines.S b/import/chips/p9/procedures/utils/stopreg/p9_core_restore_routines.S index a3cf0d85..7e7277ea 100755 --- a/import/chips/p9/procedures/utils/stopreg/p9_core_restore_routines.S +++ b/import/chips/p9/procedures/utils/stopreg/p9_core_restore_routines.S @@ -295,10 +295,13 @@ rfid thread_launcher_start: mfspr PIR_VAL_REG, PIR #Processor Identification Register -mfspr CPMR_BASE_REG, HRMOR -lbz FUSED_STATUS_REG, 31(CPMR_BASE_REG) -cmpwi FUSED_STATUS_REG, FUSED_MODE_CONST -bne core_is_not_fused + +#Select to read the Thread State Status register in PC using SPRC & SPRD +li TEMP_REG, CORE_THREAD_STATE_REG_ID_CONST +mtspr SPRC, TEMP_REG +mfspr FUSED_STATUS_REG, SPRD +extrdi. FUSED_STATUS_REG, FUSED_STATUS_REG, 1, 63 +beq core_is_not_fused core_is_fused: #core is fused. Find physical core number from PIR bits. @@ -334,6 +337,7 @@ jump_thread_restore: extrdi TEMP_REG, PIR_VAL_REG, 3, 57 # get quad bits sldi TEMP_REG, TEMP_REG, 2 # quad id * 4 core chiplets per quad add CORE_ID_REG, CORE_ID_REG, TEMP_REG # P9 core id = 4 * quad id + index within Quad +mfspr CPMR_BASE_REG, HRMOR #************* find address where restore instructions are present********** @@ -373,10 +377,6 @@ blrl #branch to thread register restore thread_restore_return: cmpwi THREAD_ID_REG, 0 # is it thread 0 bne enter_stop_state # if thread not in STOP 15 -li TEMP_REG, CORE_THREAD_STATE_REG_ID_CONST # thread 0 has more to do - -#Select to read the Thread State Status register in PC using SPRC & SPRD -mtspr SPRC, TEMP_REG wait_until_single_thread: # wait till all threads are done restoring mfspr TEMP_REG, SPRD |
