PM: PM: Added support for self-restore in case of LE Hypervisor - stage 3

Change-Id: Ifd5c21b88e9494aea689c291136b90bde804882e
HW-Image-Prereq: 2e8b318cb00d6a4d1c425f87d5c7f1d0fa000162
RTC: 172449
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39420
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

2 files changed, 10 insertions, 10 deletions

diff --git a/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H b/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H
index 7a992690..8c0e9c57 100755
--- a/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H
+++ b/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H
@@ -60,7 +60,8 @@ enum
     RLDICR_CONST      = 1,
     MTSPR_CONST1      = 467,
     MTMSRD_CONST1     = 178,
-    MR_INT            = 0x7c0a0378,
+    MR_R0_TO_R10      = 0x7c0a0378, //mr r10, r0
+    MR_R0_TO_R21      = 0x7c150378, //mr r21, r0
     BLR_INST          = 0x4e800020,
     MTSPR_BASE_OPCODE = 0x7c0003a6,
     ATTN_OPCODE       = 0x00000200,
diff --git a/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C b/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C
index ddff921c..d2cab1a5 100755
--- a/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C
+++ b/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C
@@ -398,12 +398,6 @@ StopReturnCode_t updateSprEntryInImage( uint32_t* i_pSprEntryLocation,
             newEntry = false;
         }
 
-        if( P9_STOP_SPR_MSR == i_regId )
-        {
-            regRs = 21; //use r21 for instruction generation
-            regRa = 21;
-        }
-
         //Add SPR search instruction i.e. "ori r0, r0, SPRID"
         *i_pSprEntryLocation = tempInst;
         i_pSprEntryLocation += SIZE_PER_SPR_RESTORE_INST;
@@ -445,14 +439,19 @@ StopReturnCode_t updateSprEntryInImage( uint32_t* i_pSprEntryLocation,
 
         if( P9_STOP_SPR_MSR == i_regId )
         {
-            // Case MSR, move contents of R0 to an MSR
-            tempInst = getMtmsrdInstruction( regRa );
+            //MSR cannot be restored completely with mtmsrd instruction.
+            //as it does not update ME, LE and HV bits. In self restore code
+            //inorder to restore MSR, contents of R21 is moved to SRR1. It also
+            //executes an RFID which causes contents of SRR1 to be copied to
+            //MSR. This allows copy of LE bit which are specifically interested
+            //in. Instruction below moves contents of MSR Value (in R0 ) to R21.
+            tempInst = SWIZZLE_4_BYTE( MR_R0_TO_R21 );
         }
         else if (P9_STOP_SPR_HRMOR == i_regId )
         {
             //Case HRMOR, move contents of R0 to a placeholder GPR (R10)
             //Thread Launcher expects HRMOR value in R10
-            tempInst = SWIZZLE_4_BYTE(MR_INT);
+            tempInst = SWIZZLE_4_BYTE( MR_R0_TO_R10 );
         }
         else
         {