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| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2017-11-10 07:55:37 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2018-02-01 15:43:57 -0600 |
| commit | 8e213eb46460a89972c4e6f61131e3ec6fc66d18 (patch) | |
| tree | a4fc6a1de9fa94277e70f26930724e497e9e1cb9 /import/chips/p9/procedures/utils/stopreg | |
| parent | 8d39c7666e19c0969cb49dbdd5b962a1613252f1 (diff) | |
| download | talos-hcode-8e213eb46460a89972c4e6f61131e3ec6fc66d18.tar.gz talos-hcode-8e213eb46460a89972c4e6f61131e3ec6fc66d18.zip | |
PM: Fixed generation of MTSPR instruction in STOP API.
STOP API generates SPR restore instruction for a given SPR.
Commit fixes the generation of mtspr instruction by API.
Problem will show up only when API is changed to generate
restore instruction using a GPR other than R0.
CQ: SW407799
Change-Id: I2a841a9aae417b7bcd92a323197d9c6a1f3cb149
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49525
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: STEWART E. SMITH <stewart@linux.vnet.ibm.com>
Dev-Ready: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/utils/stopreg')
| -rwxr-xr-x | import/chips/p9/procedures/utils/stopreg/p9_stop_api.C | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C b/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C index a08cf045..a9902b0b 100755 --- a/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C +++ b/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2017 */ +/* COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -258,7 +258,7 @@ static uint32_t getMtsprInstruction( const uint16_t i_Rs, const uint16_t i_Spr ) uint32_t mtsprInstOpcode = 0; uint32_t temp = (( i_Spr & 0x03FF ) << 11); mtsprInstOpcode = (uint8_t)i_Rs << 21; - mtsprInstOpcode = ( temp & 0x0000F800 ) << 5; + mtsprInstOpcode |= ( temp & 0x0000F800 ) << 5; mtsprInstOpcode |= ( temp & 0x001F0000 ) >> 5; mtsprInstOpcode |= MTSPR_BASE_OPCODE; |
