CME: Reduce Image Size

        On some systems, the ring overrides size is more than
        anticipated, and causes a run time failure when CME Image
        is loaded during istep 15/16. Therefore, we are reducing CME Image Size
        by converting PK_TRACE_INF to PK_TRACE_DBG for some
        trace statements.

        Key_Cronus_Test=PM_REGRESS

Change-Id: Ie5959d251cf52f034dd9f6e47b343e6a7c9390c5
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/83116
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>

5 files changed, 40 insertions, 39 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c
index 0818517e..1c81eacd 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_iota_main.c
@@ -92,7 +92,7 @@ void fit_handler()
 
     if(BIT32(CPPM_CSAR_FIT_HCODE_ERROR_INJECT) & scom_data.words.upper)
     {
-        PKTRACE("CME FIT ERROR INJECT TRAP");
+        //PKTRACE("CME FIT ERROR INJECT TRAP");
         PK_PANIC(CME_STOP_ENTRY_TRAP_INJECT);
     }
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
index cba9f9e8..67d19d9c 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
@@ -120,7 +120,7 @@ p9_cme_pgpe_hb_loss_handler(void* arg, PkIrqId irq)
 
         if(FSafe)
         {
-            PK_TRACE_INF("Fsafe=0x%x", FSafe);
+            PK_TRACE_DBG("Fsafe=0x%x", FSafe);
             G_cme_pstate_record.nextPstate = G_lppb->dpll_pstate0_value - FSafe;
             G_cme_pstate_record.globalPstate = G_lppb->dpll_pstate0_value - FSafe;
             p9_cme_pstate_update_analog();
@@ -139,7 +139,7 @@ p9_cme_pgpe_hb_loss_handler(void* arg, PkIrqId irq)
 
         intercme_direct(INTERCME_DIRECT_IN2, INTERCME_DIRECT_ACK, 0);
 
-        PK_TRACE_INF("RCVed Notify and ACKed");
+        PK_TRACE_DBG("RCVed Notify and ACKed");
 
         out32(G_CME_LCL_FLAGS_CLR, BIT32(CME_FLAGS_PSTATES_ENABLED));
         out32(G_CME_LCL_FLAGS_OR, BIT32(CME_FLAGS_SAFE_MODE) |
@@ -428,7 +428,7 @@ void p9_cme_pstate_db3_handler(void)
             intercme_direct(INTERCME_DIRECT_IN2, INTERCME_DIRECT_ACK, 0);
         }
 
-        PK_TRACE_INF("PSTATE: DB3 Clip Exit");
+        PK_TRACE_DBG("PSTATE: DB3 Clip Exit");
     }
 
     else
@@ -463,7 +463,7 @@ void p9_cme_pstate_init()
 
     G_lppb = (LocalPstateParmBlock*)(pstate_offset + CME_SRAM_BASE_ADDR);
 
-    PK_TRACE_INF("PSTATE: Hdr=0x%x, LPPB=0x%x, Nominal_Freq_Mhz=%d ", (uint32_t)G_cmeHeader, (uint32_t)G_lppb,
+    PK_TRACE_DBG("PSTATE: Hdr=0x%x, LPPB=0x%x, Nominal_Freq_Mhz=%d ", (uint32_t)G_cmeHeader, (uint32_t)G_lppb,
                  G_lppb->operating_points[NOMINAL].frequency_mhz);
 
     // Pre-compute the value to be used as the SPURR reference during CME Boot and
@@ -848,7 +848,7 @@ inline void p9_cme_pstate_register()
 
         if(register_enable)
         {
-            PK_TRACE_INF("PSTATE: DB0 Processing is Enabled");
+            PK_TRACE_DBG("PSTATE: DB0 Processing is Enabled");
 
             //PGPE sends MSGID_DB0_REGISTER_DONE, if Pstates aren't active anymore.
             //Otherwise, PGPE sends DB0 in the following order
@@ -899,7 +899,7 @@ inline void p9_cme_pstate_register()
     {
         if (register_enable)
         {
-            PK_TRACE_INF("PSTATE: Wait on Pstate Start");
+            PK_TRACE_DBG("PSTATE: Wait on Pstate Start");
 
             //PGPE sends MSGID_DB0_REGISTER_DONE, if Pstates aren't active anymore.
             //Otherwise, PGPE sends DB0 in the following order
@@ -1109,7 +1109,7 @@ inline void p9_cme_pstate_db0_pmsr_updt()
 
 void p9_cme_pstate_notify_sib(INTERCME_DIRECT_INTF intf)
 {
-    PK_TRACE_INF("PSTATE: Notify Enter");
+    PK_TRACE_INF("PSTATE: Notify");
 
     //Notify sibling CME(if any)
     if(G_cme_pstate_record.siblingCMEFlag)
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index 70ed76c6..48111d1d 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -293,7 +293,7 @@ p9_cme_stop_entry()
     if (!core)
     {
         // PM_ACTIVE can be phantom, only gives warning
-        PK_TRACE_INF("WARNING: Only Phantom PM_ACTIVE to be Ignored. Return");
+        //PK_TRACE_INF("WARNING: Only Phantom PM_ACTIVE to be Ignored. Return");
         return;
     }
 
@@ -304,7 +304,7 @@ p9_cme_stop_entry()
     if (((core & CME_MASK_C0) && (in32(G_CME_LCL_SISR)    & BITS32(13, 2))) ||
         ((core & CME_MASK_C1) && (in32_sh(CME_LCL_SISR) & BITS64SH(61, 2))))
     {
-        PK_TRACE_INF("WARNING: Attn/Recov Present, Abort Entry and Return");
+        //PK_TRACE_INF("WARNING: Attn/Recov Present, Abort Entry and Return");
         return;
     }
 
@@ -432,7 +432,7 @@ p9_cme_stop_entry()
 
             if (!core)
             {
-                PK_TRACE_INF("WARNING: STOP1 PM_ACTIVE to be Ignored. Return");
+                //PK_TRACE_INF("WARNING: STOP1 PM_ACTIVE to be Ignored. Return");
                 return;
             }
 
@@ -678,13 +678,13 @@ p9_cme_stop_entry()
             if (core & CME_MASK_C0)
             {
                 CME_GETSCOM(RAS_STATUS, CME_MASK_C0, scom_data.value);
-                PKTRACE("CheckA RAS_STATUS_UPPER Core0 %X", scom_data.words.upper);
+                //PKTRACE("CheckA RAS_STATUS_UPPER Core0 %X", scom_data.words.upper);
             }
 
             if (core & CME_MASK_C1)
             {
                 CME_GETSCOM(RAS_STATUS, CME_MASK_C1, scom_data.value);
-                PKTRACE("CheckA RAS_STATUS_UPPER Core1 %X", scom_data.words.upper);
+                //PKTRACE("CheckA RAS_STATUS_UPPER Core1 %X", scom_data.words.upper);
             }
 
 #endif
@@ -701,7 +701,7 @@ p9_cme_stop_entry()
 
                 CME_GETSCOM_AND(RAS_STATUS, core, scom_data.value);
 #ifdef PLS_DEBUG
-                PKTRACE("CheckB RAS_STATUS_AND_UPPER %X", scom_data.words.upper);
+                //PKTRACE("CheckB RAS_STATUS_AND_UPPER %X", scom_data.words.upper);
 #endif
             }
             while((scom_data.words.upper & (BIT32(1) | BIT32(3) | BIT32(9) | BIT32(11) | BIT32(17) | BIT32(19) | BIT32(25) | BIT32(
@@ -715,7 +715,7 @@ p9_cme_stop_entry()
 
                 CME_GETSCOM_OR(RAS_STATUS, core, scom_data.value);
 #ifdef PLS_DEBUG
-                PKTRACE("CheckC RAS_STATUS_OR_LOWER[0] %X", scom_data.words.lower);
+                //PKTRACE("CheckC RAS_STATUS_OR_LOWER[0] %X", scom_data.words.lower);
 #endif
             }
             while(scom_data.words.lower & BIT32(0));
@@ -727,7 +727,7 @@ p9_cme_stop_entry()
 
                 CME_GETSCOM_OR(THREAD_INFO, core, scom_data.value);
 #ifdef PLS_DEBUG
-                PKTRACE("CheckD THREAD_INFO_OR_UPPER[23] %X", scom_data.words.upper);
+                //PKTRACE("CheckD THREAD_INFO_OR_UPPER[23] %X", scom_data.words.upper);
 #endif
             }
             while(scom_data.words.upper & BIT32(23));
@@ -739,13 +739,13 @@ p9_cme_stop_entry()
             if (core & CME_MASK_C0)
             {
                 CME_GETSCOM(THREAD_INFO, CME_MASK_C0, scom_data.value);
-                PKTRACE("CheckE THREAD_INFO_UPPER[0:3] Core0 %X", scom_data.words.upper);
+                //PKTRACE("CheckE THREAD_INFO_UPPER[0:3] Core0 %X", scom_data.words.upper);
             }
 
             if (core & CME_MASK_C1)
             {
                 CME_GETSCOM(THREAD_INFO, CME_MASK_C1, scom_data.value);
-                PKTRACE("CheckE THREAD_INFO_UPPER[0:3] Core1 %X", scom_data.words.upper);
+                //PKTRACE("CheckE THREAD_INFO_UPPER[0:3] Core1 %X", scom_data.words.upper);
             }
 
             PK_TRACE("RAMMING Read CORE_THREAD_STATE[56:59] to find out which threads are stopped");
@@ -753,13 +753,13 @@ p9_cme_stop_entry()
             if (core & CME_MASK_C0)
             {
                 CME_GETSCOM(CORE_THREAD_STATE, CME_MASK_C0, scom_data.value);
-                PKTRACE("CheckF CORE_THREAD_STATE[56:59] Core0 %X %X", scom_data.words.upper, scom_data.words.lower);
+                //PKTRACE("CheckF CORE_THREAD_STATE[56:59] Core0 %X %X", scom_data.words.upper, scom_data.words.lower);
             }
 
             if (core & CME_MASK_C1)
             {
                 CME_GETSCOM(CORE_THREAD_STATE, CME_MASK_C1, scom_data.value);
-                PKTRACE("CheckF CORE_THREAD_STATE[56:59] Core1 %X %X", scom_data.words.upper, scom_data.words.lower);
+                //PKTRACE("CheckF CORE_THREAD_STATE[56:59] Core1 %X %X", scom_data.words.upper, scom_data.words.lower);
             }
 
 #endif
@@ -772,7 +772,7 @@ p9_cme_stop_entry()
 
                 CME_GETSCOM_AND(THREAD_INFO, core, scom_data.value);
 #ifdef PLS_DEBUG
-                PKTRACE("CheckG THREAD_INFO_AND_UPPER[0:3] %X", scom_data.words.upper);
+                //PKTRACE("CheckG THREAD_INFO_AND_UPPER[0:3] %X", scom_data.words.upper);
 #endif
             }
             while((scom_data.words.upper & BITS32(0, 4)) != BITS32(0, 4));
@@ -841,8 +841,9 @@ p9_cme_stop_entry()
                         }
 
 #ifdef PLS_DEBUG
-                        PKTRACE("cXtX PSSCR %X %X G_pls %x core %d",
-                                scom_data.words.upper, scom_data.words.lower, G_pls[core_mask & 1][thread], core);
+                        /*                        PKTRACE("cXtX PSSCR %X %X G_pls %x core %d",
+                                                        scom_data.words.upper, scom_data.words.lower, G_pls[core_mask & 1][thread], core);
+                        */
 #endif
 
                     }
@@ -862,7 +863,7 @@ p9_cme_stop_entry()
             if (core & CME_MASK_C0)
             {
 #ifdef PLS_DEBUG
-                PKTRACE("SCRATCH1 %x %x", (G_scratch[0] >> 32), (G_scratch[0] & 0xffffffff));
+                //PKTRACE("SCRATCH1 %x %x", (G_scratch[0] >> 32), (G_scratch[0] & 0xffffffff));
 #endif
                 CME_PUTSCOM(SCRATCH1, CME_MASK_C0, G_scratch[0]);
             }
@@ -870,7 +871,7 @@ p9_cme_stop_entry()
             if (core & CME_MASK_C1)
             {
 #ifdef PLS_DEBUG
-                PKTRACE("SCRATCH1 %x %x", (G_scratch[1] >> 32), (G_scratch[1] & 0xffffffff));
+                //PKTRACE("SCRATCH1 %x %x", (G_scratch[1] >> 32), (G_scratch[1] & 0xffffffff));
 #endif
                 CME_PUTSCOM(SCRATCH1, CME_MASK_C1, G_scratch[1]);
             }
@@ -1383,13 +1384,13 @@ p9_cme_stop_entry()
 
             if ((core & CME_MASK_C0) && (in32(G_CME_LCL_SISR) & BITS32(12, 4)))
             {
-                PK_TRACE_INF("WARNING: Core0 Xstop/Attn/Recov Present, Abort Entry");
+                //PK_TRACE_INF("WARNING: Core0 Xstop/Attn/Recov Present, Abort Entry");
                 core -= CME_MASK_C0;
             }
 
             if ((core & CME_MASK_C1) && (in32_sh(CME_LCL_SISR) & BITS64SH(60, 4)))
             {
-                PK_TRACE_INF("WARNING: Core1 Xstop/Attn/Recov Present, Abort Entry");
+                //PK_TRACE_INF("WARNING: Core1 Xstop/Attn/Recov Present, Abort Entry");
                 core -= CME_MASK_C1;
             }
 
@@ -1599,7 +1600,7 @@ p9_cme_stop_entry()
                             MARK_TAG(SE_PURGE_L2_ABORT, core_aborted)
                             //=======================================
 
-                            PK_TRACE_INF("Abort: L2+NCU purge aborted by core[%d]", core_aborted);
+                            //PK_TRACE_INF("Abort: L2+NCU purge aborted by core[%d]", core_aborted);
                             out32(G_CME_LCL_SICR_OR, BIT32(19) | BIT32(23));
                         }
                     }
@@ -1645,7 +1646,7 @@ p9_cme_stop_entry()
 
             if (G_cme_record.disableSGPEHandoff)
             {
-                PK_TRACE_INF("SE.4+: Disable SGPE Handoff due to SGPE Halt");
+                //PK_TRACE_INF("SE.4+: Disable SGPE Handoff due to SGPE Halt");
                 break;
             }
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
index b83624ec..e16f4fc8 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
@@ -661,7 +661,7 @@ p9_cme_stop_exit()
 
         if (core_stop1)
         {
-            PK_TRACE_INF("SX.1A: Core[%d] Requested Stop1 Exit", core_stop1);
+            //PK_TRACE_INF("SX.1A: Core[%d] Requested Stop1 Exit", core_stop1);
             p9_cme_stop_exit_end(core_stop1, spwu_stop);
 
             core = core - core_stop1;
@@ -1297,7 +1297,7 @@ p9_cme_stop_self_execute(uint32_t core, uint32_t i_saveRestore )
 
             if (scom_data.words.upper & BIT32(8))
             {
-                PK_TRACE_INF("WARNING: Injecting a core[%d] xstop via C_LFIR[11]", core);
+                //PK_TRACE_INF("WARNING: Injecting a core[%d] xstop via C_LFIR[11]", core);
                 CME_PUTSCOM(C_LFIR_OR, core_mask, BIT64(11));
             }
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
index 12f353b3..7f82bb8d 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HCODE Project                                                */
 /*                                                                        */
-/* COPYRIGHT 2015,2018                                                    */
+/* COPYRIGHT 2015,2019                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -83,7 +83,7 @@ p9_cme_stop_pcwu_handler(void)
     // if still wakeup for core with notify_select == cme, go exit
     if (core)
     {
-        PK_TRACE_INF("PCWU Launching exit thread");
+        //PK_TRACE_INF("PCWU Launching exit thread");
 
         out32(G_CME_LCL_EIMR_OR, BITS32(12, 10));
         g_eimr_override |= BITS64(12, 10);
@@ -148,7 +148,7 @@ p9_cme_stop_spwu_handler(void)
                     }
                 }
 
-                PK_TRACE_INF("Falling edge of SPWU, now clear spwu_done, eisr and flip eipr");
+                //PK_TRACE_INF("Falling edge of SPWU, now clear spwu_done, eisr and flip eipr");
                 out32(G_CME_LCL_SICR_CLR, BIT32((16 + core_index)));
                 out32(G_CME_LCL_EISR_CLR, BIT32((14 + core_index)));
                 out32(G_CME_LCL_EIPR_OR,  BIT32((14 + core_index)));
@@ -159,7 +159,7 @@ p9_cme_stop_spwu_handler(void)
                     out32(G_CME_LCL_EISR_CLR, BIT32((14 + core_index)));
                     out32(G_CME_LCL_EIPR_CLR, BIT32((14 + core_index)));
                     out32(G_CME_LCL_SICR_OR,  BIT32((16 + core_index)));
-                    PK_TRACE_INF("SPWU asserts again, clear eisr, flip eipr, re-assert spwu_done");
+                    //PK_TRACE_INF("SPWU asserts again, clear eisr, flip eipr, re-assert spwu_done");
                 }
                 // if spwu truly dropped:
                 else
@@ -192,7 +192,7 @@ p9_cme_stop_spwu_handler(void)
 
     if (spwu_rise)
     {
-        PK_TRACE_INF("SPWU Launching exit thread");
+        //PK_TRACE_INF("SPWU Launching exit thread");
 
         out32(G_CME_LCL_EIMR_OR, BITS32(12, 10));
         g_eimr_override |= BITS64(12, 10);
@@ -218,7 +218,7 @@ void
 p9_cme_stop_rgwu_handler(void)
 {
     MARK_TRAP(STOP_RGWU_HANDLER)
-    PK_TRACE_INF("RGWU Handler Trigger");
+    //PK_TRACE_INF("RGWU Handler Trigger");
 
     out32(G_CME_LCL_EIMR_OR, BITS32(12, 10));
     g_eimr_override |= BITS64(12, 10);
@@ -244,7 +244,7 @@ void
 p9_cme_stop_enter_handler(void)
 {
     MARK_TRAP(STOP_ENTER_HANDLER)
-    PK_TRACE_INF("PM_ACTIVE Handler Trigger");
+    //PK_TRACE_INF("PM_ACTIVE Handler Trigger");
 
     // Abort Protection
     out32(G_CME_LCL_EIMR_OR, BITS32(12, 10));
@@ -373,7 +373,7 @@ p9_cme_stop_db1_handler(void)
     uint32_t         suspend_ack = 0;
 
     MARK_TRAP(STOP_DB1_HANDLER)
-    PK_TRACE_INF("DB1 Handler Trigger");
+    //PK_TRACE_INF("DB1 Handler Trigger");
 
     // Suspend DB should only come from the first good core
     core = G_cme_pstate_record.firstGoodCoreMask;