PGPE: Use PGPE Header from p9_hcode_images_defines.h

     Key_Cronus_Test=PM_REGRESS

Change-Id: Ie72b0d588b4da9eadf93625227a3d0cd519e9e6e
CQ: SW421711
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56043
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

8 files changed, 64 insertions, 94 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h
index 3a92f8bb..202bc115 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h
@@ -54,6 +54,8 @@
 #include "pstate_pgpe_cme_api.h"
 #include "p9_hcd_memmap_base.H"
 #include "p9_pm_hcd_flags.h"
+#include "p9_hcode_image_defines.H"
+#include "p9_hcd_memmap_occ_sram.H"
 #include "ipc_api.h"
 #include "ipc_async_cmd.h"
 
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
index 5d2062bc..ca5fbd61 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
@@ -122,8 +122,8 @@ __attribute__((always_inline)) inline void handle_core_throttle()
         uint32_t inject = run & 0x1; //Inject is bit 17, if this is high we run one throttle burst then turn off
         uint32_t type = (config >> 13) & 0x1; //type is bit 18, this determines which kind of throttling we do
         uint32_t mask = type ? CORE_SLOWDOWN : CORE_IFU_THROTTLE;
-        uint32_t pgpe_throttle_assert   = G_pgpe_header_data->g_pgpe_throttle_assert;
-        uint32_t pgpe_throttle_deassert = G_pgpe_header_data->g_pgpe_throttle_deassert;
+        uint32_t pgpe_throttle_assert   = G_pgpe_header_data->g_pgpe_core_throttle_assert_cnt;
+        uint32_t pgpe_throttle_deassert = G_pgpe_header_data->g_pgpe_core_throttle_deassert_cnt;
 
         //if currently off, we don't desire always off, this is the first evaluation since become enabled, we are in always on,
         //or we (re enabled and have reached the count, then we turn throttling on (if both assert and deassert are 0 this statement fails)
@@ -195,7 +195,7 @@ __attribute__((always_inline)) inline void handle_occ_beacon()
         if (G_pgpe_pstate_record.updatePGPEBeacon == 1)
         {
             //write to SRAM
-            *(G_pgpe_header_data->g_pgpe_beacon_addr) = *(G_pgpe_header_data->g_pgpe_beacon_addr) + 1;
+            *((uint32_t*)(G_pgpe_header_data->g_pgpe_beacon_addr)) = *((uint32_t*)(G_pgpe_header_data->g_pgpe_beacon_addr)) + 1;
             G_beacon_count = 0;
         }
     }
@@ -310,7 +310,7 @@ __attribute__((always_inline)) inline void handle_fit_timebase_sync()
         }
         else
         {
-            G_pgpe_optrace_data.word[0] = *(G_pgpe_header_data->g_pgpe_beacon_addr);
+            G_pgpe_optrace_data.word[0] = *((uint32_t*)(G_pgpe_header_data->g_pgpe_beacon_addr));
             p9_pgpe_optrace(FIT_TB_SYNC);
             G_last_sync_op = 1;
         }
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
index 04d0306c..c3c99cdd 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
@@ -26,7 +26,7 @@
 #include "p9_pstates_pgpe.h"
 #include "p9_pstates_table.h"
 #include "p9_pgpe_gppb.h"
-#include "p9_pgpe_header.h"
+#include "p9_hcode_image_defines.H"
 #include "pstate_pgpe_occ_api.h"
 #include "p9_pgpe.h"
 
@@ -89,14 +89,17 @@ void p9_pgpe_gen_pstate_info()
     PK_TRACE_DBG("INIT:highest_ps=0x%x, biased_ps=0x%x",
                  G_gpi->header.highest_ps_offset,
                  G_gpi->header.biased_pstate_tbl_offset);
-    gppb = (GlobalPstateParmBlock*)((G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.gppb_offset));
-    ps0 = (uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.ps0_offset);
-    highest_pstate = (uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.highest_ps_offset);
-    rTbl = (PstateTable*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.raw_pstate_tbl_offset);
-    bTbl = (PstateTable*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.biased_pstate_tbl_offset);
-    PK_TRACE_DBG("INIT:highest_ps=0x%x, ps0=0x%x",
-                 *highest_pstate,
-                 *ps0);
+    gppb = (GlobalPstateParmBlock*)((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) +
+                                    G_gpi->header.gppb_offset));
+    ps0 = ((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) + G_gpi->header.ps0_offset);
+    highest_pstate = ((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) + G_gpi->header.highest_ps_offset);
+    rTbl = (PstateTable*)((uint32_t*)(G_(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) +
+                                      G_gpi->header.raw_pstate_tbl_offset);
+           bTbl = (PstateTable*)(((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) +
+                                  G_gpi->header.biased_pstate_tbl_offset);
+                                 PK_TRACE_DBG("INIT:highest_ps=0x%x, ps0=0x%x",
+                                         *highest_pstate,
+                                         *ps0);
 #elif USE_GEN_PSTATE_STRUCT_V == 2
     G_gpi = (GeneratedPstateInfo_v2*)G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset;
     G_gpi->magic = GEN_PSTATES_TBL_MAGIC_V2;
@@ -120,12 +123,15 @@ void p9_pgpe_gen_pstate_info()
     PK_TRACE_DBG("INIT:vratio_vindex ofsset=0x%x,length=0x%x ",
                  G_gpi->header.vratio_vindex_tbl_offset,
                  G_gpi->header.vratio_vindex_tbl_length);
-    gppb = (GlobalPstateParmBlock*)((G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.gppb_offset));
-    ps0 = (uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.ps0_offset);
-    highest_pstate = (uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.highest_ps_offset);
-    rTbl = (PstateTable*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.raw_pstate_tbl_offset);
-    bTbl = (PstateTable*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset + G_gpi->header.biased_pstate_tbl_offset);
-    VRatioVIndexTable* vTbl = (VRatioVIndexTable*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset +
+    gppb = (GlobalPstateParmBlock*)((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) +
+                                    G_gpi->header.gppb_offset);
+    ps0 = (((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset)) + G_gpi->header.ps0_offset);
+    highest_pstate = ((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) + G_gpi->header.highest_ps_offset);
+    rTbl = (PstateTable*)((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) +
+                          G_gpi->header.raw_pstate_tbl_offset);
+    bTbl = (PstateTable*)((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) +
+                          G_gpi->header.biased_pstate_tbl_offset);
+    VRatioVIndexTable* vTbl = (VRatioVIndexTable*)((uint32_t*)(G_pgpe_header_data->g_pgpe_gen_pstables_mem_offset) +
                               G_gpi->header.vratio_vindex_tbl_offset);
     PK_TRACE_DBG("INIT:highest_ps=0x%x, ps0=0x%x",
                  *highest_pstate,
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c
index 03db491e..058229af 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HCODE Project                                                */
 /*                                                                        */
-/* COPYRIGHT 2016,2017                                                    */
+/* COPYRIGHT 2016,2018                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -25,6 +25,7 @@
 
 #include "p9_pgpe_gppb.h"
 #include "p9_pgpe_header.h"
+#include "p9_hcode_image_defines.H"
 
 //Globals and externs
 GlobalPstateParmBlock* G_gppb;//Global pointer to GlobalPstateParmBlock
@@ -45,7 +46,7 @@ uint8_t p9_pgpe_gppb_get_ps_region(Pstate ps, uint8_t vpt_pt_set);
 //
 void p9_pgpe_gppb_init()
 {
-    void* gppb_sram_offset = G_pgpe_header_data->g_pgpe_gppb_sram_addr;//GPPB Sram Offset
+    void* gppb_sram_offset = (void*)G_pgpe_header_data->g_pgpe_gppb_sram_addr;//GPPB Sram Offset
     G_gppb = (GlobalPstateParmBlock*)gppb_sram_offset;
 
     PK_TRACE_INF("INIT: DPLL0Value=0x%x", G_gppb->dpll_pstate0_value);
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c
index 3c729e4f..3c0f5bdf 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HCODE Project                                                */
 /*                                                                        */
-/* COPYRIGHT 2016,2017                                                    */
+/* COPYRIGHT 2016,2018                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -24,15 +24,12 @@
 /* IBM_PROLOG_END_TAG                                                     */
 #include "p9_pgpe_header.h"
 #include "pstate_pgpe_occ_api.h"
-
-// @todo The PGPE start and the length needs to come from the occ_sram_layout.h
-#define OCC_PGPE_SRAM_ADDR_START 0xfff20000
-#define OCC_PGPE_SRAM_SIZE       0xC000      // 48KB
+#include "p9_hcode_image_defines.H"
+#include "p9_hcd_memmap_base.H"
 
 //OCC Shared SRAM starts at bottom 2K of PGPE OCC SRAM space
-#define OCC_SHARED_SRAM_ADDR_LENGTH 2*1024
 #define OCC_SHARED_SRAM_ADDR_START \
-    (OCC_PGPE_SRAM_ADDR_START + OCC_PGPE_SRAM_SIZE - OCC_SHARED_SRAM_ADDR_LENGTH)
+    (OCC_SRAM_PGPE_BASE_ADDR + OCC_SRAM_PGPE_REGION_SIZE - PGPE_OCC_SHARED_SRAM_SIZE)
 
 PgpeHeader_t* G_pgpe_header_data;
 extern PgpeHeader_t* _PGPE_IMG_HEADER __attribute__ ((section (".pgpe_image_header")));
@@ -52,30 +49,31 @@ void p9_pgpe_header_init()
                                             OCC_SHARED_SRAM_ADDR_START; //Bottom 2K of PGPE OCC Sram Space
 
     //OCC Shared SRAM address and length
-    G_pgpe_header_data->g_pgpe_shared_sram_addr = (uint32_t*)OCC_SHARED_SRAM_ADDR_START;
-    G_pgpe_header_data->g_pgpe_shared_sram_len = OCC_SHARED_SRAM_ADDR_LENGTH;
+    G_pgpe_header_data->g_pgpe_shared_sram_addr = (uint32_t)OCC_SHARED_SRAM_ADDR_START;
+    G_pgpe_header_data->g_pgpe_shared_sram_len = PGPE_OCC_SHARED_SRAM_SIZE;
 
     //OCC Pstate Tables SRAM address and length
     uint64_t* occ_shared_data_indx = (uint64_t*)OCC_SHARED_SRAM_ADDR_START;
 
-    for (i = 0; i < OCC_SHARED_SRAM_ADDR_LENGTH / sizeof(uint64_t); ++i)
+    for (i = 0; i < PGPE_OCC_SHARED_SRAM_SIZE / sizeof(uint64_t); ++i)
     {
         *occ_shared_data_indx = 0;
         occ_shared_data_indx++;
     }
 
-    G_pgpe_header_data->g_pgpe_occ_pstables_sram_addr = (uint32_t*)
+    G_pgpe_header_data->g_pgpe_occ_pstables_sram_addr = (uint32_t)
             &occ_shared_data->pstate_table; //OCC Pstate table address
     G_pgpe_header_data->g_pgpe_occ_pstables_len  = sizeof(OCCPstateTable_t); //OCC Pstate table length
 
-    G_pgpe_header_data->g_pgpe_beacon_addr = (uint32_t*)&occ_shared_data->pgpe_beacon;//Beacon
-    G_pgpe_header_data->g_quad_status_addr = (uint32_t*)&occ_shared_data->quad_pstate_0;//Quad Pstate
+    G_pgpe_header_data->g_pgpe_beacon_addr = (uint32_t)&occ_shared_data->pgpe_beacon;//Beacon
+    G_pgpe_header_data->g_quad_status_addr = (uint32_t)&occ_shared_data->quad_pstate_0;//Quad Pstate
 
     //GPPB Sram Offset
-    G_pgpe_header_data->g_pgpe_gppb_sram_addr = (uint32_t*)(OCC_PGPE_SRAM_ADDR_START +
+    G_pgpe_header_data->g_pgpe_gppb_sram_addr = (uint32_t)(OCC_SRAM_PGPE_BASE_ADDR +
             G_pgpe_header_data->g_pgpe_hcode_length);
 
-    G_pgpe_header_data->g_pgpe_wof_state_addr = (uint32_t*)&occ_shared_data->pgpe_wof_state;//Wof State
-    G_pgpe_header_data->g_req_active_quad_addr = (uint32_t*)&occ_shared_data->req_active_quads;//Requested Active Quads
+    G_pgpe_header_data->g_pgpe_wof_state_address = (uint32_t)&occ_shared_data->pgpe_wof_state;//Wof State
+    G_pgpe_header_data->g_pgpe_req_active_quad_address = (uint32_t)
+            &occ_shared_data->req_active_quads;//Requested Active Quads
 
 }
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.h
index 4b02608f..efde1b33 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_header.h
@@ -27,43 +27,6 @@
 
 #include "pk.h"
 
-
-//
-//\todo RTC: 164335 Use the structure from p9_hcode_image_defines.H
-//when it's updated
-typedef struct
-{
-    uint32_t  g_pgpe_magic_number[2];         // PGPE_1.0
-    uint32_t* g_pgpe_sys_reset_addr;          // Fully qualified OCC address where pk_init resides
-    uint32_t* g_pgpe_shared_sram_addr;        // SRAM address where shared SRAM begins
-    uint32_t* g_pgpe_ivpr_addr;               // Beginning of PGPE region in OCC SRAM
-    uint32_t  g_pgpe_shared_sram_len;         // Length of shared SRAM area
-    uint32_t  g_pgpe_build_date;              // Build date for PGPE Image
-    uint32_t  g_pgpe_build_ver;               // Build Version
-    uint16_t  g_pgpe_qm_flags;                // QM Flags
-    uint16_t  g_pgpe_reserve1;                // Reserve field
-    uint32_t  g_pgpe_timebase_hz;             // Reserve field
-    uint32_t* g_pgpe_gppb_sram_addr;          // Offset to Global P State Parameter Block
-    uint32_t  g_pgpe_hcode_length;            // Length of PGPE Hcode
-    uint32_t* g_pgpe_gppb_mem_offset;         // Offset to start of Global PS Param Block wrt start of HOMER.
-    uint32_t  g_pgpe_gppb_length;             // Length of Global P State Parameter Block
-    uint32_t* g_pgpe_gen_pstables_mem_offset; // Offset to PState Table wrt start of HOMER
-    uint32_t  g_pgpe_gen_pstables_length;     // Length of P State table
-    uint32_t* g_pgpe_occ_pstables_sram_addr;  // Offset to start of OCC P-State table
-    uint32_t  g_pgpe_occ_pstables_len;        // Length of OCC P-State table
-    uint32_t* g_pgpe_beacon_addr;             // SRAM addr where PGPE beacon is located
-    uint32_t* g_quad_status_addr;             // Actual Quad address
-    uint32_t* g_pgpe_wof_state_addr;          //
-    uint32_t* g_req_active_quad_addr;         //Requested Active Quads Address
-    uint32_t* g_wof_table_addr;               // WOF Table Address
-    uint32_t  g_wof_table_length;             // WOF Table Length
-    uint32_t  g_pgpe_throttle_assert;
-    uint32_t  g_pgpe_throttle_deassert;
-    uint32_t  g_pgpe_aux_controls;
-    uint32_t  g_pgpe_doptrace_offset;         //Offset from PBABAR that Deep Operational Trace written into
-    uint32_t  g_pgpe_doptrace_length;         //Size in bytes of Deep Operational Trace memory region
-} PgpeHeader_t;
-
 void p9_pgpe_header_init();
 
 #endif //_P9_PGPE_HEADER_H_
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
index 37c54705..63099099 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
@@ -119,8 +119,8 @@ void p9_pgpe_pstate_init()
 
     //Init OCC Shared SRAM
     G_pgpe_pstate_record.pQuadState0 = (quad_state0_t*)G_pgpe_header_data->g_quad_status_addr;
-    G_pgpe_pstate_record.pQuadState1 = (quad_state1_t*)(G_pgpe_header_data->g_quad_status_addr + 2);
-    G_pgpe_pstate_record.pReqActQuads = (requested_active_quads_t*)(G_pgpe_header_data->g_req_active_quad_addr);
+    G_pgpe_pstate_record.pQuadState1 = (quad_state1_t*)(G_pgpe_header_data->g_quad_status_addr + 8);
+    G_pgpe_pstate_record.pReqActQuads = (requested_active_quads_t*)(G_pgpe_header_data->g_pgpe_req_active_quad_address);
     G_pgpe_pstate_record.pQuadState0->fields.quad0_pstate = 0xff;
     G_pgpe_pstate_record.pQuadState0->fields.quad1_pstate = 0xff;
     G_pgpe_pstate_record.pQuadState0->fields.quad2_pstate = 0xff;
@@ -350,7 +350,7 @@ void p9_pgpe_pstate_calc_wof()
 
     //2. Vratio calc and VFRT table lookup
     //Currently, PGPE only support VRATIO Fixed and VRATIO active cores only
-    if (G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_ENABLE_VRATIO)
+    if (G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_ENABLE_VRATIO)
     {
         G_pgpe_pstate_record.vratio = (G_pgpe_pstate_record.numActiveCores * MAX_VRATIO) / (G_pgpe_pstate_record.numSortCores);
 
@@ -394,7 +394,7 @@ void p9_pgpe_pstate_calc_wof()
 void p9_pgpe_pstate_update_wof_state()
 {
     PK_TRACE_DBG("WFU: Updt WOF Shr Sram");
-    pgpe_wof_state_t* wof_state = (pgpe_wof_state_t*)G_pgpe_header_data->g_pgpe_wof_state_addr;
+    pgpe_wof_state_t* wof_state = (pgpe_wof_state_t*)G_pgpe_header_data->g_pgpe_wof_state_address;
     wof_state->fields.fclip_ps = G_pgpe_pstate_record.wofClip;
     wof_state->fields.vclip_mv = G_pgpe_pstate_record.eVidCurr;
     wof_state->fields.fratio = G_pgpe_pstate_record.fratio;
@@ -1121,8 +1121,8 @@ void p9_pgpe_pstate_wof_ctrl(uint32_t action)
     if (action == PGPE_ACTION_WOF_ON)
     {
         //In WOF Phase >= 2, we ask SGPE to start sending active core updates
-        if ((G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_ENABLE_VRATIO) ||
-            (G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_VRATIO_MODIFIER))
+        if ((G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_ENABLE_VRATIO) ||
+            (G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_VRATIO_MODIFIER))
         {
             p9_pgpe_pstate_send_ctrl_stop_updt(CTRL_STOP_UPDT_ENABLE_CORE);
             activeCores = G_sgpe_control_updt.fields.active_cores << 8;
@@ -1164,8 +1164,8 @@ void p9_pgpe_pstate_wof_ctrl(uint32_t action)
     {
         //In WOF Phase >= 2, we take a note that WOF has been disabled, and
         //simply ACK any active cores updates that come from SGPE.
-        if ((G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_ENABLE_VRATIO) ||
-            (G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_VRATIO_MODIFIER))
+        if ((G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_ENABLE_VRATIO) ||
+            (G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_VRATIO_MODIFIER))
         {
             G_pgpe_pstate_record.activeCoreUpdtAction = ACTIVE_CORE_UPDATE_ACTION_ACK_ONLY;
         }
@@ -1300,7 +1300,7 @@ void p9_pgpe_pstate_process_quad_exit_notify(uint32_t quadsRequested)
                 //Otherwise, just write the VDM register
                 vdmcfg.value = 0;
 
-                if (G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_VDM_ENABLE)
+                if (G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_VDM_ENABLE)
                 {
                     GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(QPPM_VDMCFGR, q), vdmcfg.value);
                 }
@@ -1905,7 +1905,7 @@ void p9_pgpe_pstate_updt_ext_volt(uint32_t tgtEVid)
     G_pgpe_pstate_record.eVidCurr = G_pgpe_pstate_record.eVidNext;
 
     //If VDM is disabled, update VDMCFG register for every quad
-    if (!(G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_VDM_ENABLE))
+    if (!(G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_VDM_ENABLE))
     {
         vdmcfg.value = 0;
         vdmcfg.fields.vdm_vid_compare = (G_pgpe_pstate_record.eVidCurr - 512) >> 2;
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
index c68ad583..c3ae7321 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c
@@ -78,9 +78,9 @@ void p9_pgpe_thread_process_requests(void* arg)
     // 10 - WOF Phase3(Vratio Full, Fratio Fixed)
     // 11 - WOF Phase4(Vratio Full, Fratio Full)
     // Currently, only Phase 1 and 2 are supported.
-    if ((G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_ENABLE_VRATIO) ||
-        (G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_VRATIO_MODIFIER) ||
-        (G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_ENABLE_FRATIO))
+    if ((G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_ENABLE_VRATIO) ||
+        (G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_VRATIO_MODIFIER) ||
+        (G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_ENABLE_FRATIO))
     {
         out32(OCB_OCCFLG_OR, BIT32(29));
     }
@@ -425,7 +425,7 @@ inline void p9_pgpe_process_start_stop()
     ipc_async_cmd_t* async_cmd = (ipc_async_cmd_t*)G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_PSTATE_START_STOP].cmd;
     ipcmsg_start_stop_t* args = (ipcmsg_start_stop_t*)async_cmd->cmd_data;
 
-    if(G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_OCC_IPC_IMMEDIATE_MODE)
+    if(G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_OCC_IPC_IMMEDIATE_MODE)
     {
         PK_TRACE_DBG("START_STOP: Imm");
         args->msg_cb.rc = PGPE_RC_SUCCESS;
@@ -554,7 +554,7 @@ inline void p9_pgpe_process_clip_updt()
 
     G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_CLIP_UPDT].pending_processing = 0;
 
-    if(G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_OCC_IPC_IMMEDIATE_MODE)
+    if(G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_OCC_IPC_IMMEDIATE_MODE)
     {
         PK_TRACE_DBG("PTH: Clip Updt Imme");
         args->msg_cb.rc = PGPE_RC_SUCCESS;
@@ -679,8 +679,8 @@ inline void p9_pgpe_process_wof_ctrl()
 
     G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_WOF_CTRL].pending_processing = 0;
 
-    if((G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_OCC_IPC_IMMEDIATE_MODE) ||
-       (G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_WOF_IPC_IMMEDIATE_MODE))
+    if((G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_OCC_IPC_IMMEDIATE_MODE) ||
+       (G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_WOF_IPC_IMMEDIATE_MODE))
     {
         PK_TRACE_DBG("PTH: WOF Ctrl Imme");
         args->msg_cb.rc = PGPE_RC_SUCCESS;
@@ -795,8 +795,8 @@ inline void p9_pgpe_process_wof_vfrt()
 
     G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_WOF_VFRT].pending_processing = 0;
 
-    if((G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_OCC_IPC_IMMEDIATE_MODE) ||
-       (G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_WOF_IPC_IMMEDIATE_MODE))
+    if((G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_OCC_IPC_IMMEDIATE_MODE) ||
+       (G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_WOF_IPC_IMMEDIATE_MODE))
     {
         PK_TRACE_DBG("PTH: WOF VFRT Imme");
         args->msg_cb.rc = PGPE_RC_SUCCESS;
@@ -893,7 +893,7 @@ inline void p9_pgpe_process_set_pmcr_req()
 
     G_pgpe_pstate_record.ipcPendTbl[IPC_PEND_SET_PMCR_REQ].pending_processing = 0;
 
-    if(G_pgpe_header_data->g_pgpe_qm_flags & PGPE_FLAG_OCC_IPC_IMMEDIATE_MODE)
+    if(G_pgpe_header_data->g_pgpe_flags & PGPE_FLAG_OCC_IPC_IMMEDIATE_MODE)
     {
         PK_TRACE_DBG("PTH: Set PMCR Imme");
         p9_pgpe_optrace(PRC_SET_PMCR);