PM: Add Fields in OCC Comp. Shr SRAM (1/4)

    1st commit in series of 4 commits which combined moves SGPE/PGPE
    SRAM regions, and also allows to do so easily in future.

    Commit 1(Hcode): Adds fields to OCC Complex Shared SRAM for storing SGPE
    and PGPE region addresses/size, image header and debug header.

    Commit 2(Hostboot): Moves around SGPE/PGPE regions, and adds fields
    to QPMR/PPMR for storing SGPE/PGPE region info

    Commit 3(Hcode): Populates the newly added SGPE/PGPE region info
    fields in QPMR/PPMR

    Commit 4(Hostboot): Adds check for QPMR and PPMR fields in the
    Hostboot Code

    Key_Cronus_Test=PM_REGRESS

Change-Id: Ie117a780d11bfb9f272a17300ba4f12d3926c758
CQ: SW447651
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67640
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

3 files changed, 15 insertions, 3 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
index 6c4c0b26..e53c1432 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
@@ -29,6 +29,9 @@
 #include "p9_pgpe_boot_temp.h"
 #include "p9_pgpe_pstate.h"
 #include "p9_pgpe_optrace.h"
+#include "occhw_shared_data.h"
+#include "p9_hcd_memmap_occ_sram.H"
+#include "p9_hcd_memmap_base.H"
 
 extern TraceData_t G_pgpe_optrace_data;
 
@@ -311,7 +314,9 @@ main(int argc, char** argv)
 
     p9_pgpe_optrace_init();
 
-    PK_TRACE_DBG("Start PK Threads");
+    OSD_PTR->occ_comp_shr_data.gpe2_data.gpe2_sram_region_start = OCC_SRAM_PGPE_BASE_ADDR;
+    OSD_PTR->occ_comp_shr_data.gpe2_data.gpe2_image_header_addr = OCC_SRAM_PGPE_BASE_ADDR + PGPE_HEADER_IMAGE_OFFSET;
+    OSD_PTR->occ_comp_shr_data.gpe2_data.gpe2_debug_header_addr = OCC_SRAM_PGPE_BASE_ADDR + SGPE_DEBUG_PTRS_OFFSET;
 
     // Start running the highest priority thread.
     // This function never returns
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
index 3f6a5ffe..560c4f25 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
@@ -781,7 +781,7 @@ void p9_pgpe_pstate_start(uint32_t pstate_start_origin)
         }
     }
 
-    PK_TRACE_INF("PST: LowestDPLL:0x%x DPLL_PS0=0x%x", lowestDpll, G_gppb->dpll_pstate0_value);
+    //PK_TRACE_INF("PST: LowestDPLL:0x%x DPLL_PS0=0x%x", lowestDpll, G_gppb->dpll_pstate0_value);
 
     //2. Determine Sync Pstate
     if (lowestDpll > G_gppb->dpll_pstate0_value)
@@ -898,7 +898,7 @@ void p9_pgpe_pstate_start(uint32_t pstate_start_origin)
         //to PMCR, and then switching the owner to CHAR which enables PCB_TYPE1 interrupts
         //and allows CME to forward Pstate Requests
         p9_pgpe_pstate_set_pmcr_owner(PMCR_OWNER_OCC);
-        PK_TRACE_INF("PST: OWNER_CHAR");
+        //PK_TRACE_INF("PST: OWNER_CHAR");
         G_pgpe_pstate_record.pmcrOwner = PMCR_OWNER_CHAR;
         g_oimr_override &= ~(BIT64(46));
         out32(G_OCB_OIMR1_CLR, BIT32(14)); //Enable PCB_INTR_TYPE1
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C
index 792ffbc9..dce81d17 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C
@@ -25,6 +25,9 @@
 
 #include "p9_sgpe_stop.h"
 #include <fapi2.H>
+#include "occhw_shared_data.h"
+#include "p9_hcd_memmap_occ_sram.H"
+#include "p9_hcd_memmap_base.H"
 
 
 //We define a global literal for these register addresses
@@ -251,6 +254,10 @@ main(int argc, char** argv)
     // Make G_p9_sgpe_stop_exit_thread runnable
     pk_thread_resume(&G_p9_sgpe_stop_exit_thread);
 
+    OSD_PTR->occ_comp_shr_data.gpe3_data.gpe3_sram_region_start = OCC_SRAM_SGPE_BASE_ADDR;
+    OSD_PTR->occ_comp_shr_data.gpe3_data.gpe3_image_header_addr = OCC_SRAM_SGPE_BASE_ADDR + SGPE_HEADER_IMAGE_OFFSET;
+    OSD_PTR->occ_comp_shr_data.gpe3_data.gpe3_debug_header_addr = OCC_SRAM_SGPE_BASE_ADDR + SGPE_DEBUG_PTRS_OFFSET;
+
     // Start running the highest priority thread.
     // This function never returns
     pk_start_threads();