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author | Greg Still <stillgs@us.ibm.com> | 2017-11-07 09:23:48 -0600 |
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committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-11-17 14:57:36 -0600 |
commit | 6d9038e46246ce55597a9dae8eb3344eae2505af (patch) | |
tree | fb67973c7944c5035df9f9ce6aba4da2bebbd97a /import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c | |
parent | 387d3838addab113ae1bb202602cbea5a70714e4 (diff) | |
download | talos-hcode-6d9038e46246ce55597a9dae8eb3344eae2505af.tar.gz talos-hcode-6d9038e46246ce55597a9dae8eb3344eae2505af.zip |
PGPE/CME Hcode: Safe Pstate and STOP<>VDM Fixes
- Set OVERRIDE_PSAFE_PSTATE=0(use psafe from GPPB) (PGPE)
- Make safe Pstate be lowest frequency limit (PGPE)
- Uses POWERSAVE if the safe mode frequency is not set. Otherwise, uses the
in the general clipping equation vs the safe computation (PGPE)
- Use the correct jump field (L_S) for setting safe mode (split variables for
better understanding (HWP)
- Incorporate PGPE fix for registration doorbell acks as Safe Mode exacerbated
a STOP 11 Quad Manager Registration timing window
- Fix CME DB0 ack window upon before QM registration
- Fix PGPE auto mode for Cronus
- Put CME Pstate analog update and Next Pstate update in critical section
to fix testing issues
Key_Cronus_Test=PM_REGRESS
Change-Id: Ie065e788c632ee41240602f654e38c59534278ef
Original-Change-Id: I10388e288251d9915a5dc0b38a9424747524ea17
CQ: SW405402
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49372
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c')
-rw-r--r-- | import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c | 23 |
1 files changed, 15 insertions, 8 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c index b094e368..4e11cd8d 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c @@ -75,12 +75,20 @@ void p9_pgpe_pstate_init() ccsr.value = in32(OCB_CCSR); G_pgpe_pstate_record.pstatesStatus = PSTATE_INIT; - G_pgpe_pstate_record.safePstate = (G_gppb->reference_frequency_khz - G_gppb->safe_frequency_khz + - (G_gppb->frequency_step_khz - 1)) / G_gppb->frequency_step_khz; -#if OVERRIDE_PSAFE_PSTATE == 1 - G_pgpe_pstate_record.safePstate = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate; -#endif + + if (G_gppb->safe_frequency_khz) + { + G_pgpe_pstate_record.safePstate = (G_gppb->reference_frequency_khz - G_gppb->safe_frequency_khz - + (G_gppb->frequency_step_khz)) / G_gppb->frequency_step_khz; + } + else + { + G_pgpe_pstate_record.safePstate = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate; + PK_TRACE_INF("Safe Frequency is NOT set. Using POWERSAVE as Pstate as safe"); + } + PK_TRACE_INF("SafePstate=0x%x", G_pgpe_pstate_record.safePstate); + PK_TRACE_INF("SafeFrequency=0x%x,SafeVoltage=0x%x", G_gppb->safe_frequency_khz, G_gppb->safe_voltage_mv); for (q = 0; q < MAX_QUADS; q++) { @@ -246,9 +254,8 @@ void p9_pgpe_pstate_apply_clips() for (q = 0; q < MAX_QUADS; q++) { uint8_t minPS = G_pgpe_pstate_record.psClipMin[q]; - uint8_t maxPS = G_pgpe_pstate_record.psClipMax[q] < - G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate ? - G_pgpe_pstate_record.psClipMax[q] : G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate; + uint8_t maxPS = G_pgpe_pstate_record.psClipMax[q] < G_pgpe_pstate_record.safePstate ? + G_pgpe_pstate_record.psClipMax[q] : G_pgpe_pstate_record.safePstate; if (G_pgpe_pstate_record.activeQuads & QUAD_MASK(q)) { |