STOP: Support to unfreeze IMA after self-restore

Change-Id: Ibbfdd893ceeb69b69537fbe46cfc692ab18eb744
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40299
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

3 files changed, 18 insertions, 13 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h
index b1fb9b6f..7e58a6fb 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h
@@ -93,10 +93,11 @@
 #define RAM_STATUS             0x20010A50
 #define SCOM_SPRC              0x20010A80
 #define SPR_MODE               0x20010A84
-#define SCRACTH0               0x20010A86
-#define SCRACTH1               0x20010A87
+#define SCRATCH0               0x20010A86
+#define SCRATCH1               0x20010A87
 #define THREAD_INFO            0x20010A9B
 #define DIRECT_CONTROLS        0x20010A9C
+#define IMA_EVENT_MASK         0x20010AA8
 #define HRMOR                  0x20010AB9
 
 #define C_SYNC_CONFIG          0x20030000
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index 72fda6a8..d8d7aa9f 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -99,12 +99,12 @@ uint16_t ram_read_lpid( uint32_t core, uint32_t thread )
 
     if (core & CME_MASK_C0)
     {
-        CME_GETSCOM(SCRACTH0, CME_MASK_C0, CME_SCOM_AND, scom_data);
+        CME_GETSCOM(SCRATCH0, CME_MASK_C0, CME_SCOM_AND, scom_data);
     }
 
     if (core & CME_MASK_C1)
     {
-        CME_GETSCOM(SCRACTH1, CME_MASK_C1, CME_SCOM_AND, scom_data);
+        CME_GETSCOM(SCRATCH1, CME_MASK_C1, CME_SCOM_AND, scom_data);
     }
 
     PK_TRACE("RAMMING LPID read for core 0x%X 0x%X", core, (uint32_t) (scom_data & 0xFFFFFFFF));
@@ -127,14 +127,14 @@ void ram_write_lpid( uint32_t core, uint32_t thread, uint16_t lpid )
     {
         PK_TRACE("LPID Set SPRC to scratch0 for core0 via SCOM_SPRC");
         CME_PUTSCOM(SCOM_SPRC, CME_MASK_C0, 0);
-        CME_PUTSCOM(SCRACTH0, CME_MASK_C0, (uint64_t) lpid);
+        CME_PUTSCOM(SCRATCH0, CME_MASK_C0, (uint64_t) lpid);
     }
 
     if (core & CME_MASK_C1)
     {
         PK_TRACE("LPID Set SPRC to scratch1 for core1 via SCOM_SPRC");
         CME_PUTSCOM(SCOM_SPRC, CME_MASK_C1, BIT64(60));
-        CME_PUTSCOM(SCRACTH1, CME_MASK_C1, (uint64_t) lpid);
+        CME_PUTSCOM(SCRATCH1, CME_MASK_C1, (uint64_t) lpid);
     }
 
     PK_TRACE("LPID RAM: mfspr sprd , gpr0 via RAM_CTRL");
@@ -159,12 +159,12 @@ void turn_off_ram_mode (uint32_t core)
 
     if (core & CME_MASK_C0)
     {
-        CME_PUTSCOM(SCRACTH0,  CME_MASK_C0, 0);
+        CME_PUTSCOM(SCRATCH0,  CME_MASK_C0, 0);
     }
 
     if (core & CME_MASK_C1)
     {
-        CME_PUTSCOM(SCRACTH1,  CME_MASK_C1, 0);
+        CME_PUTSCOM(SCRATCH1,  CME_MASK_C1, 0);
     }
 
     PK_TRACE("LPID Clear core maintenance mode via direct controls");
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
index 55615c8c..81c81391 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
@@ -874,15 +874,15 @@ p9_cme_stop_exit()
                 PK_TRACE_DBG("Set SPRC to scratch for core[%d] via SCOM_SPRC", core_mask);
                 CME_PUTSCOM(SCOM_SPRC, core_mask, ((core_mask & 1) ? BIT64(60) : 0));
 
-                PK_TRACE_DBG("Load SCRACTH with HOMER+2MB address %x", scom_data.value);
+                PK_TRACE_DBG("Load SCRATCH0 with HOMER+2MB address %x", scom_data.value);
 
 #if EPM_P9_TUNING
 
-                CME_PUTSCOM((SCRACTH0 + (core_mask & 1)), core_mask, 0xA200000);
+                CME_PUTSCOM((SCRATCH0 + (core_mask & 1)), core_mask, 0xA200000);
 
 #else
 
-                CME_PUTSCOM((SCRACTH0 + (core_mask & 1)), core_mask, scom_data.value);
+                CME_PUTSCOM((SCRATCH0 + (core_mask & 1)), core_mask, scom_data.value);
 
 #endif
             }
@@ -906,12 +906,12 @@ p9_cme_stop_exit()
 
         if (core & CME_MASK_C0)
         {
-            CME_PUTSCOM(SCRACTH0,  CME_MASK_C0, 0);
+            CME_PUTSCOM(SCRATCH0,  CME_MASK_C0, 0);
         }
 
         if (core & CME_MASK_C1)
         {
-            CME_PUTSCOM(SCRACTH1,  CME_MASK_C1, 0);
+            CME_PUTSCOM(SCRATCH1,  CME_MASK_C1, 0);
         }
 
 #endif
@@ -973,6 +973,10 @@ p9_cme_stop_exit()
         PK_TRACE("Restore SPATTN after self-restore");
         CME_PUTSCOM(SPATTN_MASK, core, scom_data.value);
 
+        PK_TRACE("Always Unfreeze IMA (by clearing bit 34) in case the CHTM is enabled to sample it");
+        CME_GETSCOM(IMA_EVENT_MASK, core, CME_SCOM_EQ, scom_data.value);
+        CME_PUTSCOM(IMA_EVENT_MASK, core, scom_data.value & ~BIT64(34));
+
         PK_TRACE("Drop block interrupt to PC via SICR[2/3]");
         out32(CME_LCL_SICR_CLR, core << SHIFT32(3));