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| author | Nick Klazynski <jklazyns@us.ibm.com> | 2018-04-02 14:13:26 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-04-13 09:17:38 -0500 |
| commit | 48545f1d475a93ff38be0f7f139d610681eed695 (patch) | |
| tree | fa0dfcf1702caa37a16d993e1f84ad35c1e026fe /import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c | |
| parent | 270068cbfcb001fa5ccfbb6e8bc18eea22d68487 (diff) | |
| download | talos-hcode-48545f1d475a93ff38be0f7f139d610681eed695.tar.gz talos-hcode-48545f1d475a93ff38be0f7f139d610681eed695.zip | |
Add core-level checkstop support for Cumulus and Axone
Change-Id: Ib0a11e1b85a5dc7a07d6ae0974f0e95ea937e793
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56585
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c')
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c index 8b1d4bc3..c1111f3a 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2017 */ +/* COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -70,11 +70,18 @@ p9_hcd_core_scominit(uint32_t core) scom_data.words.upper |= BITS32(20, 2);// DTS loop1 enable CME_PUTSCOM(C_THERM_MODE_REG, core, scom_data.value); - // content of p9_core_scom + // Cumulus and Axone support core-level checkstop, + // however Nimbus-based products do not. PK_TRACE("Initialize FIR MASK/ACT0/ACT1"); +#if NIMBUS_DD_LEVEL >= 10 CME_PUTSCOM(CORE_ACTION0, core, 0x0000000000000000); CME_PUTSCOM(CORE_ACTION1, core, 0xA854009775100000); CME_PUTSCOM(CORE_FIRMASK, core, 0x0301D70000AB76FE); +#else + CME_PUTSCOM(CORE_ACTION0, core, 0x14A800408A000040); + CME_PUTSCOM(CORE_ACTION1, core, 0xBCFC00D7FF100040); + CME_PUTSCOM(CORE_FIRMASK, core, 0x0301D70000AB76BE); +#endif PK_TRACE("Update Core Hang Pulse Dividers via C_HANG_CONTROL[0-15]"); CME_GETSCOM(C_HANG_CONTROL, core, scom_data.value); |
