CME/SGPE: STOP image updates and fixes

patchset 1: fix quad spwu(initial)
patchset 2: fix quad spwu
patchset 3: set scan0 and arrayinit code as default
patchset 4: fix for stop3 being nop
patchset 5: fix unitified interrupt handler hole of ee bit
patchset 6: workaround for pbie read ptr hw bug(initial)
patchset 7: optional debug trap based on occ flag[12]/[13]
            fix stop8 history update typo
            update fix in patchset 6(still more to come)
patchset 8: default disable HW386311_PBIE_RW_PTR_STOP11_FIX
patchset 9: workaround for pbie read ptr hw bug(complete)
patchset 10:update workaround debug trace and RTC comment
patchset 11:add more pk traces to workaround and fix addr
patchset 12:fix region bits for the workaround
patchset 13:fix region bits ver2
patchset 14:rebase for merge conflict
patchset 15:reset scan0/arrayinit to on after rebase
patchset 16:fix workaround ring length for rotate back
patchset 17:fix pk trace on printing 64bit variables
patchset 18:fix l3 purge abort
            add more traces in partial good config
patchset 19:fix history reporting in scominit
patchset 20:fix spin bug on 6bits
            change thread stack size on cme to 512
            fix sgpe default pk_app_cfg on istep15_hack
patchset 21:fix a typo in patchset 20
patchset 22:fix quad stop history bit0
patchset 23:fix typo in previous 22
patchset 24:add more debug thrace for workaround
            have parameter for each thread stack size
patchset 25:fix typo in 24
patchset 26:fix quad spwu done and possible for pfet error
patchset 27:fix stupid kernel bug to cause 0x03abcdef
patchset 28:1) add dls+stop1 workaround for pls+srr1 issue
            2) some code for bce irritator
            3) add block wakeup support and db1+db2 change
            4) Note: one marker change for doorbell
patchset 29:add broadside support for scan0 module
patchset 30:add fused core mode workaround
            fix workaround compiler define
patchset 31:fix qspwu parital good case
            fix compiler error with broadside mode
            fix conflict of enum between two headers
patchset 32:fix stop handler anormaly introduced by
            unified interrupt handler returns group id
patchset 33:fix a bug introduced by patchset 32
patchset 34:clean scan0 region after workaround
patchset 35:Rebased

Change-Id: I315d8ccc425a0d420a77d82814962ff6eaa38152
RTC: 161155
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29405
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Dev-Ready: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

1 files changed, 62 insertions, 5 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
index 89b9d4f8..624e1513 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
@@ -53,14 +53,71 @@ p9_cme_stop_event_handler(void* arg, PkIrqId irq)
 {
     MARK_TRAP(STOP_EVENT_HANDLER)
     PK_TRACE("STOP-IRQ: %d", irq);
-    pk_semaphore_post((PkSemaphore*)arg);
+
+    if (in32(CME_LCL_EISR) & BITS32(12, 6))
+    {
+        PK_TRACE("lanuch exit");
+        pk_semaphore_post((PkSemaphore*)(&(G_cme_stop_record.sem[1])));
+    }
+    else if (in32(CME_LCL_EISR) & BITS32(20, 2))
+    {
+        PK_TRACE("lanuch entry");
+        pk_semaphore_post((PkSemaphore*)(&(G_cme_stop_record.sem[0])));
+    }
 }
 
 void
-p9_cme_stop_doorbell_handler(void* arg, PkIrqId irq)
+p9_cme_stop_db1_handler(void* arg, PkIrqId irq)
 {
-    PkMachineContext  ctx;
-    MARK_TRAP(STOP_DOORBELL_HANDLER)
-    PK_TRACE("DB-IRQ: %d", irq);
+    PkMachineContext ctx;
+    MARK_TRAP(STOP_DB1_HANDLER)
+    PK_TRACE("DB1-IRQ: %d", irq);
+    pk_irq_vec_restore(&ctx);
+}
+
+void
+p9_cme_stop_db2_handler(void* arg, PkIrqId irq)
+{
+    PkMachineContext ctx;
+    cppm_cmedb2_t    db2c0, db2c1;
+
+    MARK_TRAP(STOP_DB2_HANDLER)
+    PK_TRACE("DB2-IRQ: %d", irq);
+
+    CME_GETSCOM(CPPM_CMEDB2, CME_MASK_C0, CME_SCOM_AND, db2c0.value);
+    CME_GETSCOM(CPPM_CMEDB2, CME_MASK_C1, CME_SCOM_AND, db2c1.value);
+    CME_PUTSCOM(CPPM_CMEDB2, CME_MASK_BC, 0);
+    out32(CME_LCL_EISR_CLR,  BITS32(18, 2));
+
+    if (db2c0.fields.cme_message_numbern == DB2_BLOCK_WKUP_ENTRY)
+    {
+        G_cme_stop_record.core_blockwu |= CME_MASK_C0;
+        g_eimr_override                |= IRQ_VEC_PCWU_C0;
+    }
+    else if (db2c0.fields.cme_message_numbern == DB2_BLOCK_WKUP_EXIT)
+    {
+        G_cme_stop_record.core_blockwu &= ~CME_MASK_C0;
+        g_eimr_override                &= ~IRQ_VEC_PCWU_C0;
+    }
+
+    if (db2c1.fields.cme_message_numbern == DB2_BLOCK_WKUP_ENTRY)
+    {
+        G_cme_stop_record.core_blockwu |= CME_MASK_C1;
+        g_eimr_override                |= IRQ_VEC_PCWU_C1;
+    }
+    else if (db2c1.fields.cme_message_numbern == DB2_BLOCK_WKUP_EXIT)
+    {
+        G_cme_stop_record.core_blockwu &= ~CME_MASK_C1;
+        g_eimr_override                &= ~IRQ_VEC_PCWU_C1;
+    }
+
+    out32(CME_LCL_SICR_OR,  G_cme_stop_record.core_blockwu << SHIFT32(3));
+    out32(CME_LCL_SICR_CLR,
+          (~G_cme_stop_record.core_blockwu & CME_MASK_BC) << SHIFT32(3));
+
+    out32(CME_LCL_FLAGS_OR, G_cme_stop_record.core_blockwu << SHIFT32(9));
+    out32(CME_LCL_FLAGS_CLR,
+          (~G_cme_stop_record.core_blockwu & CME_MASK_BC) << SHIFT32(9));
+
     pk_irq_vec_restore(&ctx);
 }