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| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2017-10-25 06:18:02 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-11-17 15:06:50 -0600 |
| commit | 7b498d0313e135c84e573f6ebba9421d1beab7ba (patch) | |
| tree | ac7bca580053e52e314edf45ff1fcec7339dd236 /import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h | |
| parent | 6ec15f3d2d8fd652e1ce89cf105220a0a8274092 (diff) | |
| download | talos-hcode-7b498d0313e135c84e573f6ebba9421d1beab7ba.tar.gz talos-hcode-7b498d0313e135c84e573f6ebba9421d1beab7ba.zip | |
EQ SCOM Restore: Introduced version control in SCOM restore entry.
- introduces version control in header of SCOM restore entry
- ensures backward compatibility
- introduces flexibility to handle any number of SCOM restore entry.
Key_Cronus_Test=NO_TEST
CQ:HW423686
HW-Image-Prereq: Ie1611b009e95192a0dad3a47af14ef8a36dd454b
Change-Id: I5d4e544461e94f61a3135e8b029a0ca3b0088814
Original-Change-Id: I781b0862dc983001574ba5f09a84ea0a2f7f781f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48793
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h')
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h index ede65f5e..f86bbc99 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h @@ -208,6 +208,12 @@ enum CME_STOP_SRR1 NO_STATE_LOSS = 1 }; +enum CME_SCOM_RESTORE_CONST +{ + SCOM_REST_SKIP_CODE = 0x60000000, +}; + + #if TEST_ONLY_BCE_IRR #define FLAG_BCE_IRR_ENABLE BIT32(18) |
