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| author | Christopher M. Riedl <cmriedl@us.ibm.com> | 2017-04-12 09:35:32 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:30:48 -0500 |
| commit | 849710ebc56c667778a74a354681ad2a7fb9c92f (patch) | |
| tree | 5c87d63208d40f109c2f94cc8dd9e7f357b55c7d /import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h | |
| parent | 03e5a6f2151e689fa484f5e8964797e6b5b203f4 (diff) | |
| download | talos-hcode-849710ebc56c667778a74a354681ad2a7fb9c92f.tar.gz talos-hcode-849710ebc56c667778a74a354681ad2a7fb9c92f.zip | |
Pstate: Resonant Clocking Enablement - CME Hcode
- implement p9_cme_resclk_control and p9_cme_resclk_update
- initialize resclk datastructures during init
- add handler for comm_recvd (intercme msg interrupt) and corresponding
irq priority (10)
- update p9_cme_qm_flags.h to match header definition (uint16_t) and fix
duplicate flag definition
- add intercme msg functions and packet definition
Change-Id: I3509892ec90b5a2135f7419f4c78209ac24e4e06
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39353
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h')
| -rw-r--r-- | import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h index f99653e8..2eef1960 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.h @@ -58,10 +58,11 @@ #define IDX_PRTY_LVL_DB0 8 #define IDX_PRTY_LVL_INTERCME_IN0 9 #define IDX_PRTY_LVL_PMCR 10 -#define IDX_PRTY_LVL_DISABLED 11 +#define IDX_PRTY_LVL_COMM_RECVD 11 +#define IDX_PRTY_LVL_DISABLED 12 #define IDX_PRTY_VEC 0 #define IDX_MASK_VEC 1 -#define NUM_EXT_IRQ_PRTY_LEVELS (uint8_t)(12) +#define NUM_EXT_IRQ_PRTY_LEVELS 13 extern const uint64_t ext_irq_vectors_cme[NUM_EXT_IRQ_PRTY_LEVELS][2]; // Group0: Non-task hi-prty IRQs @@ -86,8 +87,10 @@ extern const uint64_t ext_irq_vectors_cme[NUM_EXT_IRQ_PRTY_LEVELS][2]; #define IRQ_VEC_PRTY9_CME (uint64_t)(0x0100000000000000) // Group10: PMCR #define IRQ_VEC_PRTY10_CME (uint64_t)(0x0000000030000000) -// Group11: We should never detect these -#define IRQ_VEC_PRTY11_CME (uint64_t)(0x00C003FFC33FFFFF) +// Group11: COMM_RECVD +#define IRQ_VEC_PRTY11_CME (uint64_t)(0x0000000400000000) +// Group12: We should never detect these +#define IRQ_VEC_PRTY12_CME (uint64_t)(0x00C003FBC33FFFFF) // This should be 0xFFFFFFFFFFFFFFFF #define IRQ_VEC_PRTY_CHECK ( IRQ_VEC_PRTY0_CME | \ @@ -101,7 +104,8 @@ extern const uint64_t ext_irq_vectors_cme[NUM_EXT_IRQ_PRTY_LEVELS][2]; IRQ_VEC_PRTY8_CME | \ IRQ_VEC_PRTY9_CME | \ IRQ_VEC_PRTY10_CME | \ - IRQ_VEC_PRTY11_CME ) + IRQ_VEC_PRTY11_CME | \ + IRQ_VEC_PRTY12_CME ) extern uint8_t g_current_prty_level; extern uint8_t g_eimr_stack[NUM_EXT_IRQ_PRTY_LEVELS]; |
