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| author | Yue Du <daviddu@us.ibm.com> | 2018-11-09 16:34:54 -0600 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2019-05-10 10:55:04 -0500 |
| commit | f52ed17d38e2db55d094f95f6607a343dcfd75dd (patch) | |
| tree | 6c0b4a5a02a6c9357cd04bdc8cd429d8f0e85539 /import/chips/p9/procedures/ppe | |
| parent | d0888141f218cb29655fd0fa0d213e09325546c6 (diff) | |
| download | talos-hcode-f52ed17d38e2db55d094f95f6607a343dcfd75dd.tar.gz talos-hcode-f52ed17d38e2db55d094f95f6607a343dcfd75dd.zip | |
PM: Handle PIB Reset with data check handler on all GPEs
Key_Cronus_Test=PM_REGRESS
Change-Id: I121aaf5efb579fde88829f2ef5354ad4c8b6d77b
CQ:SW447494
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68622
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/ppe')
4 files changed, 96 insertions, 5 deletions
diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/pk_panic_codes.h b/import/chips/p9/procedures/ppe/pk/ppe42/pk_panic_codes.h index ec78f923..3504405b 100644 --- a/import/chips/p9/procedures/ppe/pk/ppe42/pk_panic_codes.h +++ b/import/chips/p9/procedures/ppe/pk/ppe42/pk_panic_codes.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2016,2017 */ +/* COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -49,7 +49,7 @@ typedef enum PK_DEFAULT_SPECIAL_HANDLER = 0x0007, PPE42_PHANTOM_INTERRUPT = 0x0008, PPE42_ILLEGAL_INSTRUCTION = 0x0009, - PK_UNUSED_000a = 0x000a, + PPE42_PIB_RESET_NOT_RECOVER = 0x000a, PK_UNUSED_000d = 0x000d, PK_UNUSED_001c = 0x001c, PK_UNUSED_001d = 0x001d, diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S index 2c773397..56cba14e 100644 --- a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S +++ b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2018 */ +/* COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -583,4 +583,49 @@ ctx_pop: rfi +__special_machine_check_handler: + + stwu %r1, -PK_CTX_SIZE(%r1) + stw %r0, PK_CTX_GPR0(%r1) + stvd %d3, PK_CTX_GPR3(%r1) + stvd %d5, PK_CTX_GPR5(%r1) + stvd %d7, PK_CTX_GPR7(%r1) + stvd %d9, PK_CTX_GPR9(%r1) + stvd %d28, PK_CTX_GPR28(%r1) + stvd %d30, PK_CTX_GPR30(%r1) + mflr %r3 + stw %r3, PK_CTX_LR(%r1) + mfcr %r3 + mfsprg0 %r4 + stvd %d3, PK_CTX_CR(%r1) + mfxer %r3 + mfctr %r4 + stvd %d3, PK_CTX_XER(%r1) + mfsrr0 %r3 + mfsrr1 %r4 + stvd %d3, PK_CTX_SRR0(%r1) +#if defined(__PPE__) + bl __ppe42_pib_reset_handler +#endif + lwz %r0, PK_CTX_GPR0(%r1) + lvd %d7, PK_CTX_SRR0(%r1) + mtsrr1 %r8 + mtsrr0 %r7 + lvd %d5, PK_CTX_XER(%r1) + mtctr %r6 + mtxer %r5 + lvd %d30, PK_CTX_GPR30(%r1) + lvd %d28, PK_CTX_GPR28(%r1) + lvd %d9, PK_CTX_GPR9(%r1) + lvd %d7, PK_CTX_GPR7(%r1) + lvd %d5, PK_CTX_GPR5(%r1) + lvd %d3, PK_CTX_CR(%r1) ## CR,SPRG0 + mtcr0 %r3 + lwz %r4, PK_CTX_LR(%r1) + mtlr %r4 + lvd %d3, PK_CTX_GPR3(%r1) + addi %r1, %r1, PK_CTX_SIZE + + rfi + /// \endcond diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq_core.c b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq_core.c index d472c183..87eafa40 100644 --- a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq_core.c +++ b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq_core.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2017 */ +/* COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -34,8 +34,50 @@ #define __PPE42_IRQ_CORE_C__ + #include "pk.h" +uint32_t G_pib_reset_flag = 0; + +#ifdef __PPE__ + +void +__ppe42_pib_reset_handler() +{ + //PK_TRACE("Entered 1 ppe42_pib_reset_handler"); + uint32_t srr1 = mfspr(SPRN_SRR1); + + // assuming pib is being reset thus give timeout error + if (((srr1 & MSR_SIBRC) == MSR_SIBRC)) + { + // if already waited for pib to reset, panic as still fail + if (G_pib_reset_flag == 10 ) + { + G_pib_reset_flag = 0; + PK_PANIC(PPE42_PIB_RESET_NOT_RECOVER); + } + + // note pib reset is being detected + // this flag will be cleared by fit timer if pib reset recovers + G_pib_reset_flag++; + + // DELAY to wait pib reset to complete + volatile uint32_t loop; + + for(loop = 0; loop < 6400; loop++); + + PK_TRACE_INF("PIB reset flag value %x", G_pib_reset_flag); + + } + else + { + // panic for all other pib return codes + PK_PANIC(PPE42_MACHINE_CHECK_PANIC); + } +} +#endif + + #ifndef STATIC_IRQ_TABLE Ppe42IrqHandler __ppe42_irq_handlers[EXTERNAL_IRQS + 1]; #endif diff --git a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.h b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.h index 36e5aa1f..df64095b 100755 --- a/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.h +++ b/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HCODE Project */ /* */ -/* COPYRIGHT 2015,2017 */ +/* COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -49,6 +49,7 @@ extern "C" { #endif + /// PPE Load Virtual Double operation #define PPE_LVD(_m_address, _m_data) \ asm volatile \ @@ -149,6 +150,9 @@ extern inline uint32_t getscom(const uint32_t i_chiplet, const uint32_t i_addres extern inline void putscom_norc(const uint32_t i_address, uint64_t i_data) { PPE_STVD(i_address, i_data); +#ifdef PK_MACHINE_HANDLER_SUPPPORT + asm volatile ("sync"); +#endif } #ifdef __cplusplus |
