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| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2018-05-24 09:03:35 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-05-26 10:32:44 -0500 |
| commit | ac95674227486cf053b1bbfce2cdc5077aded496 (patch) | |
| tree | 8ade9182d753decb2dc3ba192e30e1dcaa35ea02 /import/chips/p9/procedures/hwp | |
| parent | 17b8473da01f8dcda8d8bc4f93d07d1bf65e1ede (diff) | |
| download | talos-hcode-ac95674227486cf053b1bbfce2cdc5077aded496.tar.gz talos-hcode-ac95674227486cf053b1bbfce2cdc5077aded496.zip | |
PM: Addressed TODOs in hcode image build HWP.
Commit addresses TODOs which were found to be functional.
Code has been updated for those which needed an investigation.
TODOs which intend design improvement has been deferred for next
release.
Change-Id: I68eb6c388cc9ff6bb72b79d9de718baa2812beab
RTC: 184604
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59317
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/hwp')
| -rw-r--r-- | import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 37cc8354..b8eaa72f 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -59,7 +59,6 @@ namespace p9_hcodeImageBuild #endif //__cplusplus #endif //__ASSEMBLER__ -//FIXME to make future addition simple, need a better solution /** * @brief returns maximum quad common rings that enter HOMER. */ @@ -255,9 +254,7 @@ HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); #ifdef __ASSEMBLER__ .endm #else -//FIXME RTC 155018 -//Eventually SGPE Img header has been defined to be of size 96B. Next 36B would be for -//debug pointer.Aligning SGPE image header to 64B boundary. +//SGPE header size is 96B } __attribute__((packed, aligned(IMG_HDR_ALIGN_SIZE))) sgpeHeader_t; #endif @@ -299,9 +296,7 @@ HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); #ifdef __ASSEMBLER__ .endm #else -//FIXME RTC 155018 -//Eventually CME Img header might be of size 96B. Next 36B would be for -//debug pointer.Aligning CME image header to 64B boundary. +//CME Header size is 96B } __attribute__((packed, aligned(IMG_HDR_ALIGN_SIZE))) cmeHeader_t; #endif @@ -364,9 +359,7 @@ HCD_HDR_UINT32(g_pgpe_doptrace_length, 0 ); // Deep Opeartional #ifdef __ASSEMBLER__ .endm #else -//FIXME RTC 155018 -//Eventually PGPE Img header has been defined to be of size 96B. Next 36B would be for -//debug pointer.Aligning PGPE image header to 64B boundary. +//PGPE Header size is 128B } __attribute__((packed, aligned(IMG_HDR_ALIGN_SIZE))) PgpeHeader_t; #endif @@ -618,6 +611,7 @@ typedef struct uint8_t cmeSramRegion[CME_REGION_SIZE]; } CPMRLayout_t; + /** * @brief models image section associated with PGPE in HOMER. */ @@ -631,7 +625,8 @@ typedef struct uint8_t ppmr_reserved0[PGPE_IMAGE_RESERVE_SIZE]; uint8_t occParmBlock[sizeof(OCCPstateParmBlock)]; // PPMR + 128KB uint8_t occParmBlockReserve[OCC_PSTATE_PARAM_BLOCK_REGION_SIZE - sizeof(OCCPstateParmBlock)]; - uint8_t pstateTable[PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE]; // PPMR + 144KB + uint8_t pstateTable[sizeof(GeneratedPstateInfo)]; // PPMR + 144KB + uint8_t pstateTableReserve[PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE - sizeof(GeneratedPstateInfo)]; uint8_t ppmr_reserved1[WOF_TABLE_RESERVE]; uint8_t wofTableSize[OCC_WOF_TABLES_SIZE]; //WOF Tables located ar PPMR base + 768KB } PPMRLayout_t; |

