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| author | Prasad Bg Ranganath <prasadbgr@in.ibm.com> | 2018-05-23 05:02:06 -0500 |
|---|---|---|
| committer | hostboot <hostboot@us.ibm.com> | 2018-06-08 10:35:43 -0500 |
| commit | db007d46b1de4d0b30ca15fa2b1d2260c88a89d8 (patch) | |
| tree | 39b68bf936ff2980037c746a5cdc4a4c12644845 /import/chips/p9/procedures/hwp/lib | |
| parent | ef6955814d8ec3b716236d00eff8fd9af4173ea2 (diff) | |
| download | talos-hcode-db007d46b1de4d0b30ca15fa2b1d2260c88a89d8.tar.gz talos-hcode-db007d46b1de4d0b30ca15fa2b1d2260c88a89d8.zip | |
PPB: Bug fix in computing IAC Vdn value
- Hardcode the Vdn Ceff value to 1 as the dimension is not supported in the WOF
Tables. This avoids the root of the issue noted which was VPD data
dependent in the previous algoithm for an unused element.
- Update OCC Pstate Parameter Block comments on Iddq units to 5mA
-- This is non-functional update to ensure the header comments represent
reality and is for documentation only!!! (no pre/co-req)
Key_Cronus_Test=PM_REGRESS
Change-Id: I3a790160998eda4e384d9bcb9da7198aa45f457c
CQ:SW429936
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60033
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/hwp/lib')
| -rw-r--r-- | import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h b/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h index c8b8ea29..086776e3 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h +++ b/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h @@ -107,19 +107,19 @@ typedef struct /// Spare uint8_t spare[8]; - /// IVDD ALL Good Cores ON; 1mA units + /// IVDD ALL Good Cores ON; 5mA units iddq_entry_t ivdd_all_good_cores_on_caches_on[IDDQ_MEASUREMENTS]; - /// IVDD ALL Cores OFF; 1mA units + /// IVDD ALL Cores OFF; 5mA units iddq_entry_t ivdd_all_cores_off_caches_off[IDDQ_MEASUREMENTS]; - /// IVDD ALL Good Cores OFF; 1mA units + /// IVDD ALL Good Cores OFF; 5mA units iddq_entry_t ivdd_all_good_cores_off_good_caches_on[IDDQ_MEASUREMENTS]; - /// IVDD Quad 0 Good Cores ON, Caches ON; 1mA units + /// IVDD Quad 0 Good Cores ON, Caches ON; 5mA units iddq_entry_t ivdd_quad_good_cores_on_good_caches_on[MAXIMUM_QUADS][IDDQ_MEASUREMENTS]; - /// IVDDN; 1mA units + /// IVDDN; 5mA units iddq_entry_t ivdn[IDDQ_MEASUREMENTS]; /// IVDD ALL Good Cores ON, Caches ON; 0.5C units |
