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| author | Stephen Glancy <sglancy@us.ibm.com> | 2017-05-25 10:35:02 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:47:02 -0500 |
| commit | 36eadd6d59c6410409d9f60ce06ac1613e00b603 (patch) | |
| tree | 491c0e2a42402e10b9da70491376e2829345413c /import/chips/p9/common | |
| parent | 724effb336d509e303def707646b78e0b7d6107e (diff) | |
| download | talos-hcode-36eadd6d59c6410409d9f60ce06ac1613e00b603.tar.gz talos-hcode-36eadd6d59c6410409d9f60ce06ac1613e00b603.zip | |
Adds DD2 dcd functionality
Change-Id: I2d873ea84b8ae202d78cf8c49ffce56caebd3699
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41052
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/common')
| -rw-r--r-- | import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H b/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H index c35b547d..e67c7e39 100644 --- a/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H +++ b/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H @@ -149,6 +149,11 @@ static const uint64_t SH_FLD_23_DD2_PERBIT_RDVREF_DISABLE = 99990099; static const uint64_t SH_FLD_4_DD2_PERBIT_RDVREF_DISABLE = 99990100; static const uint64_t SH_FLD_01_DD2_BLUE_EXTEND_RANGE = 99990101; static const uint64_t SH_FLD_01_DD2_BLUE_EXTEND_RANGE_LEN = 99990102; +static const uint64_t SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST_LEN = 99990103; +static const uint64_t SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ENABLE = 99990104; +static const uint64_t SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_POWERDOWN = 99990105; +static const uint64_t SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_DONE = 99990106; +static const uint64_t SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ERROR = 99990107; REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , 0 ); @@ -589,4 +594,16 @@ REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_BLUE_EXTEND_RANGE , 48 , SH SH_FLD_01_DD2_BLUE_EXTEND_RANGE ); REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_BLUE_EXTEND_RANGE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_DD2_BLUE_EXTEND_RANGE_LEN ); + +// DCD DD2 field updates +REG64_FLD( DD2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST_LEN ); +REG64_FLD( DD2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ENABLE , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ENABLE ); +REG64_FLD( DD2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_POWERDOWN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_POWERDOWN ); +REG64_FLD( DD2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_DONE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_DONE ); +REG64_FLD( DD2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ERROR , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DD2_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ERROR ); #endif |
