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| author | Joe McGill <jmcgill@us.ibm.com> | 2016-12-29 15:53:03 -0600 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:00:43 -0500 |
| commit | 11b6ab74fabd510552f2a9b9102402f2584cbb7d (patch) | |
| tree | df27989880968d3a42768b6a83d1af7cd57e6465 /import/chips/p9/common | |
| parent | 823279b7b87a119060e77bee754b6d4b2d6345ad (diff) | |
| download | talos-hcode-11b6ab74fabd510552f2a9b9102402f2584cbb7d.tar.gz talos-hcode-11b6ab74fabd510552f2a9b9102402f2584cbb7d.zip | |
FIR updates -- pervasive/core/PPE
p9_obus_scom_address_fixes.H
add OBUS IO PPE address constants
p9.cme.scan.initfile
align EQ pervasive LFIR/XFIR settings with RAS XML docs
p9.core.scan.initfile
align EC pervasive LFIR/XFIR settings with RAS XML docs
p9.core.scom.initfile
p9_hcd_core_scominit.c
adjust core FIR action settings for bits 1,12:13 to match RAS XML doc
p9_sbe_scominit.C
mask PBA FIR bit 1 to match RAS XML doc
initialize FBC/XBUS/OBUS PPE FIR registers
p9_sbe_common.C
align non-EQ/EC pervasive LFIR/XFIR settings with RAS XML docs
Change-Id: Ifbc6a47eb2dbe268a7ea832e55986d46a1870420
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34271
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Diffstat (limited to 'import/chips/p9/common')
| -rw-r--r-- | import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H b/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H index e6e30976..6b1624e3 100644 --- a/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H +++ b/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H @@ -61,4 +61,32 @@ REG64( OBUS_2_LL2_IOOL_CONTROL, REG64( OBUS_2_LL2_LL2_LL2_PB_IOOL_FIR_REG, RULL(0x0B010800), SH_UNT_OBUS_2, SH_ACS_SCOM ); +REG64( OBUS_0_IOPPE_PPE_FIR_ACTION0_REG, + RULL(0x09011046), SH_UNT_OBUS_0, SH_ACS_SCOM ); +REG64( OBUS_0_IOPPE_PPE_FIR_ACTION1_REG, + RULL(0x09011047), SH_UNT_OBUS_0, SH_ACS_SCOM ); +REG64( OBUS_0_IOPPE_PPE_FIR_MASK_REG, + RULL(0x09011043), SH_UNT_OBUS_0, SH_ACS_SCOM ); + +REG64( OBUS_1_IOPPE_PPE_FIR_ACTION0_REG, + RULL(0x0A011046), SH_UNT_OBUS_1, SH_ACS_SCOM ); +REG64( OBUS_1_IOPPE_PPE_FIR_ACTION1_REG, + RULL(0x0A011047), SH_UNT_OBUS_1, SH_ACS_SCOM ); +REG64( OBUS_1_IOPPE_PPE_FIR_MASK_REG, + RULL(0x0A011043), SH_UNT_OBUS_1, SH_ACS_SCOM ); + +REG64( OBUS_2_IOPPE_PPE_FIR_ACTION0_REG, + RULL(0x0B011046), SH_UNT_OBUS_2, SH_ACS_SCOM ); +REG64( OBUS_2_IOPPE_PPE_FIR_ACTION1_REG, + RULL(0x0B011047), SH_UNT_OBUS_2, SH_ACS_SCOM ); +REG64( OBUS_2_IOPPE_PPE_FIR_MASK_REG, + RULL(0x0B011043), SH_UNT_OBUS_2, SH_ACS_SCOM ); + +REG64( OBUS_3_IOPPE_PPE_FIR_ACTION0_REG, + RULL(0x0C011046), SH_UNT_OBUS_3, SH_ACS_SCOM ); +REG64( OBUS_3_IOPPE_PPE_FIR_ACTION1_REG, + RULL(0x0C011047), SH_UNT_OBUS_3, SH_ACS_SCOM ); +REG64( OBUS_3_IOPPE_PPE_FIR_MASK_REG, + RULL(0x0C011043), SH_UNT_OBUS_3, SH_ACS_SCOM ); + #endif |
