Combined Stop/PState Cme Image + unified interrupt handler

Change-Id: Ie954197008f1a35bd8336c9d921f55165ec52207
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20857
Tested-by: Jenkins Server
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

5 files changed, 41 insertions, 60 deletions

diff --git a/import/chips/p9/common/pmlib/include/cmehw_interrupts.h b/import/chips/p9/common/pmlib/include/cmehw_interrupts.h
index 738d9269..2b96d961 100644
--- a/import/chips/p9/common/pmlib/include/cmehw_interrupts.h
+++ b/import/chips/p9/common/pmlib/include/cmehw_interrupts.h
@@ -284,27 +284,4 @@
    STD_IRQ_MASK64(CMEHW_IRQ_RESERVED_63))
 */
 
-////////////////////////////////////////////////////////////////////////////
-// Interrupt Mask Vector
-////////////////////////////////////////////////////////////////////////////
-
-// First, it should always be true to mask the given interrupt and every
-// interrupts has larger irq id number than the given one. Then if the given
-// interrupt belongs to a group of interrupts with same priority and the given
-// one is not the first one in the group(in which case it will automatically
-// work by first rule along), then an override bit mask can be used to mask out
-// every one else in the group above the given one, or used for special cases.
-#define CME_IRQ_MASK_VECTOR(irq) ((0xffffffffffffffffull << (irq)) >> (irq))
-#define CME_IRQ_MASK_VECTOR_AND(irq, amask) (CME_IRQ_MASK_VECTOR(irq) & amask)
-#define CME_IRQ_MASK_VECTOR_OR(irq, omask)  (CME_IRQ_MASK_VECTOR(irq) | omask)
-
-#define CME_IRQ_MASK_DB3  CME_IRQ_MASK_VECTOR(CMEHW_IRQ_DOORBELL3_C0)
-#define CME_IRQ_MASK_WAKE CME_IRQ_MASK_VECTOR(CMEHW_IRQ_PC_INTR_PENDING_C0)
-#define CME_IRQ_MASK_DB2  CME_IRQ_MASK_VECTOR(CMEHW_IRQ_DOORBELL2_C0)
-#define CME_IRQ_MASK_STOP CME_IRQ_MASK_VECTOR(CMEHW_IRQ_PC_PM_STATE_ACTIVE_C0)
-#define CME_IRQ_MASK_DB0  CME_IRQ_MASK_VECTOR(CMEHW_IRQ_PMCR_UPDATE_C0)
-#define CME_IRQ_MASK_DB1  CME_IRQ_MASK_VECTOR(CMEHW_IRQ_DOORBELL1_C0)
-
-
-
 #endif  /* __CMEHW_INTERRUPTS_H__ */
diff --git a/import/chips/p9/common/pmlib/include/gpehw_common.h b/import/chips/p9/common/pmlib/include/gpehw_common.h
index 41c4eb93..8825d1b3 100644
--- a/import/chips/p9/common/pmlib/include/gpehw_common.h
+++ b/import/chips/p9/common/pmlib/include/gpehw_common.h
@@ -75,8 +75,8 @@ enum GPE_SCOM_ADDRESS_PARAMETERS
     EX0_ADDR_OFFSET             = 0x00000800,
     EX1_ADDR_OFFSET             = 0x00000C00,
     CME_ADDR_BASE               = 0x10012000,
-    CME0_ADDR_OFFSET            = 0x00000400,
-    CME1_ADDR_OFFSET            = 0x00000800
+    CME0_ADDR_OFFSET            = 0x00000000,
+    CME1_ADDR_OFFSET            = 0x00000400
 };
 
 
diff --git a/import/chips/p9/common/pmlib/include/p9_stop_common.h b/import/chips/p9/common/pmlib/include/p9_stop_common.h
index 21e07aeb..9fac87f8 100644
--- a/import/chips/p9/common/pmlib/include/p9_stop_common.h
+++ b/import/chips/p9/common/pmlib/include/p9_stop_common.h
@@ -26,8 +26,8 @@
 /// Init Vectors for Register Setup
 enum P9_HCD_COMMON_INIT_VECTORS
 {
-    // (0)CHIPLET_ENABLE
     // (1)PCB_EP_RESET
+    // (2)CLK_ASYNC_RESET
     // (3)PLL_TEST_EN
     // (4)PLLRST
     // (5)PLLBYP
@@ -35,7 +35,9 @@ enum P9_HCD_COMMON_INIT_VECTORS
     // (13)VITL_MPW2
     // (14)VITL_MPW3
     // (18)FENCE_EN
-    NET_CTRL0_INIT_VECTOR = (BIT64(0) | BIT64(1) | BITS64(3, 3) | BITS64(12, 3) | BIT64(18)),
+    // (22)FUNC_CLKSEL
+    // (26)LVLTRANS_FENCE
+    NET_CTRL0_INIT_VECTOR = (BITS64(1, 5) | BITS64(3, 3) | BIT64(18) | BIT64(22) | BIT64(26)),
     HANG_PULSE1_INIT_VECTOR = BIT64(5)
 };
 
diff --git a/import/chips/p9/common/pmlib/include/registers/cme_register_addresses.h b/import/chips/p9/common/pmlib/include/registers/cme_register_addresses.h
index f0c16fe3..93b50634 100644
--- a/import/chips/p9/common/pmlib/include/registers/cme_register_addresses.h
+++ b/import/chips/p9/common/pmlib/include/registers/cme_register_addresses.h
@@ -55,21 +55,21 @@
 #define CME_SCOM_CSAR 0x1001200d
 #define CME_SCOM_CSDR 0x1001200e
 #define CME_SCOM_BCECSR 0x1001200f
-#define CME_SCOM_BCEBAR0 0x10012010
-#define CME_SCOM_BCEBAR1 0x10012011
-#define CME_SCOM_QFMR 0x10012012
-#define CME_SCOM_AFSR 0x10012013
-#define CME_SCOM_AFTR 0x10012014
-#define CME_SCOM_VTSR0 0x10012015
-#define CME_SCOM_VTSR1 0x10012016
-#define CME_SCOM_VDSR 0x10012017
-#define CME_SCOM_EIIR 0x10012019
-#define CME_SCOM_FWMR 0x1001201a
-#define CME_SCOM_FWMR_CLR 0x1001201b
-#define CME_SCOM_FWMR_OR 0x1001201c
-#define CME_SCOM_SICR 0x1001201d
-#define CME_SCOM_SICR_CLR 0x1001201e
-#define CME_SCOM_SICR_OR 0x1001201f
+#define CME_SCOM_BCEBAR0 0x10012030
+#define CME_SCOM_BCEBAR1 0x10012031
+#define CME_SCOM_QFMR 0x10012032
+#define CME_SCOM_AFSR 0x10012033
+#define CME_SCOM_AFTR 0x10012034
+#define CME_SCOM_VTSR0 0x10012035
+#define CME_SCOM_VTSR1 0x10012036
+#define CME_SCOM_VDSR 0x10012037
+#define CME_SCOM_EIIR 0x10012039
+#define CME_SCOM_FWMR 0x1001203a
+#define CME_SCOM_FWMR_CLR 0x1001203b
+#define CME_SCOM_FWMR_OR 0x1001203c
+#define CME_SCOM_SICR 0x1001203d
+#define CME_SCOM_SICR_CLR 0x1001203e
+#define CME_SCOM_SICR_OR 0x1001203f
 #define CME_SCOM_FLAGS 0x10012020
 #define CME_SCOM_FLAGS_CLR 0x10012021
 #define CME_SCOM_FLAGS_OR 0x10012022
@@ -83,22 +83,22 @@
 #define CME_SCOM_EINR 0x1001202a
 #define CME_SCOM_SISR 0x1001202b
 #define CME_SCOM_ICRR 0x1001202c
-#define CME_SCOM_XIXCR 0x10012030
-#define CME_SCOM_XIRAMRA 0x10012031
-#define CME_SCOM_XIRAMGA 0x10012032
-#define CME_SCOM_XIRAMDBG 0x10012033
-#define CME_SCOM_XIRAMEDR 0x10012034
-#define CME_SCOM_XIDBGPRO 0x10012035
-#define CME_SCOM_XISIB 0x10012036
-#define CME_SCOM_XIMEM 0x10012037
-#define CME_SCOM_CMEXISGB 0x10012038
-#define CME_SCOM_XIICAC 0x10012039
-#define CME_SCOM_XIPCBQ0 0x1001203a
-#define CME_SCOM_XIPCBQ1 0x1001203b
-#define CME_SCOM_XIPCBMD0 0x1001203c
-#define CME_SCOM_XIPCBMD1 0x1001203d
-#define CME_SCOM_XIPCBMI0 0x1001203e
-#define CME_SCOM_XIPCBMI1 0x1001203f
+#define CME_SCOM_XIXCR 0x10012010
+#define CME_SCOM_XIRAMRA 0x10012011
+#define CME_SCOM_XIRAMGA 0x10012012
+#define CME_SCOM_XIRAMDBG 0x10012013
+#define CME_SCOM_XIRAMEDR 0x10012014
+#define CME_SCOM_XIDBGPRO 0x10012015
+#define CME_SCOM_XISIB 0x10012016
+#define CME_SCOM_XIMEM 0x10012017
+#define CME_SCOM_CMEXISGB 0x10012018
+#define CME_SCOM_XIICAC 0x10012019
+#define CME_SCOM_XIPCBQ0 0x1001201a
+#define CME_SCOM_XIPCBQ1 0x1001201b
+#define CME_SCOM_XIPCBMD0 0x1001201c
+#define CME_SCOM_XIPCBMD1 0x1001201d
+#define CME_SCOM_XIPCBMI0 0x1001201e
+#define CME_SCOM_XIPCBMI1 0x1001201f
 #define CME_SCOM_PMSRS0 0x10012040
 #define CME_SCOM_PMSRS1 0x10012041
 #define CME_SCOM_PMCRS0 0x10012042
@@ -134,6 +134,8 @@
 #define CME_LCL_AFSR 0xc0000160
 #define CME_LCL_AFTR 0xc0000180
 #define CME_LCL_LMCR 0xc00001a0
+#define CME_LCL_LMCR_OR 0xc00001b0
+#define CME_LCL_LMCR_CLR 0xc00001b8
 #define CME_LCL_BCECSR 0xc00001f0
 #define CME_LCL_PMSRS0 0xc0000200
 #define CME_LCL_PMSRS1 0xc0000220
diff --git a/import/chips/p9/common/pmlib/include/registers/ppm_firmware_registers.h b/import/chips/p9/common/pmlib/include/registers/ppm_firmware_registers.h
index 902f36fc..0c287b93 100644
--- a/import/chips/p9/common/pmlib/include/registers/ppm_firmware_registers.h
+++ b/import/chips/p9/common/pmlib/include/registers/ppm_firmware_registers.h
@@ -345,8 +345,8 @@ typedef union ppm_sshsrc
     {
 #ifdef _BIG_ENDIAN
         uint64_t stop_gated : 1;
-        uint64_t stop_transition : 2;
         uint64_t special_wkup_done : 1;
+        uint64_t stop_transition : 2;
         uint64_t req_stop_level : 4;
         uint64_t act_stop_level : 4;
         uint64_t req_write_enable : 1;
@@ -358,8 +358,8 @@ typedef union ppm_sshsrc
         uint64_t req_write_enable : 1;
         uint64_t act_stop_level : 4;
         uint64_t req_stop_level : 4;
-        uint64_t special_wkup_done : 1;
         uint64_t stop_transition : 2;
+        uint64_t special_wkup_done : 1;
         uint64_t stop_gated : 1;
 #endif // _BIG_ENDIAN
     } fields;