REMOVE duplicate ppe/include and ppe/lib folders in ekb

Using commom/pmlib/ directories instead.

Change-Id: I39470dbd2a4c498b508f8bfdf4b63ad04c0ffd9a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22368
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

6 files changed, 2055 insertions, 0 deletions

diff --git a/import/chips/p9/common/pmlib/include/registers/core_firmware_registers.h b/import/chips/p9/common/pmlib/include/registers/core_firmware_registers.h
new file mode 100644
index 00000000..2d1a99f5
--- /dev/null
+++ b/import/chips/p9/common/pmlib/include/registers/core_firmware_registers.h
@@ -0,0 +1,680 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/pmlib/include/registers/core_firmware_registers.h $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2015,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __CORE_FIRMWARE_REGISTERS_H__
+#define __CORE_FIRMWARE_REGISTERS_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file core_firmware_registers.h
+/// \brief C register structs for the CORE unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+    #ifdef __ASSEMBLER__
+        #define SIXTYFOUR_BIT_CONSTANT(x) x
+    #else
+        #define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+    #endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union c_scan_region_type
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_scan_region_type_t;
+
+
+
+typedef union c_clk_region
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_clk_region_t;
+
+
+
+typedef union c_clock_stat_sl
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_clock_stat_sl_t;
+
+
+
+typedef union c_clock_stat_nsl
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_clock_stat_nsl_t;
+
+
+
+typedef union c_clock_stat_ary
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_clock_stat_ary_t;
+
+
+
+typedef union c_net_ctrl0
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_net_ctrl0_t;
+
+
+
+typedef union c_net_ctrl0_and
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_net_ctrl0_and_t;
+
+
+
+typedef union c_net_ctrl0_or
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_net_ctrl0_or_t;
+
+
+
+typedef union c_cplt_ctrl0
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_cplt_ctrl0_t;
+
+
+
+typedef union c_cplt_ctrl0_clr
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_cplt_ctrl0_clr_t;
+
+
+
+typedef union c_cplt_ctrl0_or
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_cplt_ctrl0_or_t;
+
+
+
+typedef union c_cplt_ctrl1
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_cplt_ctrl1_t;
+
+
+
+typedef union c_cplt_ctrl1_clr
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_cplt_ctrl1_clr_t;
+
+
+
+typedef union c_cplt_ctrl1_or
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_cplt_ctrl1_or_t;
+
+
+
+typedef union c_bist
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_bist_t;
+
+
+
+typedef union c_error_reg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_error_reg_t;
+
+
+
+typedef union c_hang_pulse_1_reg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_hang_pulse_1_reg_t;
+
+
+
+typedef union c_slave_config_reg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_slave_config_reg_t;
+
+
+
+typedef union c_thread_info
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_thread_info_t;
+
+
+
+typedef union c_direct_controls
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_direct_controls_t;
+
+
+
+typedef union c_ras_status
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_ras_status_t;
+
+
+
+typedef union c_ram_modereg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_ram_modereg_t;
+
+
+
+typedef union c_ram_ctrl
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_ram_ctrl_t;
+
+
+
+typedef union c_ram_status
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} c_ram_status_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __CORE_FIRMWARE_REGISTERS_H__
diff --git a/import/chips/p9/common/pmlib/include/registers/core_register_addresses.h b/import/chips/p9/common/pmlib/include/registers/core_register_addresses.h
new file mode 100644
index 00000000..60bfa3e3
--- /dev/null
+++ b/import/chips/p9/common/pmlib/include/registers/core_register_addresses.h
@@ -0,0 +1,68 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/pmlib/include/registers/core_register_addresses.h $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2015,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __CORE_REGISTER_ADDRESSES_H__
+#define __CORE_REGISTER_ADDRESSES_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file core_register_addresses.h
+/// \brief Symbolic addresses for the CORE unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+
+#define PIB_BASE 0x20000000
+#define C_SCAN_REGION_TYPE 0x20030005
+#define C_CLK_REGION 0x20030006
+#define C_CLOCK_STAT_SL 0x20030008
+#define C_CLOCK_STAT_NSL 0x20030009
+#define C_CLOCK_STAT_ARY 0x2003000a
+#define C_NET_CTRL0 0x200f0040
+#define C_NET_CTRL0_AND 0x200f0041
+#define C_NET_CTRL0_OR 0x200f0042
+#define C_CPLT_CTRL0 0x20000000
+#define C_CPLT_CTRL0_CLR 0x20000020
+#define C_CPLT_CTRL0_OR 0x20000010
+#define C_CPLT_CTRL1 0x20000001
+#define C_CPLT_CTRL1_CLR 0x20000021
+#define C_CPLT_CTRL1_OR 0x20000011
+#define C_BIST 0x2003000b
+#define C_ERROR_REG 0x200f001f
+#define C_HANG_PULSE_1_REG 0x200f0021
+#define C_SLAVE_CONFIG_REG 0x200f001e
+#define C_THREAD_INFO 0x20010a9b
+#define C_DIRECT_CONTROLS 0x20010a9c
+#define C_RAS_STATUS 0x20010a02
+#define C_RAM_MODEREG 0x20010a51
+#define C_RAM_CTRL 0x20010a52
+#define C_RAM_STATUS 0x20010a53
+
+#endif // __CORE_REGISTER_ADDRESSES_H__
diff --git a/import/chips/p9/common/pmlib/include/registers/perv_firmware_registers.h b/import/chips/p9/common/pmlib/include/registers/perv_firmware_registers.h
new file mode 100644
index 00000000..66705519
--- /dev/null
+++ b/import/chips/p9/common/pmlib/include/registers/perv_firmware_registers.h
@@ -0,0 +1,602 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/pmlib/include/registers/perv_firmware_registers.h $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2015,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PERV_FIRMWARE_REGISTERS_H__
+#define __PERV_FIRMWARE_REGISTERS_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file perv_firmware_registers.h
+/// \brief C register structs for the PERV unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+    #ifdef __ASSEMBLER__
+        #define SIXTYFOUR_BIT_CONSTANT(x) x
+    #else
+        #define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+    #endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union perv_scan_region_type
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_scan_region_type_t;
+
+
+
+typedef union perv_clk_region
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_clk_region_t;
+
+
+
+typedef union perv_clock_stat_sl
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_clock_stat_sl_t;
+
+
+
+typedef union perv_clock_stat_nsl
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_clock_stat_nsl_t;
+
+
+
+typedef union perv_clock_stat_ary
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_clock_stat_ary_t;
+
+
+
+typedef union perv_net_ctrl0
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_net_ctrl0_t;
+
+
+
+typedef union perv_net_ctrl0_and
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_net_ctrl0_and_t;
+
+
+
+typedef union perv_net_ctrl0_or
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_net_ctrl0_or_t;
+
+
+
+typedef union perv_cplt_ctrl0
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_cplt_ctrl0_t;
+
+
+
+typedef union perv_cplt_ctrl0_clr
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_cplt_ctrl0_clr_t;
+
+
+
+typedef union perv_cplt_ctrl0_or
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_cplt_ctrl0_or_t;
+
+
+
+typedef union perv_cplt_ctrl1
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_cplt_ctrl1_t;
+
+
+
+typedef union perv_cplt_ctrl1_clr
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_cplt_ctrl1_clr_t;
+
+
+
+typedef union perv_cplt_ctrl1_or
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_cplt_ctrl1_or_t;
+
+
+
+typedef union perv_bist
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_bist_t;
+
+
+
+typedef union perv_error_reg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_error_reg_t;
+
+
+
+typedef union perv_hang_pulse_1_reg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_hang_pulse_1_reg_t;
+
+
+
+typedef union perv_slave_config_reg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_slave_config_reg_t;
+
+
+
+typedef union perv_opcg_reg0
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_opcg_reg0_t;
+
+
+
+typedef union perv_opcg_reg1
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_opcg_reg1_t;
+
+
+
+typedef union perv_cplt_stat0
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} perv_cplt_stat0_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __PERV_FIRMWARE_REGISTERS_H__
diff --git a/import/chips/p9/common/pmlib/include/registers/perv_register_addresses.h b/import/chips/p9/common/pmlib/include/registers/perv_register_addresses.h
new file mode 100644
index 00000000..9c8593fb
--- /dev/null
+++ b/import/chips/p9/common/pmlib/include/registers/perv_register_addresses.h
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/pmlib/include/registers/perv_register_addresses.h $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2015,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PERV_REGISTER_ADDRESSES_H__
+#define __PERV_REGISTER_ADDRESSES_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file perv_register_addresses.h
+/// \brief Symbolic addresses for the PERV unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+
+#define PIB_BASE 0x0
+#define PERV_SCAN_REGION_TYPE 0x00030005
+#define PERV_CLK_REGION 0x00030006
+#define PERV_CLOCK_STAT_SL 0x00030008
+#define PERV_CLOCK_STAT_NSL 0x00030009
+#define PERV_CLOCK_STAT_ARY 0x0003000a
+#define PERV_NET_CTRL0 0x000f0040
+#define PERV_NET_CTRL0_AND 0x000f0041
+#define PERV_NET_CTRL0_OR 0x000f0042
+#define PERV_CPLT_CTRL0 0x00000000
+#define PERV_CPLT_CTRL0_CLR 0x00000020
+#define PERV_CPLT_CTRL0_OR 0x00000010
+#define PERV_CPLT_CTRL1 0x00000001
+#define PERV_CPLT_CTRL1_CLR 0x00000021
+#define PERV_CPLT_CTRL1_OR 0x00000011
+#define PERV_BIST 0x0003000b
+#define PERV_ERROR_REG 0x000f001f
+#define PERV_HANG_PULSE_1_REG 0x000f0021
+#define PERV_SLAVE_CONFIG_REG 0x000f001e
+#define PERV_OPCG_REG0 0x00030002
+#define PERV_OPCG_REG1 0x00030003
+#define PERV_CPLT_STAT0 0x00000100
+
+#endif // __PERV_REGISTER_ADDRESSES_H__
diff --git a/import/chips/p9/common/pmlib/include/registers/quad_firmware_registers.h b/import/chips/p9/common/pmlib/include/registers/quad_firmware_registers.h
new file mode 100644
index 00000000..dbfb03de
--- /dev/null
+++ b/import/chips/p9/common/pmlib/include/registers/quad_firmware_registers.h
@@ -0,0 +1,576 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/pmlib/include/registers/quad_firmware_registers.h $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2015,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __QUAD_FIRMWARE_REGISTERS_H__
+#define __QUAD_FIRMWARE_REGISTERS_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file quad_firmware_registers.h
+/// \brief C register structs for the QUAD unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+    #ifdef __ASSEMBLER__
+        #define SIXTYFOUR_BIT_CONSTANT(x) x
+    #else
+        #define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+    #endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union eq_scan_region_type
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_scan_region_type_t;
+
+
+
+typedef union eq_clk_region
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_clk_region_t;
+
+
+
+typedef union eq_clock_stat_sl
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_clock_stat_sl_t;
+
+
+
+typedef union eq_clock_stat_nsl
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_clock_stat_nsl_t;
+
+
+
+typedef union eq_clock_stat_ary
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_clock_stat_ary_t;
+
+
+
+typedef union eq_net_ctrl0
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_net_ctrl0_t;
+
+
+
+typedef union eq_net_ctrl0_and
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_net_ctrl0_and_t;
+
+
+
+typedef union eq_net_ctrl0_or
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_net_ctrl0_or_t;
+
+
+
+typedef union eq_cplt_ctrl0
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_cplt_ctrl0_t;
+
+
+
+typedef union eq_cplt_ctrl0_clr
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_cplt_ctrl0_clr_t;
+
+
+
+typedef union eq_cplt_ctrl0_or
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_cplt_ctrl0_or_t;
+
+
+
+typedef union eq_cplt_ctrl1
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_cplt_ctrl1_t;
+
+
+
+typedef union eq_cplt_ctrl1_clr
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_cplt_ctrl1_clr_t;
+
+
+
+typedef union eq_cplt_ctrl1_or
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_cplt_ctrl1_or_t;
+
+
+
+typedef union eq_bist
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_bist_t;
+
+
+
+typedef union eq_error_reg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_error_reg_t;
+
+
+
+typedef union eq_hang_pulse_1_reg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_hang_pulse_1_reg_t;
+
+
+
+typedef union eq_slave_config_reg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_slave_config_reg_t;
+
+
+
+typedef union eq_pm_purge_reg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_pm_purge_reg_t;
+
+
+
+typedef union eq_dram_ref_reg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t value : 64;
+#else
+        uint64_t value : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} eq_dram_ref_reg_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __QUAD_FIRMWARE_REGISTERS_H__
diff --git a/import/chips/p9/common/pmlib/include/registers/quad_register_addresses.h b/import/chips/p9/common/pmlib/include/registers/quad_register_addresses.h
new file mode 100644
index 00000000..ca4c5700
--- /dev/null
+++ b/import/chips/p9/common/pmlib/include/registers/quad_register_addresses.h
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/pmlib/include/registers/quad_register_addresses.h $ */
+/*                                                                        */
+/* OpenPOWER HCODE Project                                                */
+/*                                                                        */
+/* COPYRIGHT 2015,2017                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __QUAD_REGISTER_ADDRESSES_H__
+#define __QUAD_REGISTER_ADDRESSES_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file quad_register_addresses.h
+/// \brief Symbolic addresses for the QUAD unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+
+#define PIB_BASE 0x10000000
+#define EQ_SCAN_REGION_TYPE 0x10030005
+#define EQ_CLK_REGION 0x10030006
+#define EQ_CLOCK_STAT_SL 0x10030008
+#define EQ_CLOCK_STAT_NSL 0x10030009
+#define EQ_CLOCK_STAT_ARY 0x1003000a
+#define EQ_NET_CTRL0 0x100f0040
+#define EQ_NET_CTRL0_AND 0x100f0041
+#define EQ_NET_CTRL0_OR 0x100f0042
+#define EQ_CPLT_CTRL0 0x10000000
+#define EQ_CPLT_CTRL0_CLR 0x10000020
+#define EQ_CPLT_CTRL0_OR 0x10000010
+#define EQ_CPLT_CTRL1 0x10000001
+#define EQ_CPLT_CTRL1_CLR 0x10000021
+#define EQ_CPLT_CTRL1_OR 0x10000011
+#define EQ_BIST 0x1003000b
+#define EQ_ERROR_REG 0x100f001f
+#define EQ_HANG_PULSE_1_REG 0x100f0021
+#define EQ_SLAVE_CONFIG_REG 0x100f001e
+#define EQ_PM_PURGE_REG 0x10011c13
+#define EQ_DRAM_REF_REG 0x10011c0f
+
+#endif // __QUAD_REGISTER_ADDRESSES_H__