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| author | Joe McGill <jmcgill@us.ibm.com> | 2017-04-28 14:19:45 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 17:31:34 -0500 |
| commit | db0e717dc147bded97d46eaa23b46407206e1f39 (patch) | |
| tree | b907c6a52d0d321db967f2b1a86587b8642ab961 /import/chips/p9/common/include | |
| parent | 841724b5e162c353a9000d2df0ad23c7b37b5c88 (diff) | |
| download | talos-hcode-db0e717dc147bded97d46eaa23b46407206e1f39.tar.gz talos-hcode-db0e717dc147bded97d46eaa23b46407206e1f39.zip | |
p9_nv_ref_clk_enable -- shift NV refclock field programming
Change-Id: I4d0d4c6d32ba42f0760142cca01ac15ab4e42108
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39831
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/common/include')
| -rw-r--r-- | import/chips/p9/common/include/p9_perv_scom_addresses_fld_fixes.H | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/import/chips/p9/common/include/p9_perv_scom_addresses_fld_fixes.H b/import/chips/p9/common/include/p9_perv_scom_addresses_fld_fixes.H index f12918ac..e6b97d3d 100644 --- a/import/chips/p9/common/include/p9_perv_scom_addresses_fld_fixes.H +++ b/import/chips/p9/common/include/p9_perv_scom_addresses_fld_fixes.H @@ -61,7 +61,8 @@ static const uint64_t SH_FLD_SCAN_REGION_ALL_UNITS = 32014; static const uint64_t SH_FLD_SCAN_REGION_ALL_UNITS_LEN = 32015; static const uint64_t SH_FLD_SCAN_ALL_TYPES = 32016; static const uint64_t SH_FLD_SCAN_ALL_TYPES_LEN = 32017; - +static const uint64_t SH_FLD_TSFSI_NV_REFCLK_EN_DC = 22564; +static const uint64_t SH_FLD_TSFSI_NV_REFCLK_EN_DC_LEN = 22565; REG64_FLD( PERV_1_CLK_REGION_CLOCK_REGION_ALL_UNITS , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_CLOCK_REGION_ALL_UNITS ); @@ -105,4 +106,10 @@ REG64_FLD( PERV_1_OPCG_REG0_OPCG_STARTS_BIST , 14 , SH_UN REG64_FLD( PERV_1_OPCG_REG0_OPCG_GO , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_GO ); +REG64_FLD( PERV_ROOT_CTRL6_TSFSI_NV_REFCLK_EN_DC , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TSFSI_NV_REFCLK_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL6_TSFSI_NV_REFCLK_EN_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TSFSI_NV_REFCLK_EN_DC_LEN ); + + #endif |
