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| author | Gou Peng Fei <shgoupf@cn.ibm.com> | 2016-02-22 00:33:51 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 15:59:18 -0500 |
| commit | 96d5fbad729c0970bd07a42e661829ad36c4f2a2 (patch) | |
| tree | f3994c4cdb02364a29ffcdf0afdc073f9747e06f /import/chips/p9/common/include | |
| parent | 4e0ebb999ef2d8410e6fbf7cdeccca9fdcfc13b9 (diff) | |
| download | talos-hcode-96d5fbad729c0970bd07a42e661829ad36c4f2a2.tar.gz talos-hcode-96d5fbad729c0970bd07a42e661829ad36c4f2a2.zip | |
PCIE phase1/phase2 initialization procedure.
Changes included:
1) p9_pcie_scominit for phase1.
2) p9_pcie_config for phase2.
3) Add attribute values for phase1.
Change-Id: Id9afc0edaa716b0fdc22ac9035ad4b8ebfecb38f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20885
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Tested-by: PPE CI
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Diffstat (limited to 'import/chips/p9/common/include')
| -rw-r--r-- | import/chips/p9/common/include/p9_misc_scom_addresses_fixes.H | 137 |
1 files changed, 137 insertions, 0 deletions
diff --git a/import/chips/p9/common/include/p9_misc_scom_addresses_fixes.H b/import/chips/p9/common/include/p9_misc_scom_addresses_fixes.H index f0fc7d5f..8141bec8 100644 --- a/import/chips/p9/common/include/p9_misc_scom_addresses_fixes.H +++ b/import/chips/p9/common/include/p9_misc_scom_addresses_fixes.H @@ -413,4 +413,141 @@ REG64( PU_BCDE_OCIBAR_SCOM, RULL(0x00068014), SH_UNT, SH_ACS_SCOM_RW); REG64( PU_BCDE_STAT_SCOM, RULL(0x00068012), SH_UNT, SH_ACS_SCOM_RO); //WARNING: This register is not defined anymore in the figtree. REG64( PU_PBAXCFG_SCOM, RULL(0x00068021), SH_UNT, SH_ACS_SCOM); + +REG64( PEC_PCS_RX_CONFIG_MODE_REG , RULL(0x800004800D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_RX_CONFIG_MODE_REG , RULL(0x800004800D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_RX_CONFIG_MODE_REG , RULL(0x800004800E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_RX_CONFIG_MODE_REG , RULL(0x800004800F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + +REG64( PEC_PCS_RX_ROT_CNTL_REG , RULL(0x800004820D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_RX_ROT_CNTL_REG , RULL(0x800004820D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_RX_ROT_CNTL_REG , RULL(0x800004820E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_RX_ROT_CNTL_REG , RULL(0x800004820F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + +REG64( PEC_PCS_RX_CDR_GAIN_REG , RULL(0x800004B30D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_RX_CDR_GAIN_REG , RULL(0x800004B30D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_RX_CDR_GAIN_REG , RULL(0x800004B30E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_RX_CDR_GAIN_REG , RULL(0x800004B30F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + +REG64( PEC_PCS_RX_LOFF_CONTROL_REG , RULL(0x800004A60D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_RX_LOFF_CONTROL_REG , RULL(0x800004A60D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_RX_LOFF_CONTROL_REG , RULL(0x800004A60E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_RX_LOFF_CONTROL_REG , RULL(0x800004A60F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + +REG64( PEC_PCS_RX_SIGDET_CONTROL_REG , RULL(0x800004A70D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_RX_SIGDET_CONTROL_REG , RULL(0x800004A70D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_RX_SIGDET_CONTROL_REG , RULL(0x800004A70E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_RX_SIGDET_CONTROL_REG , RULL(0x800004A70F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + +REG64( PEC_PCS_RX_VGA_CONTROL1_REG , RULL(0x8000048B0D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_RX_VGA_CONTROL1_REG , RULL(0x8000048B0D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_RX_VGA_CONTROL1_REG , RULL(0x8000048B0E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_RX_VGA_CONTROL1_REG , RULL(0x8000048B0F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + +REG64( PEC_PCS_RX_VGA_CONTROL2_REG , RULL(0x8000048C0D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_RX_VGA_CONTROL2_REG , RULL(0x8000048C0D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_RX_VGA_CONTROL2_REG , RULL(0x8000048C0E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_RX_VGA_CONTROL2_REG , RULL(0x8000048C0F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + +REG64( PEC_PCS_RX_VGA_CONTROL3_REG , RULL(0x8000048D0D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_RX_VGA_CONTROL3_REG , RULL(0x8000048D0D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_RX_VGA_CONTROL3_REG , RULL(0x8000048D0E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_RX_VGA_CONTROL3_REG , RULL(0x8000048D0F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + +REG64( PEC_PCS_TX_DCLCK_ROTATOR_REG , RULL(0x800004450D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_TX_DCLCK_ROTATOR_REG , RULL(0x800004450D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_TX_DCLCK_ROTATOR_REG , RULL(0x800004450E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_TX_DCLCK_ROTATOR_REG , RULL(0x800004450F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + +REG64( PEC_PCS_TX_FIFO_CONFIG_OFFSET_REG , RULL(0x8000044F0D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_TX_FIFO_CONFIG_OFFSET_REG , RULL(0x8000044F0D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_TX_FIFO_CONFIG_OFFSET_REG , RULL(0x8000044F0E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_TX_FIFO_CONFIG_OFFSET_REG , RULL(0x8000044F0F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + +REG64( PEC_PCS_TX_PCIE_REC_DETECT_CNTL1_REG , RULL(0x8000046C0D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_TX_PCIE_REC_DETECT_CNTL1_REG , RULL(0x8000046C0D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_TX_PCIE_REC_DETECT_CNTL1_REG , RULL(0x8000046C0E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_TX_PCIE_REC_DETECT_CNTL1_REG , RULL(0x8000046C0F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + +REG64( PEC_PCS_TX_PCIE_REC_DETECT_CNTL2_REG , RULL(0x8000046D0D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_TX_PCIE_REC_DETECT_CNTL2_REG , RULL(0x8000046D0D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_TX_PCIE_REC_DETECT_CNTL2_REG , RULL(0x8000046D0E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_TX_PCIE_REC_DETECT_CNTL2_REG , RULL(0x8000046D0F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + +REG64( PEC_PCS_TX_POWER_SEQ_ENABLE_REG , RULL(0x800004700D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_TX_POWER_SEQ_ENABLE_REG , RULL(0x800004700D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_TX_POWER_SEQ_ENABLE_REG , RULL(0x800004700E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_TX_POWER_SEQ_ENABLE_REG , RULL(0x800004700F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + +REG64( PEC_PCS_PCLCK_CNTL_PLLA_REG , RULL(0x8000050F0D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_PCLCK_CNTL_PLLA_REG , RULL(0x8000050F0D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_PCLCK_CNTL_PLLA_REG , RULL(0x8000050F0E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_PCLCK_CNTL_PLLA_REG , RULL(0x8000050F0F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + +REG64( PEC_PCS_PCLCK_CNTL_PLLB_REG , RULL(0x8000054F0D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); +REG64( PEC_0_PCS_PCLCK_CNTL_PLLB_REG , RULL(0x8000054F0D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); +REG64( PEC_1_PCS_PCLCK_CNTL_PLLB_REG , RULL(0x8000054F0E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); +REG64( PEC_2_PCS_PCLCK_CNTL_PLLB_REG , RULL(0x8000054F0F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); + + #endif |
