PGPE: WOF OCC Interaction Initial Drop

    -Added code to enable IPC on PGPE
    -Added code for OCC IPC command(immediate return only)
    -OCC Pstate table generation code

Change-Id: I33e8f2add3a74bb332024a237250f04cfde8143b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32148
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Dev-Ready: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

9 files changed, 93 insertions, 29 deletions

diff --git a/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h b/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h
index 5c300219..32f10398 100644
--- a/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h
+++ b/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h
@@ -48,14 +48,15 @@ extern "C" {
 //---------------
 // IPC from 405
 //---------------
-
+//Note: These are really not used. They are just for documentation purposes
 enum MESSAGE_ID_IPI2HI
 {
     MSGID_405_INVALID       = 0,
     MSGID_405_START_SUSPEND = 1,
     MSGID_405_CLIPS         = 2,
-    MSGID_405_WOF_CONTROL   = 3,
-    MSGID_405_WOF_VFRT      = 4
+    MSGID_405_SET_PMCR      = 3,
+    MSGID_405_WOF_CONTROL   = 4,
+    MSGID_405_WOF_VFRT      = 5
 };
 
 //
@@ -70,15 +71,15 @@ enum MESSAGE_ID_IPI2HI
 //
 // PMCR Owner
 //
-enum PMCR_OWNER
+typedef enum
 {
     PMCR_OWNER_HOST         = 0,
     PMCR_OWNER_OCC          = 1
-};
+} PMCR_OWNER;
+
 
 typedef struct ipcmsg_base
 {
-    uint8_t   msg_id;
     uint8_t   rc;
 } ipcmsg_base_t;
 
@@ -105,6 +106,15 @@ typedef struct ipcmsg_clip_update
     uint8_t         pad[2];
 } ipcmsg_clip_update_t;
 
+
+typedef struct ipcmsg_set_pmcr
+{
+    ipcmsg_base_t   msg_cb;
+    uint8_t         pad[6];
+    uint64_t        pmcr[MAX_QUADS];
+} ipcmsg_set_pmcr_t;
+
+
 //
 // WOF Control Actions
 //
@@ -132,7 +142,7 @@ typedef struct ipcmsg_wof_vfrt
 // -----------------------------------------------------------------------------
 // Start Pstate Table
 
-#define MAX_PSTATE_TABLE_ENTRIES 256
+#define MAX_OCC_PSTATE_TABLE_ENTRIES 256
 
 /// Pstate Table produce by the PGPE for consumption by OCC Firmware
 ///
@@ -158,7 +168,7 @@ typedef struct
     uint32_t                entries;
 
     /// Internal VDD voltage ID at the output of the PFET header
-    OCCPstateTable_entry_t  table[MAX_PSTATE_TABLE_ENTRIES];
+    OCCPstateTable_entry_t  table[MAX_OCC_PSTATE_TABLE_ENTRIES];
 
 } OCCPstateTable_t;
 
@@ -169,7 +179,7 @@ typedef struct
 // Start FFDC
 
 /// Scopes of the First Failure Data Capture (FFDC) registers
-enum scope_type =
+enum scope_type
 {
     FFDC_CHIP = 0,  // Address is chip scope (eg absolute)
     FFDC_QUAD = 1,  // Address + 0x01000000*quad for good quads from 0 to 5
@@ -178,25 +188,26 @@ enum scope_type =
 };
 
 /// Address types of First Failure Data Capture (FFDC) register addresses
-enum scope_type =
+enum scope_type1
 {
     FFDC_OCI  = 0,   // Address is an OCI address
     FFDC_SCOM = 1    // Address is a SCOM address
 };
 
 /// Register definition of the Hcode FFDC register list
+#define MAX_FFDC_REG_LIST 12
 typedef struct
 {
     uint32_t            address;
-    union address_attribute
-    {
-        uint32_t value;
-        struct
+    /*    union address_attribute
         {
-            uint32_t    address_type : 16;
-            uint32_t    scope        : 16;
-        } attr;
-    }
+            uint32_t value;
+            struct
+            {
+                uint32_t    address_type : 16;
+                uint32_t    scope        : 16;
+            } attr;
+        }*/
 } Hcode_FFDC_entry_t;
 
 /// Hcode FFDC register list
@@ -220,9 +231,9 @@ typedef struct
 /// take 12B x 8 = 96B.  CME scope entries will, at maximum, generate 12B x
 /// 12 CMEs x  4 SCOMs = 576B..  The overall  totla for registers is 96 + 576
 ///
-#define MAX_FFDC_REG_LIST 12
-typedef struct Hcode_FFDC_list =
+/*typedef struct Hcode_FFDC_list
 {
+
     {PERV_TP_OCC_SCOM_OCCLFIR,  FFDC_SCOM, FFDC_CHIP }, // OCC LFIR
     {PU_PBAFIR,                 FFDC_SCOM, FFDC_CHIP }, // PBA LFIR
     {EX_CME_SCOM_LFIR,          FFDC_SCOM, FFDC_CME  }, // CME LFIR
@@ -235,7 +246,8 @@ typedef struct Hcode_FFDC_list =
     {EX_PPE_XIRAMDBG,           FFDC_SCOM, FFDC_CME  }, // CME XSR, SPRG0
     {EX_PPE_XIRAMEDR,           FFDC_SCOM, FFDC_CME  }, // CME IR, EDR
     {EX_PPE_XIDBGPRO,           FFDC_SCOM, FFDC_CME  }, // CME XSR, IAR
-};
+
+};*/
 
 // End FFDC
 // -----------------------------------------------------------------------------
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h
index edae66be..107aedff 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h
@@ -70,4 +70,7 @@ void p9_pgpe_gen_pstate_info();
 ///PGPE FIT
 void p9_pgpe_fit_init();
 
+///PGPE IPC
+void p9_pgpe_ipc_init();
+
 #endif //_P9_PGPE_H_
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
index a4a64d96..7cb1c9dc 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gen_pstate_info.c
@@ -27,6 +27,7 @@
 #include "p9_pstates_table.h"
 #include "p9_pgpe_gppb.h"
 #include "p9_pgpe_header.h"
+#include "pstate_pgpe_occ_api.h"
 
 //Generated PState Table in SRAM
 GeneratedPstateInfo G_gpi;
@@ -38,6 +39,7 @@ extern VpdOperatingPoint G_operating_points[NUM_VPD_PTS_SET][VPD_PV_POINTS];
 //
 void p9_pgpe_gen_raw_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo* gpi);
 void p9_pgpe_gen_biased_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo* gpi);
+void p9_pgpe_gen_occ_pstate_tbl(GeneratedPstateInfo* gpi);
 
 //
 //p9_pgpe_gen_pstate_info
@@ -78,11 +80,16 @@ void p9_pgpe_gen_pstate_info()
     {
         pstate_tbl_memory_offset[w] = gpi[w];
     }
+
+    //Generate Pstate table for OCC in SRAM
+    p9_pgpe_gen_occ_pstate_tbl(&G_gpi);
 }
 
 //
 //p9_pgpe_gen_raw_pstates
 //
+//Generates pstate table without biasing
+//
 void p9_pgpe_gen_raw_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo* gpi)
 {
     int32_t p;
@@ -109,6 +116,8 @@ void p9_pgpe_gen_raw_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo* g
 //
 //p9_pgpe_gen_biased_pstates
 //
+//Generates pstate table with biasing
+//
 void p9_pgpe_gen_biased_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo* gpi)
 {
     int32_t p;
@@ -134,3 +143,23 @@ void p9_pgpe_gen_biased_pstates(GlobalPstateParmBlock* gppb, GeneratedPstateInfo
         freq_khz_offset += gppb->frequency_step_khz;
     }
 }
+
+
+//
+//p9_pgpe_gen_occ_pstate_tbl
+//
+//Generates pstate table for OCC consumption
+//
+void p9_pgpe_gen_occ_pstate_tbl(GeneratedPstateInfo* gpi)
+{
+    int p;
+    OCCPstateTable_t* opst = (OCCPstateTable_t*)G_pgpe_header_data->occ_pstate_tbl_addr;
+    opst->entries = (G_pgpe_header_data->occ_pstate_tbl_length) / sizeof(OCCPstateTable_entry_t);
+
+    for (p = 0; p <= opst->entries; p++)
+    {
+        opst->table[p].pstate = gpi->biased_pstates[p].pstate;
+        opst->table[p].frequency_mhz = gpi->biased_pstates[p].frequency_mhz ;
+        opst->table[p].internal_vdd_vid  = gpi->biased_pstates[p].internal_vid;
+    }
+}
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.h
index 4f9e6eb1..02770ae1 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.h
@@ -75,12 +75,12 @@
 #define NUM_EXT_IRQ_PRTY_LEVELS  (uint8_t)(5)
 extern const uint64_t ext_irq_vectors_gpe[NUM_EXT_IRQ_PRTY_LEVELS][2];
 
-#define IRQ_VEC_PRTY0_GPE   (uint64_t)(0xFFD1690000000000) // Non-task hi-prty IRQs
+#define IRQ_VEC_PRTY0_GPE   (uint64_t)(0x0001000000000000) // Non-task hi-prty IRQs
 // Shared between all instances
-#define IRQ_VEC_PRTY1_GPE2  (uint64_t)(0x0020000000000000) // Task1-OCCHW_IRQ_OCB_ERROR=HB loss?
+#define IRQ_VEC_PRTY1_GPE2  (uint64_t)(0x0000000000000000) // Task1-OCCHW_IRQ_OCB_ERROR=HB loss?
 #define IRQ_VEC_PRTY2_GPE2  (uint64_t)(0x0000001000000000) // Task2-IPC msgs from 405
 #define IRQ_VEC_PRTY3_GPE2  (uint64_t)(0x0000000000020000) // Task3-CME interrupts
-#define IRQ_VEC_PRTY4_GPE2  (uint64_t)(0x000E96EFFFFDBFFF) // Other instances' IRQs
+#define IRQ_VEC_PRTY4_GPE2  (uint64_t)(0xFFFEFFEFFFFDFFFF) // Other instances' IRQs
 // Unique to each instance
 // We should never detect these
 
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
index 54f2e319..bcd36a15 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
@@ -131,7 +131,7 @@ main(int argc, char** argv)
                   0,
                   PPE_TIMEBASE_HZ);
 
-    // Initialize the thread control block for G_p9_pgpe_stop_enter_thread
+    // Initialize the thread control block for G_p9_pgpe_pstate_thread
     pk_thread_create(&G_p9_pgpe_pstate_thread,
                      (PkThreadRoutine)p9_pgpe_pstate_thread,
                      (void*)NULL,
@@ -143,7 +143,7 @@ main(int argc, char** argv)
                  &G_p9_pgpe_pstate_thread,
                  sizeof(G_p9_pgpe_pstate_thread));
 
-    // Make G_p9_sgpe_stop_exit_thread runnable
+    // Make G_p9_pgpe_pstate_thread runnable
     pk_thread_resume(&G_p9_pgpe_pstate_thread);
 
     //Do initialization
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
index 19eb2d86..626b9656 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
@@ -30,6 +30,7 @@
 #include "avs_driver.h"
 #include "p9_dd1_doorbell_wr.h"
 
+
 #define CCSR_CORE_CONFIG_MASK    0xC0000000
 
 enum quadManager
@@ -59,12 +60,15 @@ extern VpdOperatingPoint G_operating_points[NUM_VPD_PTS_SET][VPD_PV_POINTS];
 //
 //Function Prototypes
 //
-//void p9_pgpe_pstate_init_derived_data();
 void p9_pgpe_pstate_get_config();
 void p9_pgpe_pstate_update_ext_volt();
 void p9_pgpe_pstate_freq_update();
 
 //
+//
+//
+
+//
 //PIG Interrupt Handler
 //
 void p9_pgpe_pstate_pig_handler(void* arg, PkIrqId irq)
@@ -123,8 +127,13 @@ void p9_pgpe_pstate_thread(void* arg)
 
     pk_semaphore_create(&(G_pgpe_pstate_record.sem[0]), 0, 1);
 
+    //Initialize IPC
+    p9_pgpe_ipc_init();
+
+
     //Set OCC_FLAG[PGPE_ACTIVE]
     out32(OCB_OCCFLG_OR, BIT32(4));
+    out32(OCB_OCCS0, 0x2);
 #if EPM_P9_TUNING
     asm volatile ("tw 0, 31, 0");
 #endif
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
index ae634d49..b2a5bb44 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h
@@ -37,11 +37,15 @@
 // --------------------
 #define EPM_P9_TUNING 1
 #define SIMICS_TUNING 0
-#define GEN_PSTATE_TBL 1
+#define GEN_PSTATE_TBL 0
 #define MIMIC_BOOT_TEMP 1
 #define DEV_DEBUG     1
 #define PK_TRACE_TIMER_OUTPUT 0
 
+///This application uses IPC code
+#define GLOBAL_CFG_USE_IPC
+#define STATIC_IPC_TABLES
+
 // Force CME and GPE tasks to use the unified interrupt handler.
 #define UNIFIED_IRQ_HANDLER_GPE
 
@@ -75,6 +79,7 @@
 /// using the table defined in pk_app_irq_table.c.
 #define STATIC_IRQ_TABLE
 
+
 /// About OCCHW_IRQ_PMC_PCB_INTR_TYPE1_PENDING :
 /// This interrupt is used by the PGPE (GPE2) exclusively. Thus, rather than
 ///   defining the entire OCCHW_IRQ_ROUTES table here, and thus over-riding
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
index 212a8bde..39c741d7 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk
@@ -60,6 +60,10 @@ include $(PM_LIBDIR)/common/libcommonfiles.mk
 OBJS += $(LIBCOMMON_OBJECTS)
 $(call ADD_PPEIMAGE_SRCDIR,$(IMAGE),$(PM_LIBDIR)/common)
 
+include $(PM_LIBDIR)/occlib/liboccfiles.mk
+OBJS += $(LIBOCC_OBJECTS)
+$(call ADD_PPEIMAGE_SRCDIR,$(IMAGE),$(PM_LIBDIR)/occlib)
+
 include $(HCODE_LIBDIR)/hcodelibfiles.mk
 OBJS += $(HCODE_OBJECTS)
 $(call ADD_PPEIMAGE_SRCDIR,$(IMAGE),$(HCODE_LIBDIR))
diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/topfiles.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/topfiles.mk
index daca1dbc..74711295 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/topfiles.mk
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/topfiles.mk
@@ -30,7 +30,9 @@ TOP-C-SOURCES = p9_pgpe_pstate.c \
 				p9_pgpe_boot_temp.c \
 				p9_pgpe_gppb.c \
 				p9_pgpe_gen_pstate_info.c \
-				p9_pgpe_header.c
+				p9_pgpe_header.c \
+				p9_pgpe_ipc.c \
+				ipc_func_tables.c
 TOP-S-SOURCES =
 
 TOP_OBJECTS = $(TOP-C-SOURCES:.c=.o) $(TOP-S-SOURCES:.S=.o)