STOP: Reenable STOP8 (without L2 resonant clock support)

Patchset 4 is to reenable stop8 for regression validation
Patchset 5 is to disable  stop8 for merging to mainsteam
Formally reenable stop8 will be another commit upon NDD2.1

Change-Id: Ida2e1dd185ea07db7388d46db5ddef03588688ef
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45410
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

4 files changed, 86 insertions, 6 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
index 5d2d3f82..6a4df364 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
@@ -237,11 +237,23 @@ enum SGPE_STOP_VECTOR_INDEX
     VECTOR_ACTIVE                     = 4, //(core_ipc,    quad_ipc, qswu_active)
     VECTOR_CONFIG                     = 5, //(core,        quad)
     VECTOR_ERROR                      = 6, //(             quad)
+
+#if !DISABLE_STOP8
+
+    VECTOR_PIGE                       = 7, //(core)
+    VECTOR_PIGX                       = 8, //(core)
+    VECTOR_PCWU                       = 9  //(core)
+
+#else
+
     VECTOR_RCLKE                      = 7, //(core_blocke, quad)
     VECTOR_RCLKX                      = 8, //(core_blockx, quad)
     VECTOR_PIGE                       = 9, //(core)
     VECTOR_PIGX                       = 10,//(core)
     VECTOR_PCWU                       = 11 //(core)
+
+#endif
+
 };
 
 typedef struct
@@ -266,8 +278,19 @@ typedef struct
     uint32_t qex0[2]; // 6  bits
     uint32_t qex1[2]; // 6  bits
     uint32_t qswu[5]; // 6  bits
+
+#if !DISABLE_STOP8
+
+    uint32_t quad[7]; // 6  bits
+    uint32_t core[10];// 24 bits
+
+#else
+
     uint32_t quad[9]; // 6  bits
     uint32_t core[12];// 24 bits
+
+#endif
+
 } sgpe_group_t;
 
 typedef struct
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
index 17e10714..d1b06e5b 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
@@ -53,7 +53,9 @@ p9_sgpe_stop_entry()
     uint64_t     local_xstop       = 0;
     data64_t     scom_data         = {0};
     data64_t     temp_data         = {0};
+#if DISABLE_STOP8
     ppm_pig_t    pig               = {0};
+#endif
 #if HW386311_NDD1_PBIE_RW_PTR_STOP11_FIX
     uint32_t      spin             = 0;
 #endif
@@ -82,8 +84,14 @@ p9_sgpe_stop_entry()
     for(qloop = 0; qloop < MAX_QUADS; qloop++)
     {
         if ((G_sgpe_stop_record.group.qswu[VECTOR_ACTIVE] |
-             G_sgpe_stop_record.group.quad[VECTOR_RCLKE]  |
              G_sgpe_stop_record.group.quad[VECTOR_BLOCKE] |
+
+#if DISABLE_STOP8
+
+             G_sgpe_stop_record.group.quad[VECTOR_RCLKE]  |
+
+#endif
+
              (~G_sgpe_stop_record.group.quad[VECTOR_CONFIG])) & BIT32(qloop))
         {
             continue;
@@ -126,6 +134,13 @@ p9_sgpe_stop_entry()
         if(G_sgpe_stop_record.state[qloop].act_state_q <  LEVEL_EQ_BASE &&
            G_sgpe_stop_record.state[qloop].req_state_q >= LEVEL_EQ_BASE)
         {
+
+#if !DISABLE_STOP8
+
+            G_sgpe_stop_record.group.quad[VECTOR_ENTRY] |= BIT32(qloop);
+
+#else
+
             // if resonant clock disable is completed, process stop11 entry
             if (G_sgpe_stop_record.group.quad[VECTOR_RCLKE] & BIT32((qloop + 16)))
             {
@@ -148,8 +163,6 @@ p9_sgpe_stop_entry()
 
                 G_sgpe_stop_record.group.quad[VECTOR_ENTRY] |= BIT32(qloop);
 
-#if DISABLE_STOP8
-
                 ocb_qssr_t qssr = {0};
                 qssr.value      = in32(OCB_QSSR);
 
@@ -158,8 +171,6 @@ p9_sgpe_stop_entry()
                     (((~qssr.value) & BITS32((qloop << 1), 2)) >>
                      SHIFT32(((qloop << 1) + 1)));
 
-#endif
-
             }
             // if stop11 entry qualifies, hold on processing it but first
             // send DB to Quad-Manager to disable the resonant clock
@@ -197,6 +208,9 @@ p9_sgpe_stop_entry()
 #endif
 
             }
+
+#endif
+
         }
 
         G_sgpe_stop_record.group.ex01[qloop] &=
@@ -316,7 +330,7 @@ p9_sgpe_stop_entry()
         }
     }
 
-    PK_TRACE_INF("NDD1: L2 and NCU Purged by SGPE");
+    PK_TRACE("NDD1: L2 and NCU Purged by SGPE");
 
 #endif
 
@@ -732,6 +746,8 @@ p9_sgpe_stop_entry()
         {
             PK_TRACE_INF("Abort: L3 Purge Aborted");
 
+#if DISABLE_STOP8
+
             // assume ex0 core0 is good
             cindex = (qloop << 2);
 
@@ -763,6 +779,8 @@ p9_sgpe_stop_entry()
             // block handoff to cme until resonant clock enable is completed.
             G_sgpe_stop_record.group.quad[VECTOR_RCLKX] |= BIT32(qloop);
 
+#endif
+
             // For IPC reporting, taking aborted quad out of the list
             G_sgpe_stop_record.group.quad[VECTOR_ENTRY] &= ~BIT32(qloop);
             continue;
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
index af70aa27..5565469f 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
@@ -224,6 +224,9 @@ p9_sgpe_stop_exit_end(uint32_t qloop)
 
         if (G_sgpe_stop_record.group.core[VECTOR_EXIT] & BIT32(cindex))
         {
+
+#if DISABLE_STOP8
+
             if (G_sgpe_stop_record.group.quad[VECTOR_RCLKX] & BIT32(qloop))
             {
                 G_sgpe_stop_record.group.core[VECTOR_RCLKX] |= BIT32(cindex);
@@ -231,8 +234,17 @@ p9_sgpe_stop_exit_end(uint32_t qloop)
             else
             {
                 G_sgpe_stop_record.group.core[VECTOR_RCLKX] &= ~BIT32(cindex);
+
+#endif
+
                 p9_sgpe_stop_exit_handoff_cme(cindex);
+
+#if DISABLE_STOP8
+
             }
+
+#endif
+
         }
 
     }
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c
index 1b9b0922..21486d88 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c
@@ -52,8 +52,13 @@ SgpeStopRecord G_sgpe_stop_record __attribute__((section (".dump_ptrs"))) =
         {0, 0},
         {0, 0},
         {0, 0, 0, 0, 0},
+#if DISABLE_STOP8
         {0, 0, 0, 0, 0, 0, 0, 0},
         {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+#else
+        {0, 0, 0, 0, 0, 0},
+        {0, 0, 0, 0, 0, 0, 0, 0, 0}
+#endif
     },
     // wof status
     {0, 0, 0},
@@ -505,6 +510,8 @@ p9_sgpe_pig_cpayload_parser(const uint32_t type)
                         G_sgpe_stop_record.group.core[VECTOR_PCWU] |= BIT32(cindex);
                     }
 
+#if DISABLE_STOP8
+
                     // if having ongoing stop11 in resclk disable phase, hold on to all exits
                     if (G_sgpe_stop_record.group.quad[VECTOR_RCLKE] & BIT32(qloop))
                     {
@@ -540,6 +547,17 @@ p9_sgpe_pig_cpayload_parser(const uint32_t type)
                         G_sgpe_stop_record.group.core[VECTOR_PIGX] |=
                             G_sgpe_stop_record.group.core[VECTOR_RCLKX];
                     }
+
+#else
+
+                    if (G_sgpe_stop_record.group.quad[VECTOR_BLOCKX] & BIT32(qloop))
+                    {
+                        PK_TRACE_DBG("Core Request Exit But in Block Wakeup Mode so Ignore");
+                        G_sgpe_stop_record.group.core[VECTOR_BLOCKX] |= BIT32(cindex);
+                    }
+
+#endif
+
                     else
                     {
                         PK_TRACE_INF("Core Request Exit Confirmed");
@@ -571,6 +589,8 @@ p9_sgpe_pig_cpayload_parser(const uint32_t type)
                     PK_PANIC(SGPE_PIG_TYPE23_ENTRY_WNS_CME);
                 }
 
+#if DISABLE_STOP8
+
                 // Quad-Manager completed the resonant clock disable, proceed stop11 entry
                 // block entry protocol is checked in the entry code instead of here below
                 if ((type == PIG_TYPE5) &&
@@ -581,6 +601,8 @@ p9_sgpe_pig_cpayload_parser(const uint32_t type)
                     G_sgpe_stop_record.group.quad[VECTOR_RCLKE] |=  BIT32((qloop + 16));
                 }
 
+#endif
+
                 if (G_sgpe_stop_record.group.quad[VECTOR_BLOCKE] & BIT32(qloop))
                 {
                     PK_TRACE_DBG("Core Request Entry But in Block Entry Mode so Ignore");
@@ -799,11 +821,16 @@ p9_sgpe_pig_type5_handler(void* arg, PkIrqId irq)
     // Clear Type5 Interrupt
     out32(OCB_OISR1_CLR, BIT32(18));
 
+#if DISABLE_STOP8
+
     // Parse Type5 Requests
     p9_sgpe_pig_cpayload_parser(PIG_TYPE5);
 
     // decide if launch the thread
     p9_sgpe_pig_thread_lanucher();
+
+#endif
+
 }