STOP: Scrub _ANR and _OR opcode from regular cme getscom

Change-Id: Ie886e4d7f5b515e89cdef797e87deb07a822f058
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40765
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: BRIAN D. VICTOR <brian.d.victor1@ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

14 files changed, 97 insertions, 80 deletions

diff --git a/import/chips/p9/common/pmlib/include/cmehw_common.h b/import/chips/p9/common/pmlib/include/cmehw_common.h
index 4b692087..b9587521 100644
--- a/import/chips/p9/common/pmlib/include/cmehw_common.h
+++ b/import/chips/p9/common/pmlib/include/cmehw_common.h
@@ -59,17 +59,32 @@ enum CME_BCEBAR_INDEXES
 
 #define CME_SCOM_ADDR(addr, core, op)   (addr | (core << 22) | (op << 20))
 
+// cme getscom default with 'eq' op
+#define CME_GETSCOM(addr, core, data)                          \
+    PPE_LVD(CME_SCOM_ADDR(addr, core, CME_SCOM_EQ), data);
+
+// cme getscom with 'and' op
+#define CME_GETSCOM_AND(addr, core, data)                      \
+    PPE_LVD(CME_SCOM_ADDR(addr, core, CME_SCOM_AND), data);
+
+// cme getscom with 'or' op
+#define CME_GETSCOM_OR(addr, core, data)                       \
+    PPE_LVD(CME_SCOM_ADDR(addr, core, CME_SCOM_OR), data);
+
+// use this to override cme getscom with user specified op
+#define CME_GETSCOM_OP(addr, core, scom_op, data)              \
+    PPE_LVD(CME_SCOM_ADDR(addr, core, scom_op), data);
+
+
+// use this to override undesired queued cme putscom with nop
 #define CME_PUTSCOM_NOP(addr, core, data)                      \
     putscom_norc(CME_SCOM_ADDR(addr, core, CME_SCOM_NOP), data);
 
+// queued cme putscom if enabled; otherwise default with nop
 #if defined(USE_CME_QUEUED_SCOM)
-#define CME_GETSCOM(addr, core, scom_op, data)                 \
-    PPE_LVD(CME_SCOM_ADDR(addr, core, scom_op), data);
 #define CME_PUTSCOM(addr, core, data)                          \
     putscom_norc(CME_SCOM_ADDR(addr, core, CME_SCOM_QUEUED), data);
 #else
-#define CME_GETSCOM(addr, core, scom_op, data)                 \
-    PPE_LVD(CME_SCOM_ADDR(addr, core, scom_op), data);
 #define CME_PUTSCOM(addr, core, data)                          \
     putscom_norc(CME_SCOM_ADDR(addr, core, CME_SCOM_NOP), data);
 #endif
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
index 830b8b15..8f1be519 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_intercme.c
@@ -61,11 +61,11 @@ void p9_cme_pstate_intercme_in0_handler(void* arg, PkIrqId irq)
     {
         if (cme_flags & (BIT32(CME_FLAGS_CORE0_GOOD)))
         {
-            CME_GETSCOM(CPPM_CMEDB0, CME_MASK_C0, CME_SCOM_EQ, dbData.value);
+            CME_GETSCOM(CPPM_CMEDB0, CME_MASK_C0, dbData.value);
         }
         else
         {
-            CME_GETSCOM(CPPM_CMEDB0, CME_MASK_C1, CME_SCOM_EQ, dbData.value);
+            CME_GETSCOM(CPPM_CMEDB0, CME_MASK_C1, dbData.value);
         }
     }
     while(dbData.value == 0);
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c
index 9573aa95..66944709 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_pstate.c
@@ -72,7 +72,7 @@ int send_pig_packet(uint64_t data, uint32_t coreMask)
     do
     {
         // Read PPMPIG status
-        CME_GETSCOM(PPM_PIG, coreMask, CME_SCOM_EQ, data_tmp);
+        CME_GETSCOM(PPM_PIG, coreMask, data_tmp);
     }
     while (((ppm_pig_t)data_tmp).fields.intr_granted);
 
@@ -96,8 +96,7 @@ void ippm_read(uint32_t addr, uint64_t* data)
 
     do
     {
-        CME_GETSCOM(CPPM_IPPMSTAT, G_cme_pstate_record.cmeMaskGoodCore,
-                    CME_SCOM_EQ, val);
+        CME_GETSCOM(CPPM_IPPMSTAT, G_cme_pstate_record.cmeMaskGoodCore, val);
     } // Check the QPPM_ONGOING bit
 
     while(val & BIT64(0));
@@ -108,8 +107,7 @@ void ippm_read(uint32_t addr, uint64_t* data)
         PK_PANIC(CME_PSTATE_IPPM_ACCESS_FAILED);
     }
 
-    CME_GETSCOM(CPPM_IPPMRDATA, G_cme_pstate_record.cmeMaskGoodCore,
-                CME_SCOM_EQ, val);
+    CME_GETSCOM(CPPM_IPPMRDATA, G_cme_pstate_record.cmeMaskGoodCore, val);
 
     *data = val;
 }
@@ -130,8 +128,7 @@ void ippm_write(uint32_t addr, uint64_t data)
 
     do
     {
-        CME_GETSCOM(CPPM_IPPMSTAT, G_cme_pstate_record.cmeMaskGoodCore,
-                    CME_SCOM_EQ, val);
+        CME_GETSCOM(CPPM_IPPMSTAT, G_cme_pstate_record.cmeMaskGoodCore, val);
     } // Check the QPPM_ONGOING bit
 
     while(val & BIT64(0));
@@ -297,7 +294,7 @@ void p9_cme_resclk_update(ANALOG_TARGET target, uint32_t pstate, uint32_t curr_i
     }
     else
     {
-        CME_GETSCOM(CPPM_CACCR, target, CME_SCOM_EQ, base_val);
+        CME_GETSCOM(CPPM_CACCR, target, base_val);
     }
 
     // Preserve only the resclk control bits
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
index 2ca8dcd2..96167de0 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
@@ -180,7 +180,7 @@ void p9_cme_pstate_db_thread(void* arg)
 
     // Resonant Clocking Check (QM + Sibling)
     // Check that resonance is not enabled in CACCR and EXCGCR
-    CME_GETSCOM(CPPM_CACCR, cores, CME_SCOM_EQ, scom_data);
+    CME_GETSCOM(CPPM_CACCR, cores, scom_data);
     // Ignore clk_sync_enable and reserved
     resclk_data = (scom_data >> 32) & ~BITS32(15, 17);
 
@@ -275,12 +275,12 @@ inline void p9_cme_pstate_process_db0()
     {
         out32_sh(CME_LCL_EISR_CLR, BIT32(4));
         out32_sh(CME_LCL_EISR_CLR, BIT32(5));
-        CME_GETSCOM(CPPM_CMEDB0, CME_MASK_C0, CME_SCOM_EQ, G_dbData.value);
+        CME_GETSCOM(CPPM_CMEDB0, CME_MASK_C0, G_dbData.value);
     }
     else if (G_cme_flags & BIT32(CME_FLAGS_CORE1_GOOD))
     {
         out32_sh(CME_LCL_EISR_CLR, BIT32(5));
-        CME_GETSCOM(CPPM_CMEDB0, CME_MASK_C1, CME_SCOM_EQ, G_dbData.value);
+        CME_GETSCOM(CPPM_CMEDB0, CME_MASK_C1, G_dbData.value);
     }
 
     PK_TRACE_INF("DB_TH: DB0 0x%x\n"dbData.value);
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index 984e1496..e275f84b 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -66,7 +66,7 @@ void prepare_for_ramming (uint32_t core)
     PK_TRACE("RAMMING Activate thread0-3 for RAM via THREAD_INFO 18-21");
     CME_PUTSCOM(THREAD_INFO, core, BITS64(18, 4));
 
-    CME_GETSCOM(THREAD_INFO, core, CME_SCOM_AND, scom_data);
+    CME_GETSCOM(THREAD_INFO, core, scom_data);
     PK_TRACE("THREAD_INFO core 0x%X 0x%X", core, (uint32_t) (scom_data & 0xFFFFFFFF));
 
 
@@ -101,12 +101,12 @@ uint16_t ram_read_lpid( uint32_t core, uint32_t thread )
 
     if (core & CME_MASK_C0)
     {
-        CME_GETSCOM(SCRATCH0, CME_MASK_C0, CME_SCOM_AND, scom_data);
+        CME_GETSCOM(SCRATCH0, CME_MASK_C0, scom_data);
     }
 
     if (core & CME_MASK_C1)
     {
-        CME_GETSCOM(SCRATCH1, CME_MASK_C1, CME_SCOM_AND, scom_data);
+        CME_GETSCOM(SCRATCH1, CME_MASK_C1, scom_data);
     }
 
     PK_TRACE("RAMMING LPID read for core 0x%X 0x%X", core, (uint32_t) (scom_data & 0xFFFFFFFF));
@@ -189,7 +189,7 @@ void p9_cme_pcbmux_savior_prologue(uint32_t core)
     old_msr = mfmsr();
     new_msr = old_msr | 0x7F000000;
     mtmsr(new_msr);
-    CME_GETSCOM(0x8F0002, core, CME_SCOM_AND, scom_data);
+    CME_GETSCOM(0x8F0002, core, scom_data);
     mtmsr(old_msr);
 }
 
@@ -203,7 +203,7 @@ void p9_cme_pcbmux_savior_epilogue(uint32_t core)
     old_msr = mfmsr();
     new_msr = old_msr | 0x7F000000;
     mtmsr(new_msr);
-    CME_GETSCOM(0x00000100, core, CME_SCOM_EQ, scom_data);
+    CME_GETSCOM(0x00000100, core, scom_data);
     mtmsr(old_msr);
 
 }
@@ -698,7 +698,7 @@ p9_cme_stop_entry()
             // NDD1: Core Global Xstop FIR
             if (core & CME_MASK_C0)
             {
-                CME_GETSCOM(0x20040000, CME_MASK_C0, CME_SCOM_AND, scom_data.value);
+                CME_GETSCOM(0x20040000, CME_MASK_C0, scom_data.value);
 
                 if (scom_data.value)
                 {
@@ -710,7 +710,7 @@ p9_cme_stop_entry()
 
             if (core & CME_MASK_C1)
             {
-                CME_GETSCOM(0x20040000, CME_MASK_C1, CME_SCOM_AND, scom_data.value);
+                CME_GETSCOM(0x20040000, CME_MASK_C1, scom_data.value);
 
                 if (scom_data.value)
                 {
@@ -730,12 +730,12 @@ p9_cme_stop_entry()
 
             do
             {
-                CME_GETSCOM(C_CPLT_STAT0, core, CME_SCOM_AND, scom_data.value);
+                CME_GETSCOM_AND(C_CPLT_STAT0, core, scom_data.value);
             }
             while(!(scom_data.words.upper & BIT32(8)));
 
             PK_TRACE("Check core clock is stopped via CLOCK_STAT_SL[4-13]");
-            CME_GETSCOM(C_CLOCK_STAT_SL, core, CME_SCOM_AND, scom_data.value);
+            CME_GETSCOM_AND(C_CLOCK_STAT_SL, core, scom_data.value);
 
             if (((~scom_data.value) & CLK_REGION_ALL_BUT_PLL) != 0)
             {
@@ -756,7 +756,7 @@ p9_cme_stop_entry()
 
             do
             {
-                CME_GETSCOM(CPPM_CACSR, core, CME_SCOM_OR, scom_data.value);
+                CME_GETSCOM_OR(CPPM_CACSR, core, scom_data.value);
             }
             while(scom_data.words.upper & BIT32(13));
 
@@ -769,7 +769,7 @@ p9_cme_stop_entry()
             CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(22));
 
             PK_TRACE("Drop ABIST_SRAM_MODE_DC to support ABIST Recovery via BIST[1]");
-            CME_GETSCOM(C_BIST, core, CME_SCOM_AND, scom_data.value);
+            CME_GETSCOM(C_BIST, core, scom_data.value);
             scom_data.words.upper &= ~BIT32(1);
             CME_PUTSCOM(C_BIST, core, scom_data.value);
 
@@ -1066,7 +1066,7 @@ p9_cme_stop_entry()
 
                 do
                 {
-                    CME_GETSCOM(PPM_PFSNS, core, CME_SCOM_AND, scom_data.value);
+                    CME_GETSCOM_AND(PPM_PFSNS, core, scom_data.value);
                 }
                 while(!(scom_data.words.upper & BIT32(1)));
 
@@ -1274,19 +1274,18 @@ p9_cme_stop_entry()
 
             if (core & CME_MASK_C0)
             {
-                CME_GETSCOM(CPPM_CPMMR, CME_MASK_C0, CME_SCOM_AND, scom_data.value);
+                CME_GETSCOM(CPPM_CPMMR, CME_MASK_C0, scom_data.value);
 
                 if ((scom_data.words.upper & BIT32(13)))
                 {
                     PKTRACE("ERROR.A0: C0 notify was already set?");
                     pk_halt();
-
                 }
             }
 
             if (core & CME_MASK_C1)
             {
-                CME_GETSCOM(CPPM_CPMMR, CME_MASK_C1, CME_SCOM_AND, scom_data.value);
+                CME_GETSCOM(CPPM_CPMMR, CME_MASK_C1, scom_data.value);
 
                 if ((scom_data.words.upper & BIT32(13)))
                 {
@@ -1339,19 +1338,18 @@ p9_cme_stop_entry()
 
             if (core & CME_MASK_C0)
             {
-                CME_GETSCOM(CPPM_CPMMR, CME_MASK_C0, CME_SCOM_AND, scom_data.value);
+                CME_GETSCOM(CPPM_CPMMR, CME_MASK_C0, scom_data.value);
 
                 if (!(scom_data.words.upper & BIT32(13)))
                 {
                     PKTRACE("ERROR.B0: C0 notify fail to set");
                     pk_halt();
-
                 }
             }
 
             if (core & CME_MASK_C1)
             {
-                CME_GETSCOM(CPPM_CPMMR, CME_MASK_C1, CME_SCOM_AND, scom_data.value);
+                CME_GETSCOM(CPPM_CPMMR, CME_MASK_C1, scom_data.value);
 
                 if (!(scom_data.words.upper & BIT32(13)))
                 {
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
index 5c739f2e..cdff8d2e 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
@@ -68,7 +68,7 @@ void p9_cme_stop_exit_end(uint32_t core, uint32_t spwu_stop)
 
             if (G_cme_stop_record.act_level[core_index] != STOP_LEVEL_1)
             {
-                CME_GETSCOM(PPM_SSHSRC, core_mask, CME_SCOM_AND, scom_data.value);
+                CME_GETSCOM(PPM_SSHSRC, core_mask, scom_data.value);
                 act_stop_level = (scom_data.words.upper & BITS32(8, 4)) >> SHIFT32(11);
             }
             else
@@ -156,7 +156,7 @@ void p9_cme_stop_exit_end(uint32_t core, uint32_t spwu_stop)
     {
         if (core & core_mask)
         {
-            CME_GETSCOM(PPM_SSHSRC, core_mask, CME_SCOM_AND, scom_data.value);
+            CME_GETSCOM(PPM_SSHSRC, core_mask, scom_data.value);
 
             act_stop_level = (scom_data.words.upper & BITS32(8, 4)) >> SHIFT32(11);
             scom_data.words.upper = 0;
@@ -358,7 +358,7 @@ p9_cme_stop_exit_catchup(uint32_t* core,
     {
         if (core_catchup & core_mask)
         {
-            CME_GETSCOM(CPPM_CPMMR, core_mask, CME_SCOM_AND, scom_data.value);
+            CME_GETSCOM(CPPM_CPMMR, core_mask, scom_data.value);
 
             if (scom_data.words.upper & BIT32(13))
             {
@@ -440,7 +440,7 @@ p9_cme_stop_exit()
     {
         if (core & core_mask)
         {
-            CME_GETSCOM(CPPM_CPMMR, core_mask, CME_SCOM_AND, scom_data.value);
+            CME_GETSCOM(CPPM_CPMMR, core_mask, scom_data.value);
 
             if (scom_data.words.upper & BIT32(13))
             {
@@ -961,7 +961,7 @@ p9_cme_stop_exit()
 #endif
 
             PK_TRACE("Save off and mask SPATTN before self-restore");
-            CME_GETSCOM(SPATTN_MASK, core, CME_SCOM_AND, scom_data.value);
+            CME_GETSCOM(SPATTN_MASK, core, scom_data.value);
             CME_PUTSCOM(SPATTN_MASK, core, BITS64(0, 64));
 
             PK_TRACE_INF("SF.RS: Self Restore Kickoff, S-Reset All Core Threads");
@@ -1002,7 +1002,7 @@ p9_cme_stop_exit()
             CME_PUTSCOM(SPATTN_MASK, core, scom_data.value);
 
             PK_TRACE("Always Unfreeze IMA (by clearing bit 34) in case the CHTM is enabled to sample it");
-            CME_GETSCOM(IMA_EVENT_MASK, core, CME_SCOM_EQ, scom_data.value);
+            CME_GETSCOM(IMA_EVENT_MASK, core, scom_data.value);
             CME_PUTSCOM(IMA_EVENT_MASK, core, scom_data.value & ~BIT64(34));
 
             PK_TRACE("Drop block interrupt to PC via SICR[2/3]");
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
index e20fe42f..da444382 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c
@@ -49,7 +49,7 @@ p9_cme_stop_pcwu_handler(void* arg, PkIrqId irq)
     {
         if (core & core_mask)
         {
-            CME_GETSCOM(CPPM_CPMMR, core_mask, CME_SCOM_AND, scom_data.value);
+            CME_GETSCOM(CPPM_CPMMR, core_mask, scom_data.value);
 
             // If notify_select == sgpe
             if (scom_data.words.upper & BIT32(13))
@@ -125,7 +125,7 @@ p9_cme_stop_spwu_handler(void* arg, PkIrqId irq)
                     PK_TRACE("SPWU drop confirmed, now dropping spwu_done");
                     out32(CME_LCL_SICR_CLR, BIT32((16 + core_index)));
 
-                    CME_GETSCOM(PPM_GPMMR, core_mask, CME_SCOM_AND, scom_data);
+                    CME_GETSCOM(PPM_GPMMR, core_mask, scom_data);
 
                     // if spwu has been re-asserted after spwu_done is dropped:
                     if (scom_data & BIT64(1))
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c
index 72011bc2..e7527619 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c
@@ -49,7 +49,7 @@ p9_hcd_core_arrayinit(uint32_t core)
     CME_PUTSCOM(PERV_CPLT_CTRL0_OR, core, BIT64(0));
 
     PK_TRACE("setup ABIST modes");
-    CME_GETSCOM(PERV_BIST, core, CME_SCOM_AND, scom_data);
+    CME_GETSCOM(PERV_BIST, core, scom_data);
     scom_data &= ~BIT64(0);
     scom_data |=  BIT64(1);     // select_sram  = 1
     scom_data &= ~BIT64(2);     // select_edram = 0
@@ -57,7 +57,7 @@ p9_hcd_core_arrayinit(uint32_t core)
     CME_PUTSCOM(PERV_BIST, core, scom_data);
 
     PK_TRACE("Setup all Clock Domains and Clock Types");
-    CME_GETSCOM(PERV_CLK_REGION, core, CME_SCOM_AND, scom_data);
+    CME_GETSCOM(PERV_CLK_REGION, core, scom_data);
     scom_data |= (BITS64(4, 11) | BITS64(48, 3));// regions = 0x7FF
     CME_PUTSCOM(PERV_CLK_REGION, core, scom_data);
 
@@ -65,18 +65,18 @@ p9_hcd_core_arrayinit(uint32_t core)
     CME_PUTSCOM(PERV_CPLT_CTRL1_CLEAR, core, BITS64(4, 11));
 
     PK_TRACE("Setup: loopcount , OPCG engine start ABIST, run-N mode");
-    CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_AND, scom_data);
+    CME_GETSCOM(PERV_OPCG_REG0, core, scom_data);
     scom_data |=  0x80020000000012B8;
     // b0 = 1 b14 = 1 loop_counter = 0x12B8(Parallel mode)
     CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data);
 
     PK_TRACE("Setup IDLE count");
-    CME_GETSCOM(PERV_OPCG_REG1, core, CME_SCOM_AND, scom_data);
+    CME_GETSCOM(PERV_OPCG_REG1, core, scom_data);
     scom_data |= 0x0000000F00000000; //scan_count|misr_a_valur|misr_b_value
     CME_PUTSCOM(PERV_OPCG_REG1, core, scom_data);
 
     PK_TRACE("opcg go");
-    CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_AND, scom_data);
+    CME_GETSCOM(PERV_OPCG_REG0, core, scom_data);
     scom_data |= BIT64(1);
     CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data);
 
@@ -84,12 +84,12 @@ p9_hcd_core_arrayinit(uint32_t core)
 
     do
     {
-        CME_GETSCOM(PERV_CPLT_STAT0, core, CME_SCOM_AND, scom_data);
+        CME_GETSCOM_AND(PERV_CPLT_STAT0, core, scom_data);
     }
     while(!(scom_data & BIT64(8)));
 
     PK_TRACE("OPCG done, clear Run-N mode");
-    CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_AND, scom_data);
+    CME_GETSCOM(PERV_OPCG_REG0, core, scom_data);
     scom_data &= ~(BIT64(0) | BIT64(14) | BITS64(21, 43));
     CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data);
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
index 41f749e3..9f16f781 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
@@ -96,7 +96,7 @@ p9_hcd_core_chiplet_reset(uint32_t core)
     // so it will introduce an additional 2:1 into whatever scan raito is set up. Hence,
     // to get the core to scan at 4:1, need to put a scan ratio of 2:1 if run at pll speed.
     PK_TRACE("Set scan ratio to 2:1 in non-bypass mode via OPCG_ALIGN[47-51]");
-    CME_GETSCOM(C_OPCG_ALIGN, core, CME_SCOM_AND, scom_data.value);
+    CME_GETSCOM(C_OPCG_ALIGN, core, scom_data.value);
     scom_data.words.lower &= ~BITS64SH(47, 5);
 #if !EPM_P9_TUNING
     scom_data.words.lower |= BIT32(19);
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c
index 372e3198..0fbc2728 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c
@@ -63,7 +63,7 @@ p9_hcd_core_poweron(uint32_t core)
 
         do
         {
-            CME_GETSCOM(PPM_PFCS, CME_MASK_C0, CME_SCOM_AND, scom_data);
+            CME_GETSCOM(PPM_PFCS, CME_MASK_C0, scom_data);
         }
         while(!(scom_data & BIT64(42)));
     }
@@ -78,7 +78,7 @@ p9_hcd_core_poweron(uint32_t core)
 
         do
         {
-            CME_GETSCOM(PPM_PFSNS, CME_MASK_C1, CME_SCOM_AND, scom_data);
+            CME_GETSCOM(PPM_PFSNS, CME_MASK_C1, scom_data);
         }
         while(!(scom_data & BIT64(0)));
     }
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c
index 62ad66df..a103e6b4 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scan0.c
@@ -55,7 +55,7 @@ p9_hcd_core_scan0(uint32_t core, uint64_t regions, uint64_t scan_type)
     CME_PUTSCOM(PERV_CPLT_CTRL1_OR,  core, BITS64(4, 11));
 
     PK_TRACE("Setup all Clock Domains and Clock Types");
-    CME_GETSCOM(PERV_CLK_REGION, core, CME_SCOM_AND, scom_data);
+    CME_GETSCOM(PERV_CLK_REGION, core, scom_data);
     scom_data |= ((regions << SHIFT64(14)) | BITS64(48, 3));
     CME_PUTSCOM(PERV_CLK_REGION, core, scom_data);
 
@@ -64,12 +64,12 @@ p9_hcd_core_scan0(uint32_t core, uint64_t regions, uint64_t scan_type)
     CME_PUTSCOM(PERV_SCAN_REGION_TYPE, core, scom_data);
 
     PK_TRACE("set OPCG_REG0 register bit 0='0'");
-    CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_AND, scom_data);
+    CME_GETSCOM(PERV_OPCG_REG0, core, scom_data);
     scom_data &= ~BIT64(0);
     CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data);
 
     PK_TRACE("Setting SCAN0 Mode");
-    CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_AND, scom_data);
+    CME_GETSCOM(PERV_OPCG_REG0, core, scom_data);
     scom_data |= BIT64(3);
     CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data);
 
@@ -88,7 +88,7 @@ p9_hcd_core_scan0(uint32_t core, uint64_t regions, uint64_t scan_type)
     CME_PUTSCOM(PERV_OPCG_REG1, core, scom_data);
 
     PK_TRACE("Trigger OPCG GO");
-    CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_AND, scom_data);
+    CME_GETSCOM(PERV_OPCG_REG0, core, scom_data);
     scom_data |= BIT64(1);
     CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data);
 
@@ -96,17 +96,17 @@ p9_hcd_core_scan0(uint32_t core, uint64_t regions, uint64_t scan_type)
 
     do
     {
-        CME_GETSCOM(PERV_CPLT_STAT0, core, CME_SCOM_AND, scom_data);
+        CME_GETSCOM_AND(PERV_CPLT_STAT0, core, scom_data);
     }
     while(!(scom_data & BIT64(8)));
 
     PK_TRACE("Clearing SCAN0 Mode");
-    CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_AND, scom_data);
+    CME_GETSCOM(PERV_OPCG_REG0, core, scom_data);
     scom_data &= ~BIT64(3);
     CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data);
 
     PK_TRACE("Clearing scan length count");
-    CME_GETSCOM(PERV_OPCG_REG1, core, CME_SCOM_AND, scom_data);
+    CME_GETSCOM(PERV_OPCG_REG1, core, scom_data);
     scom_data &=  ~BITS64(0, 12);
     CME_PUTSCOM(PERV_OPCG_REG1, core, scom_data);
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c
index d082ca7e..8d852035 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_scominit.c
@@ -50,12 +50,12 @@ p9_hcd_core_scominit(uint32_t core)
 
     // how about bit 6?
     PK_TRACE("Restore SYNC_CONFIG[8] for stop1");
-    CME_GETSCOM(C_SYNC_CONFIG, core, CME_SCOM_AND, scom_data.value);
+    CME_GETSCOM(C_SYNC_CONFIG, core, scom_data.value);
     scom_data.words.upper |= BIT32(8);
     CME_PUTSCOM(C_SYNC_CONFIG, core, scom_data.value);
 
     PK_TRACE("Enable DTS via THERM_MODE_REG[5,6-9,20-21]");
-    CME_GETSCOM(C_THERM_MODE_REG, core, CME_SCOM_AND, scom_data.value);
+    CME_GETSCOM(C_THERM_MODE_REG, core, scom_data.value);
     scom_data.words.upper |= BIT32(5);     // DTS sampling enable
     scom_data.words.upper |= BITS32(6, 4); // sample pulse count
     scom_data.words.upper |= BITS32(20, 2);// DTS loop1 enable
@@ -68,7 +68,7 @@ p9_hcd_core_scominit(uint32_t core)
     CME_PUTSCOM(CORE_FIRMASK, core, 0x0301D70000AB76B6);
 
     PK_TRACE("Update Core Hang Pulse Dividers via C_HANG_CONTROL[0-15]");
-    CME_GETSCOM(C_HANG_CONTROL, core, CME_SCOM_AND, scom_data.value);
+    CME_GETSCOM(C_HANG_CONTROL, core, scom_data.value);
     scom_data.words.upper &= ~BITS32(0, 16);
 #if NIMBUS_DD_LEVEL == 1
     scom_data.words.upper |= (CORE_HANG_LIMIT_100_HANG_PULSES << SHIFT32(7));
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
index 72038d07..296d0a56 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c
@@ -29,6 +29,7 @@
 void
 p9_hcd_core_startclocks(uint32_t core)
 {
+    uint32_t     core_mask  = 0;
     data64_t     scom_data  = {0};
     cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_HEADER_ADDR);
     uint32_t     id_vector  = pCmeImgHdr->g_cme_location_id;
@@ -37,7 +38,7 @@ p9_hcd_core_startclocks(uint32_t core)
     CME_PUTSCOM(C_CPLT_CONF0_OR, core, BIT64(34));
 
     PK_TRACE("Set inop_align/wait/wait_cycles via OPCG_ALIGN[0-3,12-19,52-63]");
-    CME_GETSCOM(C_OPCG_ALIGN, core, CME_SCOM_AND, scom_data.value);
+    CME_GETSCOM_AND(C_OPCG_ALIGN, core, scom_data.value);
     scom_data.value &= ~(BITS64(0, 4) | BITS64(12, 8) | BITS64(52, 12));
     scom_data.value |=  (BIT64(1) | BIT64(3) | BIT64(59));
     CME_PUTSCOM(C_OPCG_ALIGN, core, scom_data.value);
@@ -58,14 +59,14 @@ p9_hcd_core_startclocks(uint32_t core)
 
     do
     {
-        CME_GETSCOM(CPPM_CACSR, core, CME_SCOM_AND, scom_data.value);
+        CME_GETSCOM_AND(CPPM_CACSR, core, scom_data.value);
     }
     while((~(scom_data.words.upper)) & BIT32(13));
 
     MARK_TRAP(SX_STARTCLOCKS_ALIGN)
 
     PK_TRACE("Assert ABIST_SRAM_MODE_DC to support ABIST Recovery via BIST[1]");
-    CME_GETSCOM(C_BIST, core, CME_SCOM_AND, scom_data.value);
+    CME_GETSCOM(C_BIST, core, scom_data.value);
     scom_data.words.upper |= BIT32(1);
     CME_PUTSCOM(C_BIST, core, scom_data.value);
 
@@ -73,7 +74,7 @@ p9_hcd_core_startclocks(uint32_t core)
     CME_PUTSCOM(C_CPLT_CTRL0_CLEAR, core, BITS64(0, 2));
 
     PK_TRACE("Set fabric chiplet ID values via EQ_CPLT_CONF0[48-51,52-54,56-60]");
-    CME_GETSCOM(C_CPLT_CONF0, core, CME_SCOM_AND, scom_data.value);
+    CME_GETSCOM(C_CPLT_CONF0, core, scom_data.value);
     scom_data.words.lower &= ~(BITS64SH(48, 7) | BITS64SH(56, 5));
     scom_data.words.lower |= id_vector;
     CME_PUTSCOM(C_CPLT_CONF0, core, scom_data.value);
@@ -87,7 +88,7 @@ p9_hcd_core_startclocks(uint32_t core)
     CME_PUTSCOM(C_CPLT_CTRL0_OR, core, BIT64(3));
 
     PK_TRACE("Set then unset clear_chiplet_is_aligned via SYNC_CONFIG[7]");
-    CME_GETSCOM(C_SYNC_CONFIG, core, CME_SCOM_AND, scom_data.value);
+    CME_GETSCOM(C_SYNC_CONFIG, core, scom_data.value);
     scom_data.words.upper |=  BITS32(7, 2);
     CME_PUTSCOM(C_SYNC_CONFIG, core, scom_data.value);
     scom_data.words.upper &= ~BIT32(7);
@@ -100,7 +101,7 @@ p9_hcd_core_startclocks(uint32_t core)
 
     do
     {
-        CME_GETSCOM(C_CPLT_STAT0, core, CME_SCOM_AND, scom_data.value);
+        CME_GETSCOM_AND(C_CPLT_STAT0, core, scom_data.value);
     }
     while((~(scom_data.words.upper)) & BIT32(9));
 
@@ -122,12 +123,12 @@ p9_hcd_core_startclocks(uint32_t core)
 
     do
     {
-        CME_GETSCOM(C_CPLT_STAT0, core, CME_SCOM_AND, scom_data.value);
+        CME_GETSCOM_AND(C_CPLT_STAT0, core, scom_data.value);
     }
     while((~(scom_data.words.upper)) & BIT32(8));
 
     PK_TRACE("Check core clock is running via CLOCK_STAT_SL[4-13]");
-    CME_GETSCOM(C_CLOCK_STAT_SL, core, CME_SCOM_AND, scom_data.value);
+    CME_GETSCOM_OR(C_CLOCK_STAT_SL, core, scom_data.value);
 
     if(scom_data.value & CLK_REGION_ALL_BUT_PLL)
     {
@@ -143,14 +144,20 @@ p9_hcd_core_startclocks(uint32_t core)
 
 #if !EPM_P9_TUNING
 
-    PK_TRACE("Check Global Xstop FIR of Core Chiplet");
-    CME_GETSCOM(C_XFIR, core, CME_SCOM_AND, scom_data.value);
-
-    if (scom_data.words.upper & BITS32(0, 27))
+    for(core_mask = 2; core_mask; core_mask--)
     {
-        PK_TRACE_ERR("Core[%d] Chiplet Global Xstop FIR[%x] Detected. HALT CME!",
-                     core, scom_data.words.upper);
-        PK_PANIC(CME_STOP_EXIT_XSTOP_ERROR);
+        if (core & core_mask)
+        {
+            PK_TRACE("Check Global Xstop FIR of Core Chiplet");
+            CME_GETSCOM(C_XFIR, core_mask, scom_data.value);
+
+            if (scom_data.words.upper & BITS32(0, 27))
+            {
+                PK_TRACE_ERR("Core[%d] Chiplet Global Xstop FIR[%x] Detected. HALT CME!",
+                             core_mask, scom_data.words.upper);
+                PK_PANIC(CME_STOP_EXIT_XSTOP_ERROR);
+            }
+        }
     }
 
 #endif
diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c
index 673ed131..8d186806 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c
@@ -233,7 +233,7 @@ void queuedScan(enum CME_CORE_MASKS i_core,
                     l_scomAddress = 0x00038000 | l_rotateCount;
                 }
 
-                CME_GETSCOM(l_scomAddress, i_core, i_scom_op, i_scanData);
+                CME_GETSCOM_OP(l_scomAddress, i_core, i_scom_op, i_scanData);
             }// end of for loop
         }
         else if(SCAN == i_operation)
@@ -602,7 +602,7 @@ int rs4DecompressionSvc(
             l_scomOp = CME_SCOM_NOP;
         }
 
-        CME_GETSCOM(0x0003E000, i_core, l_scomOp, l_readHeader);
+        CME_GETSCOM_OP(0x0003E000, i_core, l_scomOp, l_readHeader);
 
         if(l_readHeader != 0xa5a5a5a5a5a5a5a5)
         {