diff options
| author | Yue Du <daviddu@us.ibm.com> | 2016-03-24 15:26:30 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 16:01:17 -0500 |
| commit | f984fe919217e83fb078daa972ddb70887d6703c (patch) | |
| tree | b5906a08cc0a9ca372264d1eb09b8a346eef5dca | |
| parent | 59f2dd0296da531e82aa91594b43a8a9e3893233 (diff) | |
| download | talos-hcode-f984fe919217e83fb078daa972ddb70887d6703c.tar.gz talos-hcode-f984fe919217e83fb078daa972ddb70887d6703c.zip | |
CME/SGPE: update stop cme/sgpe images
Change-Id: I9c2de4e90e7445d123290de37fff9e26dae2d1ae
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22464
Tested-by: Jenkins Server
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
31 files changed, 791 insertions, 632 deletions
diff --git a/import/chips/p9/common/pmlib/include/cmehw_interrupts.h b/import/chips/p9/common/pmlib/include/cmehw_interrupts.h index 2b96d961..44a8990e 100644 --- a/import/chips/p9/common/pmlib/include/cmehw_interrupts.h +++ b/import/chips/p9/common/pmlib/include/cmehw_interrupts.h @@ -203,18 +203,18 @@ CMEHW_IRQ_BCE_TIMEOUT STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ CMEHW_IRQ_DOORBELL3_C0 STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ CMEHW_IRQ_DOORBELL3_C1 STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ - CMEHW_IRQ_PC_INTR_PENDING_C0 STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ - CMEHW_IRQ_PC_INTR_PENDING_C1 STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ - CMEHW_IRQ_REG_WAKEUP_C0 STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ - CMEHW_IRQ_REG_WAKEUP_C1 STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ - CMEHW_IRQ_SPECIAL_WAKEUP_C0 STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ - CMEHW_IRQ_SPECIAL_WAKEUP_C1 STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ + CMEHW_IRQ_PC_INTR_PENDING_C0 STD_IRQ_TYPE_LEVEL STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ + CMEHW_IRQ_PC_INTR_PENDING_C1 STD_IRQ_TYPE_LEVEL STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ + CMEHW_IRQ_REG_WAKEUP_C0 STD_IRQ_TYPE_LEVEL STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ + CMEHW_IRQ_REG_WAKEUP_C1 STD_IRQ_TYPE_LEVEL STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ + CMEHW_IRQ_SPECIAL_WAKEUP_C0 STD_IRQ_TYPE_LEVEL STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ + CMEHW_IRQ_SPECIAL_WAKEUP_C1 STD_IRQ_TYPE_LEVEL STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ CMEHW_IRQ_DOORBELL2_C0 STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ CMEHW_IRQ_DOORBELL2_C1 STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ - CMEHW_IRQ_PC_PM_STATE_ACTIVE_C0 STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ - CMEHW_IRQ_PC_PM_STATE_ACTIVE_C1 STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ - CMEHW_IRQ_L2_PURGE_DONE STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ - CMEHW_IRQ_NCU_PURGE_DONE STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ + CMEHW_IRQ_PC_PM_STATE_ACTIVE_C0 STD_IRQ_TYPE_LEVEL STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ + CMEHW_IRQ_PC_PM_STATE_ACTIVE_C1 STD_IRQ_TYPE_LEVEL STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ + CMEHW_IRQ_L2_PURGE_DONE STD_IRQ_TYPE_LEVEL STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ + CMEHW_IRQ_NCU_PURGE_DONE STD_IRQ_TYPE_LEVEL STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ CMEHW_IRQ_CHTM_PURGE_DONE_C0 STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ CMEHW_IRQ_CHTM_PURGE_DONE_C1 STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ CMEHW_IRQ_BCE_BUSY_LOW STD_IRQ_TYPE_EDGE STD_IRQ_POLARITY_RISING STD_IRQ_MASKED \ diff --git a/import/chips/p9/common/pmlib/include/gpehw_common.h b/import/chips/p9/common/pmlib/include/gpehw_common.h index 8825d1b3..d0d01d76 100644 --- a/import/chips/p9/common/pmlib/include/gpehw_common.h +++ b/import/chips/p9/common/pmlib/include/gpehw_common.h @@ -71,9 +71,9 @@ enum GPE_SCOM_ADDRESS_PARAMETERS CORE_ADDR_OFFSET = 0x01000000, QUAD_ADDR_BASE = 0x10000000, QUAD_ADDR_OFFSET = 0x01000000, - EX_ADDR_BASE = 0x00000800, - EX0_ADDR_OFFSET = 0x00000800, - EX1_ADDR_OFFSET = 0x00000C00, + EX_ADDR_BASE = 0x10011000, + EX0_ADDR_OFFSET = 0x00000000, + EX1_ADDR_OFFSET = 0x00000400, CME_ADDR_BASE = 0x10012000, CME0_ADDR_OFFSET = 0x00000000, CME1_ADDR_OFFSET = 0x00000400 diff --git a/import/chips/p9/common/pmlib/include/p9_stop_common.h b/import/chips/p9/common/pmlib/include/p9_stop_common.h index 9fac87f8..f0a1a09d 100644 --- a/import/chips/p9/common/pmlib/include/p9_stop_common.h +++ b/import/chips/p9/common/pmlib/include/p9_stop_common.h @@ -31,13 +31,15 @@ enum P9_HCD_COMMON_INIT_VECTORS // (3)PLL_TEST_EN // (4)PLLRST // (5)PLLBYP + // (11)EDIS // (12)VITL_MPW1 // (13)VITL_MPW2 // (14)VITL_MPW3 // (18)FENCE_EN // (22)FUNC_CLKSEL // (26)LVLTRANS_FENCE - NET_CTRL0_INIT_VECTOR = (BITS64(1, 5) | BITS64(3, 3) | BIT64(18) | BIT64(22) | BIT64(26)), + C_NET_CTRL0_INIT_VECTOR = (BIT64(1) | BITS64(3, 3) | BITS64(11, 4) | BIT64(18) | BIT64(22) | BIT64(26)), + Q_NET_CTRL0_INIT_VECTOR = (BITS64(1, 5) | BITS64(11, 4) | BIT64(18) | BIT64(22) | BIT64(26)), HANG_PULSE1_INIT_VECTOR = BIT64(5) }; diff --git a/import/chips/p9/common/pmlib/include/ppehw_common.h b/import/chips/p9/common/pmlib/include/ppehw_common.h index cf9353ea..382f3eee 100644 --- a/import/chips/p9/common/pmlib/include/ppehw_common.h +++ b/import/chips/p9/common/pmlib/include/ppehw_common.h @@ -55,12 +55,18 @@ #define CODE2REGA(code) ((code & 0x1F00) >> 8) #define CODE2REGB(code) ((code & 0xF8) >> 3) -#define CODE2TAG(code,tag) ((tag << 10) | (code >> 3)) +#define CODE2TAG(code,tag) ((tag << 8) | (code >> 3)) #define TAG_SPRG0(tag) {ppe42_app_ctx_set(tag);} + +#if EPM_P9_TUNING #define MARK_TRAP(code) \ {asm volatile ("tw 0, %0, %1" : : \ "i" (CODE2REGA(code)), \ "i" (CODE2REGB(code)));} +#else +#define MARK_TRAP(code) +#endif + #define MARK_TAG(code, tag) \ TAG_SPRG0(CODE2TAG(code, tag)) \ MARK_TRAP(code) diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c index 92512c7e..41da93b7 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c +++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_irq.c @@ -178,6 +178,6 @@ void pk_unified_irq_prty_mask_handler(void) l_vecL = 0; asm volatile ("lvd %[data], 0(%[addr]) \n" \ : [data]"=r"(l_vecH) \ - : [addr]"r"(&ext_irq_vectors_cme[iPrtyLvl][IDX_PRTY_VEC]) ); + : [addr]"r"(&ext_irq_vector_pk) ); } diff --git a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h index 0bb06884..0f478706 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h +++ b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h @@ -34,7 +34,6 @@ /// \brief Application specific overrides go here. /// -#define EPM_P9_LEVEL 1 #define STOP_PRIME 0 #define SKIP_ABORT 0 #define SKIP_L2_PURGE_ABORT 0 @@ -44,13 +43,18 @@ #define SKIP_INITF 0 #define SKIP_ARY_INIT 0 #define SKIP_SELF_RESTORE 0 +#define SKIP_BCE 1 // -------------------- #define EPM_P9_TUNING 1 -#define SIMICS_TUNING 1 -#define DEV_DEBUG 1 +#define SIMICS_TUNING 0 #define USE_SIMICS_IO 0 +#define DEV_DEBUG 1 + +#if EPM_P9_TUNING + #define PK_TRACE_BUFFER_WRAP_MARKER 1 +#endif #define PK_TRACE_TIMER_OUTPUT 0 // -------------------- diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h index 2378fbed..e2f1bdb4 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h @@ -44,18 +44,7 @@ #include "cppm_firmware_registers.h" #include "p9_stop_common.h" -/* -/// Compiler flags -#define EPM_P9_LEVEL 1 -#define SKIP_ABORT 1 -#define SKIP_L2_PURGE_ABORT 1 -#define SKIP_CATCHUP 1 -#define STOP_PRIME 0 -#define SKIP_SCAN0 0 -#define SKIP_INITF 0 -#define SKIP_ARY_INIT 0 -#define SKIP_SELF_RESTORE 0 -*/ + /// handcoded addresses TO BE REMOVED #define THREAD_INFO 0x20010A9B @@ -139,6 +128,13 @@ enum CME_STOP_FLAGS }; +enum CME_STOP_PIG_TYPES +{ + PIG_TYPE2 = 2, + PIG_TYPE3 = 3 +}; + + /// Stop Score Board Structure typedef struct { diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_enter_marks.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_enter_marks.h index 6e411ccd..ec8a950c 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_enter_marks.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_enter_marks.h @@ -36,31 +36,27 @@ namespace CME_STOP_ENTRY_MARKS enum CME_SE_MARKS { - SE_POLL_PCBMUX_GRANT = 0x0, - SE_QUIESCE_CORE_INTF = 0x8, - SE_STOP_CORE_CLKS = 0x10, - SE_STOP_CORE_GRID = 0x18, - SE_STOP2_DONE = 0x20, - SE_IS0_BEGIN = 0x28, - SE_IS0_END = 0x30, - SE_CATCHUP = 0x38, - SE_CORE_VMIN = 0x40, - SE_STOP3_DONE = 0x48, - SE_POWER_OFF_CORE = 0x50, - SE_STOP4_DONE = 0x68, - SE_IS1_BEGIN = 0xe0, - SE_IS1_END = 0xe8, - SE_PURGE_L2 = 0xf0, - SE_IS2_BEGIN = 0xf8, - SE_PURGE_L2_ABORT = 0x100, - SE_PURGE_L2_ABORT_DONE = 0x108, - SE_IS2_END = 0x110, - SE_PURGE_L2_DONE = 0x118, - SE_SGPE_HANDOFF = 0x120, - BEGINSCOPE_STOP_ENTRY = 0x1f08, - ENDSCOPE_STOP_ENTRY = 0x1f10, - STOP_EVENT_HANDLER = 0x1f18, - STOP_DOORBELL_HANDLER = 0x1f20 + BEGINSCOPE_STOP_ENTRY = 0x0, + ENDSCOPE_STOP_ENTRY = 0x8, + STOP_EVENT_HANDLER = 0x10, + STOP_DOORBELL_HANDLER = 0x18, + SE_QUIESCE_CORE_INTF = 0x68, + SE_STOP_CORE_CLKS = 0xe0, + SE_STOP_CORE_GRID = 0xe8, + SE_STOP2_DONE = 0xf0, + SE_IS0_BEGIN = 0xf8, + SE_IS0_END = 0x100, + SE_CATCHUP = 0x108, + SE_CORE_VMIN = 0x110, + SE_STOP3_DONE = 0x118, + SE_POWER_OFF_CORE = 0x120, + SE_STOP4_DONE = 0x128, + SE_IS1_BEGIN = 0x130, + SE_IS1_END = 0x138, + SE_PURGE_L2 = 0x140, + SE_PURGE_L2_ABORT = 0x148, + SE_PURGE_L2_DONE = 0x150, + SE_SGPE_HANDOFF = 0x168 }; @@ -68,7 +64,10 @@ enum CME_SE_MARKS const std::vector<CME_SE_MARKS> MARKS = { - SE_POLL_PCBMUX_GRANT, + BEGINSCOPE_STOP_ENTRY, + ENDSCOPE_STOP_ENTRY, + STOP_EVENT_HANDLER, + STOP_DOORBELL_HANDLER, SE_QUIESCE_CORE_INTF, SE_STOP_CORE_CLKS, SE_STOP_CORE_GRID, @@ -83,16 +82,9 @@ const std::vector<CME_SE_MARKS> MARKS = SE_IS1_BEGIN, SE_IS1_END, SE_PURGE_L2, - SE_IS2_BEGIN, SE_PURGE_L2_ABORT, - SE_PURGE_L2_ABORT_DONE, - SE_IS2_END, SE_PURGE_L2_DONE, - SE_SGPE_HANDOFF, - BEGINSCOPE_STOP_ENTRY, - ENDSCOPE_STOP_ENTRY, - STOP_EVENT_HANDLER, - STOP_DOORBELL_HANDLER + SE_SGPE_HANDOFF }; } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index a82af15c..3bc44a6d 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -92,6 +92,7 @@ p9_cme_stop_entry() // Return error if None of both fired if (!core) { + PK_TRACE("Error: no pm_active fired"); pk_halt(); } @@ -139,7 +140,6 @@ p9_cme_stop_entry() } G_cme_stop_record.core_running &= ~core; - out32(CME_LCL_LMCR_OR, (core << SHIFT32(15))); PK_TRACE("SE1: Request Stop Levels[%d %d]", G_cme_stop_record.req_level_c0, @@ -154,6 +154,7 @@ p9_cme_stop_entry() (G_cme_stop_record.req_level_c0 <= STOP_LEVEL_1 || G_cme_stop_record.req_level_c1 <= STOP_LEVEL_1))) { + PK_TRACE("Error: stop 1 requested to hcode"); pk_halt(); } @@ -216,12 +217,6 @@ p9_cme_stop_entry() PK_TRACE("SE2: target_lv[%d], deeper_lv[%d], deeper_core[%d]", target_level, deeper_level, deeper_core); - //============================= - MARK_TRAP(SE_POLL_PCBMUX_GRANT) - //============================= - - PK_TRACE("SE2.f"); - // Poll Infinitely for PCB Mux Grant // MF: change watchdog timer in pk to ensure forward progress while((core & (in32(CME_LCL_SISR) >> SHIFT32(11))) != core); @@ -237,7 +232,8 @@ p9_cme_stop_entry() out32(CME_LCL_SICR_OR, core << SHIFT32(1)); out32(CME_LCL_SICR_CLR, core << SHIFT32(1)); - /// @todo Set LMCR bits 14 and/or 15 (override disables) + /// Set LMCR bits 12/13, 14/15 (override disables) + out32(CME_LCL_LMCR_OR, ((core << SHIFT32(13)) | (core << SHIFT32(15)))); PK_TRACE("SE2.h"); // Raise Core-L2 + Core-CC Quiesces @@ -306,6 +302,8 @@ p9_cme_stop_entry() // Switch glsmux to refclk to save clock grid power CME_PUTSCOM(C_PPM_CGCR, core, 0); + // Assert skew sense to skewadjust Fence + CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(22)); // Assert Vital Fence CME_PUTSCOM(C_CPLT_CTRL1_OR, core, BIT64(3)); // Assert Regional Fences @@ -720,10 +718,6 @@ p9_cme_stop_entry() // Poll for Purged Done PK_TRACE("SE5.1b"); - //=========================== - MARK_TRAP(SE_IS2_BEGIN) - //=========================== - do { #if !SKIP_L2_PURGE_ABORT @@ -742,10 +736,6 @@ p9_cme_stop_entry() } while((in32(CME_LCL_EISR) & BITS32(22, 2)) != BITS32(22, 2)); - //=================== - MARK_TRAP(SE_IS2_END) - //=================== - // Deassert L2+NCU Purges, their possible aborts, NCU tlbie quiesce PK_TRACE("SE5.1c"); out32(CME_LCL_SICR_CLR, BITS32(18, 6)); @@ -773,10 +763,20 @@ p9_cme_stop_entry() // Send PCB Interrupt per core PK_TRACE("SE5.2b"); - pig.fields.req_intr_type = 2; //0b010: STOP State Change if (core & CME_MASK_C0) { + if (G_cme_stop_record.req_level_c0 < STOP_LEVEL_11) + { + CME_PUTSCOM(CPPM_CPMMR_OR, CME_MASK_C0, BIT64(10)); + pig.fields.req_intr_type = PIG_TYPE3; + } + else + { + CME_PUTSCOM(CPPM_CPMMR_CLR, CME_MASK_C0, BIT64(10)); + pig.fields.req_intr_type = PIG_TYPE2; + } + pig.fields.req_intr_payload = G_cme_stop_record.req_level_c0; CME_PUTSCOM(PPM_PIG, CME_MASK_C0, pig.value); G_cme_stop_record.core_stopgpe |= core; @@ -785,6 +785,17 @@ p9_cme_stop_entry() if (core & CME_MASK_C1) { + if (G_cme_stop_record.req_level_c1 < STOP_LEVEL_11) + { + CME_PUTSCOM(CPPM_CPMMR_OR, CME_MASK_C1, BIT64(10)); + pig.fields.req_intr_type = PIG_TYPE3; + } + else + { + CME_PUTSCOM(CPPM_CPMMR_CLR, CME_MASK_C1, BIT64(10)); + pig.fields.req_intr_type = PIG_TYPE2; + } + pig.fields.req_intr_payload = G_cme_stop_record.req_level_c1; CME_PUTSCOM(PPM_PIG, CME_MASK_C1, pig.value); G_cme_stop_record.core_stopgpe |= core; diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c index dcde15aa..c38399a7 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c @@ -56,6 +56,7 @@ p9_cme_stop_exit() // extract wakeup signals, clear status, and mask wakeup interrupts wakeup = (in32(CME_LCL_EISR) >> SHIFT32(17)) & 0x3F; out32(CME_LCL_EISR_CLR, (wakeup << SHIFT32(17)) | BITS32(24, 2)); + out32_sh(CME_LCL_EISR_CLR, (in32_sh(CME_LCL_EISR) & BITS32(8, 2))); // build the core select for wakeup pcwu = (wakeup >> 4) & CME_MASK_BC; @@ -72,6 +73,7 @@ p9_cme_stop_exit() // Code Error: function should never be entered without wakeup source active if (!core) { + PK_TRACE("Error: no wakeup fired"); pk_halt(); } @@ -146,16 +148,12 @@ p9_cme_stop_exit() // STOP LEVEL 4 //-------------------------------------------------------------------------- - //====================== - MARK_TAG(SX_STOP3, core) - //====================== - - if (deeper_level >= 4) + if (deeper_level >= STOP_LEVEL_4) { PK_TRACE("STOP Level 4+ Sequence"); // if deeper_core is set, then core must be 0b11 - if (deeper_core && target_level < 4) + if (deeper_core && target_level < STOP_LEVEL_4) { d2u4_flag = 1; core = deeper_core; @@ -164,10 +162,11 @@ p9_cme_stop_exit() do //catchup loop { +#if !SKIP_BCE PK_TRACE("BCE Runtime Kickoff"); - //right now a blocking call. Need to confirm this. instance_scan_init(); +#endif // todo for catch up case //PK_TRACE("X1: Request PCB Arbiter"); @@ -331,7 +330,19 @@ p9_cme_stop_exit() } } - // todo STOP LEVEL 3 + //-------------------------------------------------------------------------- + // STOP LEVEL 3 + //-------------------------------------------------------------------------- + if (deeper_level == STOP_LEVEL_3 || target_level == STOP_LEVEL_3) + { + //====================== + MARK_TAG(SX_STOP3, core) + //====================== + + PK_TRACE("STOP Level 3 Sequence"); + //Return to full voltage + //disable ivrm? + } //-------------------------------------------------------------------------- // STOP LEVEL 2 @@ -351,7 +362,7 @@ p9_cme_stop_exit() // STOP LEVEL 4 //-------------------------------------------------------------------------- - if (deeper_level >= 4) + if (deeper_level >= STOP_LEVEL_4) { PK_TRACE("STOP Level 4+ Sequence"); @@ -370,14 +381,19 @@ p9_cme_stop_exit() //========================== MARK_TAG(SX_BCE_CHECK, core) - //========================== + +#if !SKIP_BCE + PK_TRACE("BCE Runtime Check"); + if( BLOCK_COPY_SUCCESS != isScanRingCopyDone() ) { PK_TRACE("BC2: Copy of Instance Specific Scan ring failed"); // TODO should return an error code. } +#endif + // todo //PK_TRACE("X11: XIP Customized Scoms"); //MARK_TRAP(SX_SCOMCUST) @@ -406,10 +422,6 @@ p9_cme_stop_exit() PK_TRACE("Raise block interrupt to PC"); out32(CME_LCL_SICR_OR, core << SHIFT32(3)); - //===================== - MARK_TRAP(SX_RAM_HRMOR) - //===================== - PK_TRACE("RAM HRMOR"); PK_TRACE("Now Wakeup the Core(pm_exit=1)"); @@ -420,9 +432,8 @@ p9_cme_stop_exit() while((in32(CME_LCL_EINR)) & (core << SHIFT32(21))); PK_TRACE("S-Reset all threads"); - CME_PUTSCOM(DIRECT_CONTROLS, core, BIT64(4)); - // BIT64(3)|BIT64(11)|BIT64(19)|BIT64(27)); - // BIT64(4)|BIT64(12)|BIT64(20)|BIT64(28)); + CME_PUTSCOM(DIRECT_CONTROLS, core, + BIT64(4) | BIT64(12) | BIT64(20) | BIT64(28)); //========================== MARK_TRAP(SX_SRESET_THREADS) @@ -435,10 +446,6 @@ p9_cme_stop_exit() while((~(in32(CME_LCL_EINR))) & (core << SHIFT32(21))); - //========================== - MARK_TRAP(SX_STOP15_THREADS) - //========================== - //PK_TRACE("Restore PSSCR back to actual level"); //PLS here: if (core & CME_MASK_C0) @@ -455,16 +462,16 @@ p9_cme_stop_exit() out32(CME_LCL_SICR_CLR, core << SHIFT32(3)); #endif - //========================= - MARK_TRAP(SX_ENABLE_ANALOG) - //========================= - if (d2u4_flag) { core = CME_MASK_BC; } } + //========================= + MARK_TRAP(SX_ENABLE_ANALOG) + //========================= + //-------------------------------------------------------------------------- // END OF STOP EXIT //-------------------------------------------------------------------------- @@ -472,7 +479,7 @@ p9_cme_stop_exit() PK_TRACE("XF: Now Wakeup the Core(pm_exit=1)"); out32(CME_LCL_SICR_OR, core << SHIFT32(5)); -// PK_TRACE("XF: Polling for Core Wakeup(pm_active=0)"); + PK_TRACE("XF: Polling for Core Waking up(pm_active=0)"); while((in32(CME_LCL_EINR)) & (core << SHIFT32(21))); @@ -492,7 +499,7 @@ p9_cme_stop_exit() G_cme_stop_record.core_running |= core; G_cme_stop_record.core_stopgpe &= ~core; - out32(CME_LCL_LMCR_CLR, (core << SHIFT32(15))); + out32(CME_LCL_LMCR_CLR, ((core << SHIFT32(13)) | (core << SHIFT32(15)))); if (core & CME_MASK_C0) { @@ -506,12 +513,8 @@ p9_cme_stop_exit() G_cme_stop_record.act_level_c1 = 0; } - // If not special wakeup, allow core to go back into STOP in the future - if (!spwu) - { - PK_TRACE("XF: Drop pm_exit if special wakeup is not present"); - out32(CME_LCL_SICR_CLR, core << SHIFT32(5)); - } + PK_TRACE("XF: Drop pm_exit to allow core to run if spwu is not present"); + out32(CME_LCL_SICR_CLR, core << SHIFT32(5)); //=========================== MARK_TRAP(ENDSCOPE_STOP_EXIT) diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit_marks.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit_marks.h index 30f2121d..19ebdb92 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit_marks.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit_marks.h @@ -36,33 +36,26 @@ namespace CME_STOP_EXIT_MARKS enum CME_SX_MARKS { - SX_STOP3 = 0x0, - SX_POWERON = 0x8, - SX_POWERON_DONE = 0x10, - SX_CHIPLET_RESET = 0x18, - SX_CHIPLET_RESET_GLSMUX_RESET = 0x20, - SX_CHIPLET_RESET_SCAN0 = 0x28, - SX_CATCHUP_A = 0x30, - SX_CHIPLET_INITS = 0x38, - SX_CHIPLET_INIT_SCAN0 = 0x40, - SX_CATCHUP_B = 0x48, - SX_ARRAY_INIT = 0x50, - SX_ARRAY_INIT_SUBMODULE = 0x68, - SX_ARRAY_INIT_SCAN0 = 0xe0, - SX_FUNC_INIT = 0xe8, - SX_STARTCLOCKS = 0xf0, - SX_STARTCLOCKS_GRID = 0xf8, - SX_STARTCLOCKS_DONE = 0x100, - SX_SCOM_INITS = 0x108, - SX_BCE_CHECK = 0x110, - SX_RUNTIME_INITS = 0x118, - SX_SELF_RESTORE = 0x120, - SX_RAM_HRMOR = 0x128, - SX_SRESET_THREADS = 0x130, - SX_STOP15_THREADS = 0x138, - SX_ENABLE_ANALOG = 0x140, - BEGINSCOPE_STOP_EXIT = 0x1f28, - ENDSCOPE_STOP_EXIT = 0x1f30 + BEGINSCOPE_STOP_EXIT = 0x20, + ENDSCOPE_STOP_EXIT = 0x28, + SX_STOP3 = 0x68, + SX_POWERON = 0xe0, + SX_CHIPLET_RESET = 0xe8, + SX_CHIPLET_RESET_SCAN0 = 0xf0, + SX_CATCHUP_A = 0xf8, + SX_CHIPLET_INITS = 0x100, + SX_CATCHUP_B = 0x108, + SX_ARRAY_INIT = 0x110, + SX_FUNC_INIT = 0x118, + SX_STARTCLOCKS = 0x120, + SX_STARTCLOCKS_ALIGN = 0x128, + SX_STARTCLOCKS_REGION = 0x130, + SX_SCOM_INITS = 0x138, + SX_BCE_CHECK = 0x140, + SX_RUNTIME_INITS = 0x148, + SX_SELF_RESTORE = 0x150, + SX_SRESET_THREADS = 0x168, + SX_ENABLE_ANALOG = 0x1e0 }; @@ -70,33 +63,26 @@ enum CME_SX_MARKS const std::vector<CME_SX_MARKS> MARKS = { + BEGINSCOPE_STOP_EXIT, + ENDSCOPE_STOP_EXIT, SX_STOP3, SX_POWERON, - SX_POWERON_DONE, SX_CHIPLET_RESET, - SX_CHIPLET_RESET_GLSMUX_RESET, SX_CHIPLET_RESET_SCAN0, SX_CATCHUP_A, SX_CHIPLET_INITS, - SX_CHIPLET_INIT_SCAN0, SX_CATCHUP_B, SX_ARRAY_INIT, - SX_ARRAY_INIT_SUBMODULE, - SX_ARRAY_INIT_SCAN0, SX_FUNC_INIT, SX_STARTCLOCKS, - SX_STARTCLOCKS_GRID, - SX_STARTCLOCKS_DONE, + SX_STARTCLOCKS_ALIGN, + SX_STARTCLOCKS_REGION, SX_SCOM_INITS, SX_BCE_CHECK, SX_RUNTIME_INITS, SX_SELF_RESTORE, - SX_RAM_HRMOR, SX_SRESET_THREADS, - SX_STOP15_THREADS, - SX_ENABLE_ANALOG, - BEGINSCOPE_STOP_EXIT, - ENDSCOPE_STOP_EXIT + SX_ENABLE_ANALOG }; } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c index 59b95954..64bd14cd 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c @@ -29,57 +29,53 @@ extern CmeStopRecord G_cme_stop_record; +// Important: g_eimr_override at any time should mask wakeup interrupts of +// running core(s), the override vector should change after each +// entry and exit as core state is changed. +// For Entry, mask the following interrupts via unified interrupt handler: +// lower priority interrupts than pm_active, and both pm_active (catchup) +// wakeup interrupts of the entering core(s) should still be masked +// via g_eimr_override (abortion), stopped core can still exit any time +// as their wakeup interrupts should be unmasked +// After Entry, unmask the following interrupts via pk_irq_vec_restore: +// priority group on stack, likely at least both pm_active unmasked +// (stopped core cannot get extra pm_active, untouched core can enter) +// here needs to use g_eimr_override to mask wakeup of running core(s) +// wakeup of the stopped core(s) should be already unmasked by default +// (when restored, previous masked wakeups are being unmasked as well) +// For Exit, mask the following interrupts via unified interrupt handler: +// lower priority interrupts than wakeup, including DB2+pm_active(catchup) +// After Exit, unmask the following interrupts via pk_irq_vec_restore: +// priority group on stack, likely at least wakeup and DB2 unmasked +// here needs to use g_eimr_override to mask wakeup of exited core(s) void p9_cme_stop_event_handler(void* arg, PkIrqId irq) { MARK_TRAP(STOP_EVENT_HANDLER) - PK_TRACE("SE-IRQ: %d", irq); + PK_TRACE("STOP-IRQ: %d", irq); pk_semaphore_post((PkSemaphore*)arg); - - // Important: g_eimr_override at any time should mask wakeup interrupts of - // running core(s), the override vector should change after each - // entry and exit as core state is changed. - // For Entry, mask the following interrupts via unified interrupt handler: - // lower priority interrupts than pm_active, and both pm_active (catchup) - // wakeup interrupts of the entering core(s) should still be masked - // via g_eimr_override (abortion), stopped core can still exit any time - // as their wakeup interrupts should be unmasked - // After Entry, unmask the following interrupts via pk_irq_vec_restore: - // priority group on stack, likely at least both pm_active unmasked - // (stopped core cannot get extra pm_active, untouched core can enter) - // here needs to use g_eimr_override to mask wakeup of running core(s) - // wakeup of the stopped core(s) should be already unmasked by default - // (when restored, previous masked wakeups are being unmasked as well) - // For Exit, mask the following interrupts via unified interrupt handler: - // lower priority interrupts than wakeup, including DB2+pm_active(catchup) - // After Exit, unmask the following interrupts via pk_irq_vec_restore: - // priority group on stack, likely at least wakeup and DB2 unmasked - // here needs to use g_eimr_override to mask wakeup of exited core(s) } void p9_cme_stop_doorbell_handler(void* arg, PkIrqId irq) { - int rc = 0; + uint32_t db1; PkMachineContext ctx; + MARK_TRAP(STOP_DOORBELL_HANDLER) PK_TRACE("DB-IRQ: %d", irq); - out32_sh(CME_LCL_EIMR_OR, BIT32(irq - 32)); - out32_sh(CME_LCL_EISR_CLR, BIT32(irq - 32)); + db1 = in32_sh(CME_LCL_EISR); + g_eimr_override |= BITS64(40, 2); - if (irq == IRQ_DB1_C0) + if (db1 & BIT32(8)) { - CME_PUTSCOM(CPPM_CMEDB1, CME_MASK_C0, 0); g_eimr_override &= ~IRQ_VEC_WAKE_C0; - //out32(CME_LCL_EIMR_CLR, BIT32(12) | BIT32(14) | BIT32(16)); } - if (irq == IRQ_DB1_C1) + if (db1 & BIT32(9)) { - CME_PUTSCOM(CPPM_CMEDB1, CME_MASK_C1, 0); g_eimr_override &= ~IRQ_VEC_WAKE_C1; - //out32(CME_LCL_EIMR_CLR, BIT32(13) | BIT32(15) | BIT32(17)); } pk_irq_vec_restore(&ctx); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c index e10997fa..b64f30b9 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_arrayinit.c @@ -30,68 +30,63 @@ int p9_hcd_core_arrayinit(uint32_t core) { int rc = CME_STOP_SUCCESS; -#if !EPM_P9_TUNING - uint64_t scom_data; - - PK_TRACE("Setup ABISTMUX_SEL"); - CME_PUTSCOM(PERV_CPLT_CTRL0_OR, core, BIT64(0)); - - PK_TRACE("setup ABIST modes"); - CME_GETSCOM(PERV_BIST, core, CME_SCOM_OR, scom_data); - scom_data &= ~BIT64(0) ; - scom_data |= BITS64(1, 2); - scom_data |= BITS64(6, 2); - CME_PUTSCOM(PERV_BIST, core, scom_data); - - PK_TRACE("Setup all Clock Domains and Clock Types"); - CME_GETSCOM(PERV_CLK_REGION, core, CME_SCOM_OR, scom_data); - scom_data |= BITS64(6, 2); - scom_data |= BITS64(48, 3); - CME_PUTSCOM(PERV_CLK_REGION, core, scom_data); - - PK_TRACE("Setup: loopcount , OPCG engine start ABIST, run-N mode"); - CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_OR, scom_data); - scom_data = 0x8002000000042FFF; - CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data); - - PK_TRACE("Setup IDLE count"); - CME_GETSCOM(PERV_OPCG_REG1, core, CME_SCOM_OR, scom_data); - scom_data &= 0x000000000FFFFFFF; - scom_data |= 0x0000000F00000000; - CME_PUTSCOM(PERV_OPCG_REG1, core, scom_data); - - PK_TRACE("opcg go"); - CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_OR, scom_data); - scom_data |= BIT64(1); - CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data); - - PK_TRACE("Poll OPCG done bit to check for run-N completeness"); - - do - { - CME_GETSCOM(PERV_CPLT_STAT0, core, CME_SCOM_AND, scom_data); - } - while(!(scom_data & BIT64(8))); - - MARK_TRAP(SX_ARRAY_INIT_SUBMODULE) - - PK_TRACE("OPCG done, clear Run-N mode"); - CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_OR, scom_data); - scom_data &= ~(BIT64(0) | BIT64(14) | BITS64(21, 43)); - CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data); - - PK_TRACE("clear all clock REGIONS and type"); - CME_PUTSCOM(PERV_CLK_REGION, core, 0); - - PK_TRACE("clear ABISTCLK_MUXSEL"); - CME_PUTSCOM(PERV_CPLT_CTRL0_CLEAR, core, BIT64(0)); - - PK_TRACE("clear BIST REGISTER"); - CME_PUTSCOM(PERV_BIST, core, 0); -#endif -#if !SKIP_SCAN0 - MARK_TRAP(SX_ARRAY_INIT_SCAN0) -#endif + /* @todo minic arrayinit module + uint64_t scom_data; + + PK_TRACE("Setup ABISTMUX_SEL"); + CME_PUTSCOM(PERV_CPLT_CTRL0_OR, core, BIT64(0)); + + PK_TRACE("setup ABIST modes"); + CME_GETSCOM(PERV_BIST, core, CME_SCOM_OR, scom_data); + scom_data &= ~BIT64(0) ; + scom_data |= BITS64(1, 2); + scom_data |= BITS64(6, 2); + CME_PUTSCOM(PERV_BIST, core, scom_data); + + PK_TRACE("Setup all Clock Domains and Clock Types"); + CME_GETSCOM(PERV_CLK_REGION, core, CME_SCOM_OR, scom_data); + scom_data |= BITS64(6, 2); + scom_data |= BITS64(48, 3); + CME_PUTSCOM(PERV_CLK_REGION, core, scom_data); + + PK_TRACE("Setup: loopcount , OPCG engine start ABIST, run-N mode"); + CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_OR, scom_data); + scom_data = 0x8002000000042FFF; + CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data); + + PK_TRACE("Setup IDLE count"); + CME_GETSCOM(PERV_OPCG_REG1, core, CME_SCOM_OR, scom_data); + scom_data &= 0x000000000FFFFFFF; + scom_data |= 0x0000000F00000000; + CME_PUTSCOM(PERV_OPCG_REG1, core, scom_data); + + PK_TRACE("opcg go"); + CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_OR, scom_data); + scom_data |= BIT64(1); + CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data); + + PK_TRACE("Poll OPCG done bit to check for run-N completeness"); + + do + { + CME_GETSCOM(PERV_CPLT_STAT0, core, CME_SCOM_AND, scom_data); + } + while(!(scom_data & BIT64(8))); + + PK_TRACE("OPCG done, clear Run-N mode"); + CME_GETSCOM(PERV_OPCG_REG0, core, CME_SCOM_OR, scom_data); + scom_data &= ~(BIT64(0) | BIT64(14) | BITS64(21, 43)); + CME_PUTSCOM(PERV_OPCG_REG0, core, scom_data); + + PK_TRACE("clear all clock REGIONS and type"); + CME_PUTSCOM(PERV_CLK_REGION, core, 0); + + PK_TRACE("clear ABISTCLK_MUXSEL"); + CME_PUTSCOM(PERV_CPLT_CTRL0_CLEAR, core, BIT64(0)); + + PK_TRACE("clear BIST REGISTER"); + CME_PUTSCOM(PERV_BIST, core, 0); + */ return rc; } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_init.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_init.c index 152cbb2b..3d1ef150 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_init.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_init.c @@ -31,10 +31,5 @@ p9_hcd_core_chiplet_init(uint32_t core) { int rc = CME_STOP_SUCCESS; -#if !SKIP_SCAN0 - // Marker for scan0 - MARK_TRAP(SX_CHIPLET_INIT_SCAN0) -#endif - return rc; } diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c index 50c0e058..a97ac8da 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c @@ -33,8 +33,9 @@ p9_hcd_core_chiplet_reset(uint32_t core) //uint64_t scom_data, uint32_t loop; - PK_TRACE("Init NET_CTRL0[1-5,12-14,18,22,26],step needed for hotplug"); - CME_PUTSCOM(CPPM_NC0INDIR_OR, core, NET_CTRL0_INIT_VECTOR); + PK_TRACE("Init NET_CTRL0[1,3-5,11-14,18,22,26],step needed for hotplug"); + CME_PUTSCOM(CPPM_NC0INDIR_OR, core, C_NET_CTRL0_INIT_VECTOR); + CME_PUTSCOM(CPPM_NC0INDIR_CLR, core, ~(C_NET_CTRL0_INIT_VECTOR | BIT64(2))); PK_TRACE("Flip core glsmux to refclk via PPM_CGCR[3]"); CME_PUTSCOM(C_PPM_CGCR, core, BIT64(0)); @@ -42,17 +43,8 @@ p9_hcd_core_chiplet_reset(uint32_t core) PK_TRACE("Assert core progdly and DCC bypass via NET_CTRL1[1,2]"); CME_PUTSCOM(CPPM_NC1INDIR_OR, core, BITS64(1, 2)); - PK_TRACE("Assert core DCC reset via NET_CTRL0[2]"); - CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(2)); - PK_TRACE("Drop vital thold via NET_CTRL0[16]"); CME_PUTSCOM(CPPM_NC0INDIR_CLR, core, BIT64(16)); - /* - PK_TRACE("ONLY till TP030: SET VITL_PHASE=1"); - CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(8)); - PPE_WAIT_CORE_CYCLES(loop, 50); - */ - MARK_TRAP(SX_CHIPLET_RESET_GLSMUX_RESET) PK_TRACE("Drop core glsmux reset via PPM_CGCR[0]"); CME_PUTSCOM(C_PPM_CGCR, core, 0); @@ -72,13 +64,7 @@ p9_hcd_core_chiplet_reset(uint32_t core) PK_TRACE("Drop PCB fence via NET_CTRL0[25]"); CME_PUTSCOM(CPPM_NC0INDIR_CLR, core, BIT64(25)); - /* - PK_TRACE("ONLY till TP030: SET SYNC_PULSE_DELAY=0b0011"); - CME_GETSCOM(C_SYNC_CONFIG, core, CME_SCOM_AND, scom_data); - scom_data = scom_data | 0x3000000000000000; - scom_data = scom_data & 0x3FFFFFFFFFFFFFFF; - CME_PUTSCOM(C_SYNC_CONFIG, core, scom_data); - */ + #if !SKIP_SCAN0 // Marker for scan0 MARK_TRAP(SX_CHIPLET_RESET_SCAN0) diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c index b24a192e..b2a1acb2 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_poweron.c @@ -66,8 +66,6 @@ p9_hcd_core_poweron(uint32_t core) } while(!(scom_data & BIT64(42))); - MARK_TRAP(SX_POWERON_DONE) - // vdd_pfet_force_state = 00 (Nop) PK_TRACE("Turn Off Force Von"); CME_PUTSCOM(PPM_PFCS_CLR, core, BITS64(0, 2)); diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c index 3ab36b7f..06aeea19 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_startclocks.c @@ -48,6 +48,9 @@ p9_hcd_core_startclocks(uint32_t core) PK_TRACE("Drop vital fences via CPLT_CTRL1[3]"); CME_PUTSCOM(C_CPLT_CTRL1_CLEAR, core, BIT64(3)); + PK_TRACE("Drop skew sense to skew adjust fence via NET_CTRL0[22]"); + CME_PUTSCOM(CPPM_NC0INDIR_CLR, core, BIT64(22)); + PK_TRACE("Assert core clock sync enable via CPPM_CACCR[15]"); CME_PUTSCOM(CPPM_CACCR_OR, core, BIT64(15)); @@ -59,6 +62,8 @@ p9_hcd_core_startclocks(uint32_t core) } while(~scom_data & BIT64(13)); + MARK_TRAP(SX_STARTCLOCKS_ALIGN) + PK_TRACE("Reset abstclk & syncclk muxsel(io_clk_sel) via CPLT_CTRL0[0:1]"); CME_PUTSCOM(C_CPLT_CTRL0_CLEAR, core, BITS64(0, 2)); @@ -85,6 +90,8 @@ p9_hcd_core_startclocks(uint32_t core) } while(~scom_data & BIT64(9)); + MARK_TRAP(SX_STARTCLOCKS_REGION) + PK_TRACE("Drop force_align via CPLT_CTRL0[3]"); CME_PUTSCOM(C_CPLT_CTRL0_CLEAR, core, BIT64(3)); PPE_WAIT_CORE_CYCLES(loop, 450); @@ -112,8 +119,6 @@ p9_hcd_core_startclocks(uint32_t core) PK_TRACE("Core clock is now running"); - MARK_TRAP(SX_STARTCLOCKS_DONE) - PK_TRACE("Drop chiplet fence via NC0INDIR[18]"); CME_PUTSCOM(CPPM_NC0INDIR_CLR, core, BIT64(18)); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c index 018fbeb5..6b1803de 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_arrayinit.c @@ -31,9 +31,5 @@ p9_hcd_cache_arrayinit(uint32_t quad) { int rc = SGPE_STOP_SUCCESS; -#if !SKIP_SCAN0 - MARK_TRAP(SX_ARRAY_INIT_SCAN0) -#endif - return rc; } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_init.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_init.c index db934114..04709af2 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_init.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_init.c @@ -31,10 +31,5 @@ p9_hcd_cache_chiplet_init(uint32_t quad) { int rc = SGPE_STOP_SUCCESS; -#if !SKIP_SCAN0 - // Marker for scan0 - MARK_TRAP(SX_CHIPLET_INIT_SCAN0) -#endif - return rc; } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c index f9f2393a..8e1e4a08 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_chiplet_reset.c @@ -26,31 +26,50 @@ #include "p9_sgpe_stop.h" #include "p9_sgpe_stop_exit_marks.h" +extern SgpeStopRecord G_sgpe_stop_record; + int p9_hcd_cache_chiplet_reset(uint32_t quad) { int rc = SGPE_STOP_SUCCESS; uint64_t scom_data; - - PK_TRACE("Init NET_CTRL0[1-5,12-14,18,22,26],step needed for hotplug"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, quad), NET_CTRL0_INIT_VECTOR); + uint32_t core, cbit; + + for(core = 0, cbit = BIT32((quad << 2)); + core < CORES_PER_QUAD; + core++, cbit = cbit >> 1) + { + if (G_sgpe_stop_record.group.core[VECTOR_CONFIG] & cbit) + { + PK_TRACE("Assert Core DCC reset via NET_CTRL0[2]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(C_NET_CTRL0_WOR, ((quad << 2) + core)), BIT64(2)); + } + } + + PK_TRACE("Init NET_CTRL0[1-5,11-14,18,22,26],step needed for hotplug"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, quad), Q_NET_CTRL0_INIT_VECTOR); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WAND, quad), Q_NET_CTRL0_INIT_VECTOR); PK_TRACE("Assert Progdly/DCC bypass,L2 DCC reset via NET_CTRL1[1,2,23,24]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL1_WOR, quad), (BITS64(1, 2) | BITS64(23, 2))); + PK_TRACE("Flip cache glsmux to DPLL via PPM_CGCR[3]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_PPM_CGCR, quad), (BIT64(0) | BIT64(3))); + + PK_TRACE("Flip L2 glsmux to DPLL via QPPM_EXCGCR[34:35]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_OR, quad), BITS64(34, 2)); + PK_TRACE("Assert DPLL ff_bypass via QPPM_DPLL_CTRL[2]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_DPLL_CTRL_OR, quad), BIT64(2)); PK_TRACE("Drop vital thold via NET_CTRL0[16]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WAND, quad), ~BIT64(16)); - MARK_TRAP(SX_CHIPLET_RESET_GLSMUX_RESET) + PK_TRACE("Drop cache glsmux reset via PPM_CGCR[0]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_PPM_CGCR, quad), BIT64(3)); - PK_TRACE("Drop L3 glsmux reset and select refclk via PPM_CGCR[0:3]"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_PPM_CGCR, quad), 0); - - PK_TRACE("Drop L2 glsmux reset and select refclk via QPPM_EXCGCR[32:35]"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_CLR, quad), BITS64(32, 4)); + PK_TRACE("Drop L2 glsmux reset via QPPM_EXCGCR[32:33]"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_CLR, quad), BITS64(32, 2)); PK_TRACE("Assert chiplet enable via NET_CTRL0[0]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, quad), BIT64(0)); @@ -75,10 +94,8 @@ p9_hcd_cache_chiplet_reset(uint32_t quad) #endif /// @todo scan_with_setpulse_module(l3 dcc) - - PK_TRACE("Drop L3 DCC bypass via NET_CTRL1[1]"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL1_WAND, quad), ~BIT64(1)); - + //PK_TRACE("Drop L3 DCC bypass via NET_CTRL1[1]"); + //GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL1_WAND, quad), ~BIT64(1)); return rc; } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c index f5efec7d..88a5acc9 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c @@ -80,12 +80,6 @@ p9_hcd_cache_dpll_setup(uint32_t quad) PK_TRACE("Drop DPLL bypass via NET_CTRL0[5]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WAND, quad), ~BIT64(5)); - PK_TRACE("Flip L3 glsmux select to DPLL output via PPM_CGCR[3]"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_PPM_CGCR, quad), BIT64(3)); - - PK_TRACE("Flip L2 glsmux select to DPLL output via QPPM_EXCGCR[34,35]"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_OR, quad), BITS64(34, 2)); - PK_TRACE("Drop DPLL ff_bypass via QPPM_DPLL_CTRL[2]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_DPLL_CTRL_CLEAR, quad), BIT64(2)); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c index c36b862e..22835d3c 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_l2_startclocks.c @@ -46,6 +46,19 @@ p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex) GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_CLEAR, quad), ((uint64_t)ex << SHIFT64(9))); + PK_TRACE("Raise clock sync enable before switch to dpll"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_OR, quad), (ex << SHIFT64(37))); + + PK_TRACE("Poll for clock sync done to raise"); + + do + { + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QACSR, quad), scom_data); + } + while(!(scom_data & (ex << SHIFT64(37)))); + + MARK_TRAP(SX_L2_STARTCLOCKS_ALIGN) + // align_chiplets() PK_TRACE("Set flushmode_inhibit via CPLT_CTRL0[2]"); @@ -72,18 +85,7 @@ p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex) PK_TRACE("Clear force_align via CPLT_CTRL0[3]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL0_CLEAR, quad), BIT64(3)); - PK_TRACE("Raise clock sync enable before switch to dpll"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_EXCGCR_OR, quad), (ex << SHIFT64(37))); - - PK_TRACE("Poll for clock sync done to raise"); - - do - { - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QACSR, quad), scom_data); - } - while(!(scom_data & (ex << SHIFT64(37)))); - - MARK_TRAP(SX_L2_STARTCLOCKS_GRID) + MARK_TRAP(SX_L2_STARTCLOCKS_REGION) // ------------------------------- // Start L2 Clock @@ -110,8 +112,6 @@ p9_hcd_cache_l2_startclocks(uint32_t quad, uint32_t ex) PK_TRACE("L2 clock is now running"); - MARK_TRAP(SX_L2_STARTCLOCKS_DONE) - PK_TRACE("Drop TLBIE Quiesce"); if (ex & FST_EX_IN_QUAD) diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c index c6a979df..f5732e13 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_poweron.c @@ -83,8 +83,6 @@ p9_hcd_cache_poweron(uint32_t quad) } while(!(scom_data & BIT64(50))); - MARK_TRAP(SX_POWERON_DONE) - // vdd_pfet_force_state = 00 (Nop) // vcs_pfet_force_state = 00 (Nop) PK_TRACE("Turn Off Force Von"); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c index fbb2c264..e43ca92e 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_startclocks.c @@ -105,6 +105,8 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex) } while(~scom_data & BIT64(9)); + MARK_TRAP(SX_CACHE_STARTCLOCKS_REGION) + PK_TRACE("Drop force_align via CPLT_CTRL0[3]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL0_CLEAR, quad), BIT64(3)); PPE_WAIT_CORE_CYCLES(loop, 450); @@ -137,8 +139,6 @@ p9_hcd_cache_startclocks(uint32_t quad, uint32_t ex) PK_TRACE("Cache clocks running now"); - MARK_TRAP(SX_CACHE_STARTCLOCKS_DONE) - // @todo // deskew_init() diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h index 8c329801..40690ac3 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h @@ -58,6 +58,7 @@ #define EQ_BIST 0x100F000B #define EQ_NET_CTRL0_WAND 0x100F0041 #define EQ_NET_CTRL0_WOR 0x100F0042 +#define C_NET_CTRL0_WOR 0x200F0042 #define EQ_NET_CTRL1_WAND 0x100F0045 #define EQ_NET_CTRL1_WOR 0x100F0046 @@ -114,20 +115,23 @@ enum SGPE_STOP_IRQ_SHORT_NAMES enum SGPE_STOP_IRQ_PAYLOAD_MASKS { - TYPE2_PAYLOAD_STOP_EVENT = 0xC00, - TYPE2_PAYLOAD_STOP_LEVEL = 0xF + TYPE2_PAYLOAD_EXIT_EVENT = 0xC00, + TYPE2_PAYLOAD_STOP_LEVEL = 0xF, + TYPE3_PAYLOAD_EXIT_EVENT = 0xC00, + TYPE6_PAYLOAD_EXIT_EVENT = 0xC00 }; enum SGPE_STOP_EVENT_LEVELS { - SGPE_EX_BASE_LV = 8, - SGPE_EQ_BASE_LV = 11 + LEVEL_EX_BASE = 8, + LEVEL_EQ_BASE = 11 }; -enum SGPE_STOP_EVENT_FLAGS +enum SGPE_STOP_VECTOR_INDEX { - SGPE_ENTRY_FLAG = 2, - SGPE_EXIT_FLAG = 1 + VECTOR_EXIT = 0, + VECTOR_ENTRY = 1, + VECTOR_CONFIG = 2 }; typedef struct @@ -144,21 +148,12 @@ typedef struct typedef struct { - uint32_t entry_x0; - uint32_t entry_x1; - uint32_t entry_x; - uint32_t entry_q; - uint32_t entry_c; - uint32_t exit_x0; - uint32_t exit_x1; - uint32_t exit_x; - uint32_t exit_q; - uint32_t exit_c; - uint32_t good_x0; - uint32_t good_x1; - uint32_t good_x; - uint32_t good_q; - uint32_t good_c; + uint32_t core[3]; + uint32_t ex_l[3]; + uint32_t ex_r[3]; + uint32_t ex_b[3]; + uint32_t quad[3]; + uint32_t qswu[2]; } sgpe_group_t; /// SGPE Stop Score Board Structure @@ -175,7 +170,7 @@ typedef struct } SgpeStopRecord; /// SGPE STOP Entry and Exit Prototypes -void p9_sgpe_stop_pig_type2_handler(void*, PkIrqId); +void p9_sgpe_stop_pig_handler(void*, PkIrqId); void p9_sgpe_stop_enter_thread(void*); void p9_sgpe_stop_exit_thread(void*); int p9_sgpe_stop_entry(); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_enter_marks.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_enter_marks.h index e928d987..3700f57f 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_enter_marks.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_enter_marks.h @@ -36,22 +36,23 @@ namespace SGPE_STOP_ENTRY_MARKS enum SGPE_SE_MARKS { - SE_STOP_SUSPEND_PSTATE = 0x0, - SE_STOP_L2_CLKS = 0x8, - SE_STOP_L2_GRID = 0x10, - SE_STOP8_DONE = 0x18, - SE_PURGE_L3 = 0x20, - SE_PURGE_L3_ABORT = 0x28, - SE_PURGE_L3_ABORT_DONE = 0x30, - SE_PURGE_PB = 0x38, - SE_WAIT_PGPE_SUSPEND = 0x40, - SE_QUIESCE_QUAD = 0x48, - SE_STOP_CACHE_CLKS = 0x50, - SE_POWER_OFF_CACHE = 0x68, - SE_STOP11_DONE = 0xe0, - BEGINSCOPE_STOP_ENTRY = 0x1f08, - ENDSCOPE_STOP_ENTRY = 0x1f10, - STOP_TYPE2_HANDLER = 0x1f18 + BEGINSCOPE_STOP_ENTRY = 0x0, + ENDSCOPE_STOP_ENTRY = 0x8, + STOP_PIG_HANDLER = 0x10, + SE_LESSTHAN8_WAIT = 0x68, + SE_STOP_SUSPEND_PSTATE = 0xe0, + SE_STOP_L2_CLKS = 0xe8, + SE_STOP_L2_GRID = 0xf0, + SE_STOP8_DONE = 0xf8, + SE_PURGE_L3 = 0x100, + SE_PURGE_L3_ABORT = 0x108, + SE_PURGE_L3_ABORT_DONE = 0x110, + SE_PURGE_PB = 0x118, + SE_WAIT_PGPE_SUSPEND = 0x120, + SE_QUIESCE_QUAD = 0x128, + SE_STOP_CACHE_CLKS = 0x130, + SE_POWER_OFF_CACHE = 0x138, + SE_STOP11_DONE = 0x140 }; @@ -59,6 +60,10 @@ enum SGPE_SE_MARKS const std::vector<SGPE_SE_MARKS> MARKS = { + BEGINSCOPE_STOP_ENTRY, + ENDSCOPE_STOP_ENTRY, + STOP_PIG_HANDLER, + SE_LESSTHAN8_WAIT, SE_STOP_SUSPEND_PSTATE, SE_STOP_L2_CLKS, SE_STOP_L2_GRID, @@ -71,10 +76,7 @@ const std::vector<SGPE_SE_MARKS> MARKS = SE_QUIESCE_QUAD, SE_STOP_CACHE_CLKS, SE_POWER_OFF_CACHE, - SE_STOP11_DONE, - BEGINSCOPE_STOP_ENTRY, - ENDSCOPE_STOP_ENTRY, - STOP_TYPE2_HANDLER + SE_STOP11_DONE }; } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c index 6a554b4e..31605cca 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c @@ -48,18 +48,113 @@ p9_sgpe_stop_entry() MARK_TAG(BEGINSCOPE_STOP_ENTRY, 0) //================================ - if (G_sgpe_stop_record.group.entry_q) + G_sgpe_stop_record.group.ex_l[VECTOR_ENTRY] = 0; + G_sgpe_stop_record.group.ex_r[VECTOR_ENTRY] = 0; + G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY] = 0; + G_sgpe_stop_record.group.quad[VECTOR_ENTRY] = 0; + + for(qloop = 0; qloop < MAX_QUADS; qloop++) { - MARK_TRAP(SE_STOP_SUSPEND_PSTATE) + + if (G_sgpe_stop_record.group.qswu[VECTOR_EXIT] & BIT32(qloop)) + { + continue; + } + + // Calculate EX and Quad targets based on current core stop levels + G_sgpe_stop_record.state[qloop].req_state_x0 = + G_sgpe_stop_record.level[qloop][0] < + G_sgpe_stop_record.level[qloop][1] ? + G_sgpe_stop_record.level[qloop][0] : + G_sgpe_stop_record.level[qloop][1] ; + G_sgpe_stop_record.state[qloop].req_state_x1 = + G_sgpe_stop_record.level[qloop][2] < + G_sgpe_stop_record.level[qloop][3] ? + G_sgpe_stop_record.level[qloop][2] : + G_sgpe_stop_record.level[qloop][3] ; + G_sgpe_stop_record.state[qloop].req_state_q = + G_sgpe_stop_record.state[qloop].req_state_x0 < + G_sgpe_stop_record.state[qloop].req_state_x1 ? + G_sgpe_stop_record.state[qloop].req_state_x0 : + G_sgpe_stop_record.state[qloop].req_state_x1 ; + + // Check if EX and/or Quad qualifies to proceed with entry + if (G_sgpe_stop_record.state[qloop].act_state_x0 < LEVEL_EX_BASE && + G_sgpe_stop_record.state[qloop].req_state_x0 >= LEVEL_EX_BASE) + { + G_sgpe_stop_record.group.ex_l[VECTOR_ENTRY] |= BIT32(qloop); + G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY] |= BIT32(qloop << 1); + } + + if (G_sgpe_stop_record.state[qloop].act_state_x1 < LEVEL_EX_BASE && + G_sgpe_stop_record.state[qloop].req_state_x1 >= LEVEL_EX_BASE) + { + G_sgpe_stop_record.group.ex_r[VECTOR_ENTRY] |= BIT32(qloop); + G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY] |= + BIT32((qloop << 1) + 1); + } + + if (G_sgpe_stop_record.state[qloop].act_state_q < + G_sgpe_stop_record.state[qloop].req_state_q && + G_sgpe_stop_record.state[qloop].req_state_q >= LEVEL_EQ_BASE) + { + G_sgpe_stop_record.group.quad[VECTOR_ENTRY] |= BIT32(qloop); + } + + if (G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY] || + G_sgpe_stop_record.group.quad[VECTOR_ENTRY]) + { + PK_TRACE("clv[%d][%d][%d][%d]", + G_sgpe_stop_record.level[qloop][0], + G_sgpe_stop_record.level[qloop][1], + G_sgpe_stop_record.level[qloop][2], + G_sgpe_stop_record.level[qloop][3]); + + PK_TRACE("act: qlv[%d]x0lv[%d]x1lv[%d]", + G_sgpe_stop_record.state[qloop].act_state_q, + G_sgpe_stop_record.state[qloop].act_state_x0, + G_sgpe_stop_record.state[qloop].act_state_x1); + + PK_TRACE("req: x0lv[%d]x1lv[%d]qlv[%d]", + G_sgpe_stop_record.state[qloop].req_state_x0, + G_sgpe_stop_record.state[qloop].req_state_x1, + G_sgpe_stop_record.state[qloop].req_state_q); + } } + G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY] &= + G_sgpe_stop_record.group.ex_b[VECTOR_CONFIG]; + G_sgpe_stop_record.group.ex_l[VECTOR_ENTRY] &= + G_sgpe_stop_record.group.ex_l[VECTOR_CONFIG]; + G_sgpe_stop_record.group.ex_r[VECTOR_ENTRY] &= + G_sgpe_stop_record.group.ex_r[VECTOR_CONFIG]; + + PK_TRACE("Core Entry Vectors: X[%x] X0[%x] X1[%x] Q[%x]", + G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY], + G_sgpe_stop_record.group.ex_l[VECTOR_ENTRY], + G_sgpe_stop_record.group.ex_r[VECTOR_ENTRY], + G_sgpe_stop_record.group.quad[VECTOR_ENTRY]); + //TODO: message pgpe to suspend Pstate only if stop level >= 8 + if (G_sgpe_stop_record.group.quad[VECTOR_ENTRY]) + { + //=============================== + MARK_TRAP(SE_STOP_SUSPEND_PSTATE) + //=============================== + } + else if (!G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY]) + { + //============================ + MARK_TAG(SE_LESSTHAN8_WAIT, 0) + //============================ + } + // ------------------------------------------------------------------------ // EX STOP ENTRY [LEVEL 8-10] // ------------------------------------------------------------------------ // only stop 8 sets x_in - for(xentry = G_sgpe_stop_record.group.entry_x, qloop = 0; + for(xentry = G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY], qloop = 0; xentry > 0; xentry = xentry << 2, qloop++) { @@ -195,7 +290,7 @@ p9_sgpe_stop_entry() STOP_ACT_ENABLE); } - // Update QSSR: l2_stopped, entry_ongoing = 0 + // Update QSSR: l2_stopped, drop stop_entry_ongoing out32(OCB_QSSR_CLR, BIT32(qloop + 20)); out32(OCB_QSSR_OR, (ex << SHIFT32((qloop << 1) + 1))); @@ -209,9 +304,9 @@ p9_sgpe_stop_entry() // QUAD STOP ENTRY [LEVEL 11-15] // ------------------------------------------------------------------------ - for(qentry = G_sgpe_stop_record.group.entry_q, qloop = 0; + for(qentry = G_sgpe_stop_record.group.quad[VECTOR_ENTRY], qloop = 0, ex = 0; qentry > 0; - qentry = qentry << 1, qloop++) + qentry = qentry << 1, qloop++, ex = 0) { // if this quad is not up to entry, skip if (!(qentry & BIT32(0))) @@ -219,12 +314,12 @@ p9_sgpe_stop_entry() continue; } - if (G_sgpe_stop_record.group.good_x0 & BIT32(qloop)) + if (G_sgpe_stop_record.group.ex_l[VECTOR_CONFIG] & BIT32(qloop)) { ex |= FST_EX_IN_QUAD; } - if (G_sgpe_stop_record.group.good_x1 & BIT32(qloop)) + if (G_sgpe_stop_record.group.ex_r[VECTOR_CONFIG] & BIT32(qloop)) { ex |= SND_EX_IN_QUAD; } @@ -286,74 +381,82 @@ p9_sgpe_stop_entry() { #if !SKIP_L3_PURGE_ABORT - if (in32(OCB_OISR1) & BIT32(15)) + if (in32(OCB_OISR1) & (BITS32(15, 2) & BIT32(19))) { - if (in32(OCB_OPITNPRA(2)) & (BITS32((qloop << 2), 4))) + if ((in32(OCB_OPITNPRA(2)) & BITS32((qloop << 2), 4)) || + (in32(OCB_OPITNPRA(3)) & BITS32((qloop << 2), 4))) { for(cloop = 0; cloop < CORES_PER_QUAD; cloop++) { - // todo type3 - if (in32(OCB_OPIT2CN(((qloop << 2) + cloop))) & - TYPE2_PAYLOAD_STOP_EVENT) + if ((in32(OCB_OPIT2CN(((qloop << 2) + cloop))) & + TYPE2_PAYLOAD_EXIT_EVENT) || + (in32(OCB_OPIT3CN(((qloop << 2) + cloop))) & + TYPE3_PAYLOAD_EXIT_EVENT)) { - - //======================================== - MARK_TAG(SE_PURGE_L3_ABORT, (32 >> qloop)) - //======================================== - - // Assert Purge L3 Abort - if (ex & FST_EX_IN_QUAD) - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, - qloop, 0), - BIT64(2)); - - if (ex & SND_EX_IN_QUAD) - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, - qloop, 1), - BIT64(2)); - - // Poll for Abort Done - if(ex & FST_EX_IN_QUAD) - { - do - { - GPE_GETSCOM(GPE_SCOM_ADDR_EX( - EX_PM_PURGE_REG, - qloop, 0), scom_data); - } - while(scom_data & (BIT64(0) | BIT64(2))); - } - - if(ex & SND_EX_IN_QUAD) - { - do - { - GPE_GETSCOM(GPE_SCOM_ADDR_EX( - EX_PM_PURGE_REG, - qloop, 1), scom_data); - } - while(scom_data & (BIT64(0) | BIT64(2))); - } - - //============================================= - MARK_TAG(SE_PURGE_L3_ABORT_DONE, (32 >> qloop)) - //============================================= - - // Deassert LCO Disable - if(ex & FST_EX_IN_QUAD) - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_LCO_DIS_REG, - qloop, 0), 0); - - if(ex & SND_EX_IN_QUAD) - GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_LCO_DIS_REG, - qloop, 1), 0); - - // Notify PGPE to resume l3_purge_aborted = 1; break; } } } + + if ((in32(OCB_OPIT6PRB) & BIT32(qloop)) && + (in32(OCB_OPIT6QN(qloop)) & TYPE6_PAYLOAD_EXIT_EVENT)) + { + l3_purge_aborted = 1; + } + + if (l3_purge_aborted) + { + + //======================================== + MARK_TAG(SE_PURGE_L3_ABORT, (32 >> qloop)) + //======================================== + + // Assert Purge L3 Abort + if (ex & FST_EX_IN_QUAD) + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 0), + BIT64(2)); + + if (ex & SND_EX_IN_QUAD) + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 1), + BIT64(2)); + + // Poll for Abort Done + if(ex & FST_EX_IN_QUAD) + { + do + { + GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, + qloop, 0), scom_data); + } + while(scom_data & (BIT64(0) | BIT64(2))); + } + + if(ex & SND_EX_IN_QUAD) + { + do + { + GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, + qloop, 1), scom_data); + } + while(scom_data & (BIT64(0) | BIT64(2))); + } + + //============================================= + MARK_TAG(SE_PURGE_L3_ABORT_DONE, (32 >> qloop)) + //============================================= + + // Deassert LCO Disable + if (ex & FST_EX_IN_QUAD) + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_LCO_DIS_REG, + qloop, 0), 0); + + if (ex & SND_EX_IN_QUAD) + GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_LCO_DIS_REG, + qloop, 1), 0); + + // Notify PGPE to resume + } } #endif @@ -489,9 +592,6 @@ p9_sgpe_stop_entry() GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_OR, qloop), 0xFFFF700000000000); - // Update QSSR: quad_stopped - out32(OCB_QSSR_OR, BIT32(qloop + 14)); - //========================================= MARK_TAG(SE_POWER_OFF_CACHE, (32 >> qloop)) //========================================= @@ -601,6 +701,9 @@ p9_sgpe_stop_entry() STOP_REQ_DISABLE, STOP_ACT_ENABLE); + // Update QSSR: quad_stopped + out32(OCB_QSSR_OR, BIT32(qloop + 14)); + // Update QSSR: drop stop_entry_ongoing out32(OCB_QSSR_CLR, BIT32(qloop + 20)); @@ -609,8 +712,18 @@ p9_sgpe_stop_entry() //===================================== } - // Enable Type2 Interrupt - out32(OCB_OIMR1_CLR, BIT32(15)); + //loop quad to drop spwu done + clear qswu + for(qloop = 0; qloop < MAX_QUADS; qloop++) + { + if (G_sgpe_stop_record.group.qswu[VECTOR_ENTRY] & BIT32(qloop)) + { + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_GPMMR_CLR, qloop), BIT64(0)); + G_sgpe_stop_record.group.qswu[VECTOR_ENTRY] &= ~BIT32(qloop); + } + } + + // Enable Type2/3/6 Interrupt + out32(OCB_OIMR1_CLR, (BITS32(15, 2) | BIT32(19))); //============================ MARK_TRAP(ENDSCOPE_STOP_ENTRY) //============================ diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c index 53d6e513..2a69c844 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c @@ -38,25 +38,52 @@ p9_sgpe_stop_exit() uint32_t cloop; uint32_t qloop; uint32_t cexit; - //uint64_t scom_data; + uint32_t qspwu; + int cme; + uint32_t core; + uint64_t scom_data = 0; ppm_sshsrc_t hist; //=============================== MARK_TAG(BEGINSCOPE_STOP_EXIT, 0) //=============================== - for(cexit = G_sgpe_stop_record.group.exit_c, qloop = 0, m_l2 = 0, m_l3 = 0; - cexit > 0; - cexit = cexit << 4, qloop++, m_l2 = 0, m_l3 = 0) + PK_TRACE("Core Exit Vectors: X[%x] X0[%x] X1[%x] Q[%x]", + G_sgpe_stop_record.group.ex_b[VECTOR_EXIT], + G_sgpe_stop_record.group.ex_l[VECTOR_EXIT], + G_sgpe_stop_record.group.ex_r[VECTOR_EXIT], + G_sgpe_stop_record.group.quad[VECTOR_EXIT]); + + for(cexit = G_sgpe_stop_record.group.core[VECTOR_EXIT], + qspwu = G_sgpe_stop_record.group.qswu[VECTOR_EXIT], + qloop = 0, m_l2 = 0, m_l3 = 0; + cexit > 0 || qspwu > 0; + cexit = cexit << 4, qspwu = qspwu << 1, qloop++, m_l2 = 0, m_l3 = 0) { m_l2 |= ((cexit & BITS32(0, 2)) ? FST_EX_IN_QUAD : 0); m_l2 |= ((cexit & BITS32(2, 2)) ? SND_EX_IN_QUAD : 0); + if (qspwu & BIT32(0)) + { + if (G_sgpe_stop_record.group.ex_l[VECTOR_CONFIG] & BIT32(qloop)) + { + m_l2 |= FST_EX_IN_QUAD; + } + + if (G_sgpe_stop_record.group.ex_r[VECTOR_CONFIG] & BIT32(qloop)) + { + m_l2 |= SND_EX_IN_QUAD; + } + } + if(!m_l2) { continue; } + // Update QSSR: stop_exit_ongoing + out32(OCB_QSSR_OR, BIT32(qloop + 26)); + if(G_sgpe_stop_record.state[qloop].act_state_q >= STOP_LEVEL_11) { SGPE_STOP_UPDATE_HISTORY(qloop, @@ -68,6 +95,23 @@ p9_sgpe_stop_exit() STOP_REQ_DISABLE, STOP_ACT_DISABLE); + for(cloop = 0; cloop < CORES_PER_QUAD; cloop++) + { + if(!(cexit & BIT32(cloop))) + { + continue; + } + + SGPE_STOP_UPDATE_HISTORY(((qloop << 2) + cloop), + CORE_ADDR_BASE, + STOP_CORE_IS_GATED, + STOP_TRANS_EXIT, + STOP_LEVEL_0, + STOP_LEVEL_0, + STOP_REQ_DISABLE, + STOP_ACT_DISABLE); + } + //================================= MARK_TAG(SX_POWERON, (32 >> qloop)) //================================= @@ -122,12 +166,12 @@ p9_sgpe_stop_exit() p9_hcd_cache_initf(qloop); #endif - if (G_sgpe_stop_record.group.good_x0 & BIT32(qloop)) + if (G_sgpe_stop_record.group.ex_l[VECTOR_CONFIG] & BIT32(qloop)) { m_l3 |= FST_EX_IN_QUAD; } - if (G_sgpe_stop_record.group.good_x1 & BIT32(qloop)) + if (G_sgpe_stop_record.group.ex_r[VECTOR_CONFIG] & BIT32(qloop)) { m_l3 |= SND_EX_IN_QUAD; } @@ -180,10 +224,34 @@ p9_sgpe_stop_exit() { G_sgpe_stop_record.state[qloop].act_state_x1 = 0; } + + // Update QSSR: drop l2_stopped, + out32(OCB_QSSR_CLR, (m_l2 << SHIFT32((qloop << 1) + 1))); } if(G_sgpe_stop_record.state[qloop].act_state_q >= STOP_LEVEL_11) { + for(cme = 0; cme < EXES_PER_QUAD; cme += 2) + { + core = ((cexit & BITS32(cme, 2)) >> SHIFT32(cme + 1)); + + if(!core) + { + continue; + } + + // Raise Core-L2 + Core-CC Quiesces + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SICR_OR, + qloop, (cme >> 1)), + ((core << SHIFT32(7)) | (core << SHIFT32(9)))); + + do + { + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SISR, + qloop, (cme >> 1)), scom_data); + } + while((scom_data & core) != core); + } #if !STOP_PRIME //==================================== @@ -200,11 +268,12 @@ p9_sgpe_stop_exit() MARK_TAG(SX_CME_BOOT, (32 >> qloop)) //================================== - PK_TRACE("Boot CME"); - //FIXME cmeBootList to be eventually replaced with actual vector - uint16_t cmeBootList = 0x8000; +#if !SKIP_CME_BOOT + uint16_t cmeBootList = (m_l3 << SHIFT16(((qloop << 1) + 1))); + PK_TRACE("Boot CME [%x]", cmeBootList); boot_cme( cmeBootList ); - //MARK_TRAP(SX_CME_BOOT_END) +#endif + //======================================= MARK_TAG(SX_RUNTIME_INITS, (32 >> qloop)) //======================================= @@ -220,8 +289,27 @@ p9_sgpe_stop_exit() //========================= #endif G_sgpe_stop_record.state[qloop].act_state_q = 0; + + SGPE_STOP_UPDATE_HISTORY(qloop, + QUAD_ADDR_BASE, + STOP_CORE_IS_GATED, + STOP_TRANS_COMPLETE, + STOP_LEVEL_0, + STOP_LEVEL_0, + STOP_REQ_DISABLE, + STOP_ACT_DISABLE); + + // Update QSSR: drop quad_stopped + out32(OCB_QSSR_CLR, BIT32(qloop + 26)); } + // assert quad special wakeup done + if (qspwu & BIT32(0)) + { + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_GPMMR_OR, qloop), BIT64(0)); + } + + // process core portion of core request for(cloop = 0; cloop < CORES_PER_QUAD; cloop++) { if(!(cexit & BIT32(cloop))) @@ -239,16 +327,22 @@ p9_sgpe_stop_exit() // Change PPM Wakeup to CME GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CPMMR_CLR, ((qloop << 2) + cloop)), BIT64(13)); - PK_TRACE("Doorbell1 the CME"); + PK_TRACE("Doorbell1 the CME %d", ((qloop << 2) + cloop)); GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CMEMSG, ((qloop << 2) + cloop)), (BIT64(0))); GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CMEDB1_OR, ((qloop << 2) + cloop)), BIT64(7)); } + + // Update QSSR: drop stop_exit_ongoing + out32(OCB_QSSR_CLR, BIT32(qloop + 26)); } - // Enable Type2 Interrupt - out32(OCB_OIMR1_CLR, BIT32(15)); + // Enable Type2/3/6 Interrupt + if (!G_sgpe_stop_record.group.core[VECTOR_ENTRY]) + { + out32(OCB_OIMR1_CLR, (BITS32(15, 2) | BIT32(19))); + } //=========================== MARK_TRAP(ENDSCOPE_STOP_EXIT) diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit_marks.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit_marks.h index 11905aa3..7efdc085 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit_marks.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit_marks.h @@ -36,31 +36,26 @@ namespace SGPE_STOP_EXIT_MARKS enum SGPE_SX_MARKS { - SX_POWERON = 0x0, - SX_POWERON_DONE = 0x8, - SX_CHIPLET_RESET = 0x10, - SX_CHIPLET_RESET_GLSMUX_RESET = 0x18, - SX_CHIPLET_RESET_SCAN0 = 0x20, - SX_DPLL_SETUP = 0x28, - SX_DPLL_START_DONE = 0x30, - SX_CHIPLET_INITS = 0x38, - SX_CHIPLET_INIT_SCAN0 = 0x40, - SX_ARRAY_INIT = 0x48, - SX_ARRAY_INIT_SUBMODULE = 0x50, - SX_ARRAY_INIT_SCAN0 = 0x68, - SX_FUNC_INIT = 0xe0, - SX_CACHE_STARTCLOCKS = 0xe8, - SX_CACHE_STARTCLOCKS_DONE = 0xf0, - SX_L2_STARTCLOCKS = 0xf8, - SX_L2_STARTCLOCKS_GRID = 0x100, - SX_L2_STARTCLOCKS_DONE = 0x108, - SX_SCOM_INITS = 0x110, - SX_CME_BOOT = 0x118, - SX_RUNTIME_INITS = 0x120, - SX_ENABLE_ANALOG = 0x128, - SX_LESSTHAN8_WAIT = 0x130, - BEGINSCOPE_STOP_EXIT = 0x1f28, - ENDSCOPE_STOP_EXIT = 0x1f30 + BEGINSCOPE_STOP_EXIT = 0x20, + ENDSCOPE_STOP_EXIT = 0x28, + SX_POWERON = 0x68, + SX_CHIPLET_RESET = 0xe0, + SX_CHIPLET_RESET_SCAN0 = 0xe8, + SX_DPLL_SETUP = 0xf0, + SX_DPLL_START_DONE = 0xf8, + SX_CHIPLET_INITS = 0x100, + SX_ARRAY_INIT = 0x108, + SX_FUNC_INIT = 0x110, + SX_CACHE_STARTCLOCKS = 0x118, + SX_CACHE_STARTCLOCKS_REGION = 0x120, + SX_L2_STARTCLOCKS = 0x128, + SX_L2_STARTCLOCKS_ALIGN = 0x130, + SX_L2_STARTCLOCKS_REGION = 0x138, + SX_SCOM_INITS = 0x140, + SX_CME_BOOT = 0x148, + SX_RUNTIME_INITS = 0x150, + SX_ENABLE_ANALOG = 0x168, + SX_LESSTHAN8_WAIT = 0x1e0 }; @@ -68,31 +63,26 @@ enum SGPE_SX_MARKS const std::vector<SGPE_SX_MARKS> MARKS = { + BEGINSCOPE_STOP_EXIT, + ENDSCOPE_STOP_EXIT, SX_POWERON, - SX_POWERON_DONE, SX_CHIPLET_RESET, - SX_CHIPLET_RESET_GLSMUX_RESET, SX_CHIPLET_RESET_SCAN0, SX_DPLL_SETUP, SX_DPLL_START_DONE, SX_CHIPLET_INITS, - SX_CHIPLET_INIT_SCAN0, SX_ARRAY_INIT, - SX_ARRAY_INIT_SUBMODULE, - SX_ARRAY_INIT_SCAN0, SX_FUNC_INIT, SX_CACHE_STARTCLOCKS, - SX_CACHE_STARTCLOCKS_DONE, + SX_CACHE_STARTCLOCKS_REGION, SX_L2_STARTCLOCKS, - SX_L2_STARTCLOCKS_GRID, - SX_L2_STARTCLOCKS_DONE, + SX_L2_STARTCLOCKS_ALIGN, + SX_L2_STARTCLOCKS_REGION, SX_SCOM_INITS, SX_CME_BOOT, SX_RUNTIME_INITS, SX_ENABLE_ANALOG, - SX_LESSTHAN8_WAIT, - BEGINSCOPE_STOP_EXIT, - ENDSCOPE_STOP_EXIT + SX_LESSTHAN8_WAIT }; } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c index f5176187..88cbf890 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c @@ -50,90 +50,148 @@ SgpeStopRecord G_sgpe_stop_record; // ex -> 0 // eq -> ex -> 0 // + void -p9_sgpe_stop_pig_type2_handler(void* arg, PkIrqId irq) +p9_sgpe_stop_pig_handler(void* arg, PkIrqId irq) { - int event; - uint32_t qloop; + uint32_t cirq; + uint32_t qirq; uint32_t cloop; - uint32_t cgood; - uint32_t pending; - uint32_t payload; + uint32_t qloop; + uint32_t cpending_t2 = 0; + uint32_t cpending_t3 = 0; + uint32_t qpending_t6 = 0; + uint32_t payload = 0; + + //========================= + MARK_TRAP(STOP_PIG_HANDLER) + //========================= + + PK_TRACE("PIG-IRQ: %d", irq); + // Disable type2/3/6 interrupt + out32(OCB_OIMR1_OR, (BITS32(15, 2) | BIT32(19))); + // Read type2/3/6 interrupt status + cirq = (in32(OCB_OISR1) & BITS32(15, 2)); + qirq = (in32(OCB_OISR1) & BIT32(19)); + // Clear type2/3/6 interrupt status + out32(OCB_OISR1_CLR, (cirq | qirq)); + + // read type2/3/6 interrupt pending status + // then clear interrupt pending status + if (cirq & BIT32(15)) + { + cpending_t2 = in32(OCB_OPITNPRA(2)); + out32(OCB_OPITNPRA_CLR(2), cpending_t2); + PK_TRACE("Type2: %x", cpending_t2); + } + + if (cirq & BIT32(16)) + { + cpending_t3 = in32(OCB_OPITNPRA(3)); + out32(OCB_OPITNPRA_CLR(3), cpending_t3); + PK_TRACE("Type3: %x", cpending_t3); + } - MARK_TRAP(STOP_TYPE2_HANDLER) - // Disable Type2 Interrupt - out32(OCB_OIMR1_OR, BIT32(15)); - // Cleart Type2 Interrupt - out32(OCB_OISR1_CLR, BIT32(15)); - // read type2 interrupt status - pending = in32(OCB_OPITNPRA(2)); - // then clear interrupt pending bits - out32(OCB_OPITNPRA_CLR(2), pending); + if (qirq) + { + qpending_t6 = in32(OCB_OPIT6PRB); + out32(OCB_OPIT6PRB_CLR, qpending_t6); + PK_TRACE("Type6: %x", qpending_t6); + } - PK_TRACE("Type2: %x", pending); // clear group before analyzing input - G_sgpe_stop_record.group.entry_x0 = 0; - G_sgpe_stop_record.group.entry_x1 = 0; - G_sgpe_stop_record.group.entry_x = 0; - G_sgpe_stop_record.group.entry_q = 0; - G_sgpe_stop_record.group.entry_c = 0; - G_sgpe_stop_record.group.exit_x0 = 0; - G_sgpe_stop_record.group.exit_x1 = 0; - G_sgpe_stop_record.group.exit_x = 0; - G_sgpe_stop_record.group.exit_q = 0; - G_sgpe_stop_record.group.exit_c = 0; + G_sgpe_stop_record.group.core[VECTOR_ENTRY] = 0; + G_sgpe_stop_record.group.core[VECTOR_EXIT] = 0; + G_sgpe_stop_record.group.ex_l[VECTOR_EXIT] = 0; + G_sgpe_stop_record.group.ex_r[VECTOR_EXIT] = 0; + G_sgpe_stop_record.group.ex_b[VECTOR_EXIT] = 0; + G_sgpe_stop_record.group.quad[VECTOR_EXIT] = 0; // loop all quads - for(qloop = 0, cgood = G_sgpe_stop_record.group.good_c; - qloop < MAX_QUADS; - qloop++, pending = pending << 4, cgood = cgood << 4) + for(qloop = 0; qloop < MAX_QUADS; qloop++) { - // if nothing happening to this quad, skip - if(!(BITS32(0, 4) & pending & cgood)) + + // if no quad special wakeup, skip to core request + if (qirq && (BIT32(qloop) & qpending_t6 & + G_sgpe_stop_record.group.quad[VECTOR_CONFIG])) + { + + // read payload on quad has interrupt pending + payload = in32(OCB_OPIT6QN(qloop)); + PK_TRACE("q[%d] payload [%x]", qloop, payload); + + if (payload & TYPE6_PAYLOAD_EXIT_EVENT) + { + PK_TRACE("q[%d] request special wakeup", qloop); + G_sgpe_stop_record.group.qswu[VECTOR_EXIT] |= BIT32(qloop); + G_sgpe_stop_record.group.quad[VECTOR_EXIT] |= BIT32(qloop); + G_sgpe_stop_record.group.ex_l[VECTOR_EXIT] |= BIT32(qloop); + G_sgpe_stop_record.group.ex_r[VECTOR_EXIT] |= BIT32(qloop); + G_sgpe_stop_record.group.ex_b[VECTOR_EXIT] |= + BITS32((qloop << 1), 2); + } + else + { + PK_TRACE("q[%d] drop special wakeup", qloop); + G_sgpe_stop_record.group.qswu[VECTOR_ENTRY] |= BIT32(qloop); + G_sgpe_stop_record.group.qswu[VECTOR_EXIT] &= ~BIT32(qloop); + } + } + + // if no core request, skip to next quad + if(!cirq || (!(BITS32((qloop << 2), 4) & (cpending_t2 | cpending_t3) & + G_sgpe_stop_record.group.core[VECTOR_CONFIG]))) { continue; } - PK_TRACE("q[%d]", qloop); - PK_TRACE("clv[%d][%d][%d][%d]", + PK_TRACE("q[%d] has core request:", qloop); + PK_TRACE("now clv[%d][%d][%d][%d]", G_sgpe_stop_record.level[qloop][0], G_sgpe_stop_record.level[qloop][1], G_sgpe_stop_record.level[qloop][2], G_sgpe_stop_record.level[qloop][3]); // then loop all cores in the quad - for(cloop = 0, event = 0; cloop < CORES_PER_QUAD; cloop++) + for(cloop = 0; cloop < CORES_PER_QUAD; cloop++) { - // again skip core that doesnt have interrupt pending - if (!(pending & BIT32(cloop))) + // again skip core that doesnt have interrupt cpending + if (!((cpending_t2 | cpending_t3) & BIT32((qloop << 2) + cloop))) { continue; + // read payload on core has interrupt cpending + } + else if (cpending_t2 & BIT32((qloop << 2) + cloop)) + { + payload = in32(OCB_OPIT2CN(((qloop << 2) + cloop))); + } + else if (cpending_t3 & BIT32((qloop << 2) + cloop)) + { + payload = in32(OCB_OPIT3CN(((qloop << 2) + cloop))); } - // read payload on core has interrupt pending - payload = in32(OCB_OPIT2CN(((qloop << 2) + cloop))); PK_TRACE("c[%d] payload [%x]", cloop, payload); // check if exit request - if (payload & TYPE2_PAYLOAD_STOP_EVENT) + if (payload & TYPE2_PAYLOAD_EXIT_EVENT) { PK_TRACE("c[%d] request exit", cloop); - // remember which core asking to exit - event |= SGPE_EXIT_FLAG; if (cloop < CORES_PER_EX) { - G_sgpe_stop_record.group.exit_x0 |= BIT32(qloop); - G_sgpe_stop_record.group.exit_x |= BIT32(qloop << 1); + G_sgpe_stop_record.group.ex_l[VECTOR_EXIT] |= BIT32(qloop); + G_sgpe_stop_record.group.ex_b[VECTOR_EXIT] |= + BIT32(qloop << 1); } else { - G_sgpe_stop_record.group.exit_x1 |= BIT32(qloop); - G_sgpe_stop_record.group.exit_x |= BIT32((qloop << 1) + 1); + G_sgpe_stop_record.group.ex_r[VECTOR_EXIT] |= BIT32(qloop); + G_sgpe_stop_record.group.ex_b[VECTOR_EXIT] |= + BIT32((qloop << 1) + 1); } - G_sgpe_stop_record.group.exit_q |= BIT32(qloop); - G_sgpe_stop_record.group.exit_c |= + G_sgpe_stop_record.group.quad[VECTOR_EXIT] |= BIT32(qloop); + G_sgpe_stop_record.group.core[VECTOR_EXIT] |= BIT32(((qloop << 2) + cloop)); } // otherwise it is entry request with stop level in payload @@ -141,121 +199,43 @@ p9_sgpe_stop_pig_type2_handler(void* arg, PkIrqId irq) { PK_TRACE("c[%d] request enter to lv[%d]", cloop, (payload & TYPE2_PAYLOAD_STOP_LEVEL)); + // read stop level on core asking to enter - event |= SGPE_ENTRY_FLAG; G_sgpe_stop_record.level[qloop][cloop] = (payload & TYPE2_PAYLOAD_STOP_LEVEL); - G_sgpe_stop_record.group.entry_c |= + G_sgpe_stop_record.group.core[VECTOR_ENTRY] |= BIT32(((qloop << 2) + cloop)); } - - } - - // If an entry being requested by at least one core - if (event & SGPE_ENTRY_FLAG) - { - PK_TRACE("clv[%d][%d][%d][%d]", - G_sgpe_stop_record.level[qloop][0], - G_sgpe_stop_record.level[qloop][1], - G_sgpe_stop_record.level[qloop][2], - G_sgpe_stop_record.level[qloop][3]); - - // Calculate EX and Quad targets based on current core stop levels - G_sgpe_stop_record.state[qloop].req_state_x0 = - G_sgpe_stop_record.level[qloop][0] < - G_sgpe_stop_record.level[qloop][1] ? - G_sgpe_stop_record.level[qloop][0] : - G_sgpe_stop_record.level[qloop][1] ; - G_sgpe_stop_record.state[qloop].req_state_x1 = - G_sgpe_stop_record.level[qloop][2] < - G_sgpe_stop_record.level[qloop][3] ? - G_sgpe_stop_record.level[qloop][2] : - G_sgpe_stop_record.level[qloop][3] ; - G_sgpe_stop_record.state[qloop].req_state_q = - G_sgpe_stop_record.state[qloop].req_state_x0 < - G_sgpe_stop_record.state[qloop].req_state_x1 ? - G_sgpe_stop_record.state[qloop].req_state_x0 : - G_sgpe_stop_record.state[qloop].req_state_x1 ; - - // Check if EX and/or Quad qualifies to proceed with entry - if (G_sgpe_stop_record.state[qloop].act_state_x0 < - SGPE_EX_BASE_LV && - G_sgpe_stop_record.state[qloop].req_state_x0 >= - SGPE_EX_BASE_LV) - { - G_sgpe_stop_record.group.entry_x0 |= BIT32(qloop); - G_sgpe_stop_record.group.entry_x |= BIT32(qloop << 1); - } - - if (G_sgpe_stop_record.state[qloop].act_state_x1 < - SGPE_EX_BASE_LV && - G_sgpe_stop_record.state[qloop].req_state_x1 >= - SGPE_EX_BASE_LV) - { - G_sgpe_stop_record.group.entry_x1 |= BIT32(qloop); - G_sgpe_stop_record.group.entry_x |= BIT32((qloop << 1) + 1); - } - - if (G_sgpe_stop_record.state[qloop].act_state_q < - G_sgpe_stop_record.state[qloop].req_state_q && - G_sgpe_stop_record.state[qloop].req_state_q >= - SGPE_EQ_BASE_LV) - { - G_sgpe_stop_record.group.entry_q |= BIT32(qloop); - } - } - // todo MARK_TAG(SE_LESSTHAN8_WAIT) - PK_TRACE("req:x0lv[%d]x1lv[%d]qlv[%d]", - G_sgpe_stop_record.state[qloop].req_state_x0, - G_sgpe_stop_record.state[qloop].req_state_x1, - G_sgpe_stop_record.state[qloop].req_state_q); - - PK_TRACE("act:x0lv[%d]x1lv[%d]qlv[%d]", - G_sgpe_stop_record.state[qloop].act_state_x0, - G_sgpe_stop_record.state[qloop].act_state_x1, - G_sgpe_stop_record.state[qloop].act_state_q); + PK_TRACE("new clv[%d][%d][%d][%d]", + G_sgpe_stop_record.level[qloop][0], + G_sgpe_stop_record.level[qloop][1], + G_sgpe_stop_record.level[qloop][2], + G_sgpe_stop_record.level[qloop][3]); } - G_sgpe_stop_record.group.entry_x0 &= G_sgpe_stop_record.group.good_x0; - G_sgpe_stop_record.group.entry_x1 &= G_sgpe_stop_record.group.good_x1; - G_sgpe_stop_record.group.entry_x &= G_sgpe_stop_record.group.good_x; - G_sgpe_stop_record.group.entry_q &= G_sgpe_stop_record.group.good_q; - G_sgpe_stop_record.group.entry_c &= G_sgpe_stop_record.group.good_c; - G_sgpe_stop_record.group.exit_x0 &= G_sgpe_stop_record.group.good_x0; - G_sgpe_stop_record.group.exit_x1 &= G_sgpe_stop_record.group.good_x1; - G_sgpe_stop_record.group.exit_x &= G_sgpe_stop_record.group.good_x; - G_sgpe_stop_record.group.exit_q &= G_sgpe_stop_record.group.good_q; - G_sgpe_stop_record.group.exit_c &= G_sgpe_stop_record.group.good_c; - - PK_TRACE("Good: X0[%x] X1[%x] Q[%x] C[%x]", - G_sgpe_stop_record.group.good_x0, - G_sgpe_stop_record.group.good_x1, - G_sgpe_stop_record.group.good_q, - G_sgpe_stop_record.group.good_c); - PK_TRACE("Entry: X0[%x] X1[%x] Q[%x] C[%x]", - G_sgpe_stop_record.group.entry_x0, - G_sgpe_stop_record.group.entry_x1, - G_sgpe_stop_record.group.entry_q, - G_sgpe_stop_record.group.entry_c); - PK_TRACE("Exit: X0[%x] X1[%x] Q[%x] C[%x]", - G_sgpe_stop_record.group.exit_x0, - G_sgpe_stop_record.group.exit_x1, - G_sgpe_stop_record.group.exit_q, - G_sgpe_stop_record.group.exit_c); - PK_TRACE("X: G[%x] E[%x] X[%x]", - G_sgpe_stop_record.group.good_x, - G_sgpe_stop_record.group.entry_x, - G_sgpe_stop_record.group.exit_x); - - if (G_sgpe_stop_record.group.exit_c) + G_sgpe_stop_record.group.ex_b[VECTOR_EXIT] &= + G_sgpe_stop_record.group.ex_b[VECTOR_CONFIG]; + G_sgpe_stop_record.group.ex_l[VECTOR_EXIT] &= + G_sgpe_stop_record.group.ex_l[VECTOR_CONFIG]; + G_sgpe_stop_record.group.ex_r[VECTOR_EXIT] &= + G_sgpe_stop_record.group.ex_r[VECTOR_CONFIG]; + + PK_TRACE("Quad Speciali Wakeup: Raise[%x], Drop[%x]", + G_sgpe_stop_record.group.qswu[VECTOR_EXIT], + G_sgpe_stop_record.group.qswu[VECTOR_ENTRY]); + PK_TRACE("Core Request Stop: Entry[%x], Exit[%x]", + G_sgpe_stop_record.group.core[VECTOR_ENTRY], + G_sgpe_stop_record.group.core[VECTOR_EXIT]); + + if (G_sgpe_stop_record.group.core[VECTOR_EXIT]) { PK_TRACE("unblock exit"); pk_semaphore_post(&(G_sgpe_stop_record.sem[1])); } - if (G_sgpe_stop_record.group.entry_c) + if (G_sgpe_stop_record.group.core[VECTOR_ENTRY]) { PK_TRACE("unblock entry"); pk_semaphore_post(&(G_sgpe_stop_record.sem[0])); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h index 178185bb..8e775ca7 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h @@ -37,13 +37,21 @@ #define STOP_PRIME 0 #define SKIP_L3_PURGE 0 #define SKIP_L3_PURGE_ABORT 0 +#define SKIP_CME_BOOT 1 +#define SKIP_IPL_SETUP 1 // -------------------- -#define USE_SIMICS_IO 0 #define EPM_P9_TUNING 1 +#define SIMICS_TUNING 0 +#define USE_SIMICS_IO 0 #define DEV_DEBUG 1 +#if EPM_P9_TUNING + #define PK_TRACE_BUFFER_WRAP_MARKER 1 +#endif +#define PK_TRACE_TIMER_OUTPUT 0 + // -------------------- // This application will use the external timebase register @@ -92,5 +100,7 @@ OCCHW_IRQ_CHECK_STOP_GPE3 OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ OCCHW_IRQ_IPI3_HI_PRIORITY OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ OCCHW_IRQ_IPI3_LO_PRIORITY OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ - OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED + OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ + OCCHW_IRQ_PMC_PCB_INTR_TYPE3_PENDING OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ + OCCHW_IRQ_PMC_PCB_INTR_TYPE6_PENDING OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED #endif /*__PK_APP_CFG_H__*/ |
