STOP: Add queued scom support to CME

Change-Id: I2cbcfe1a33e51c114b539fece5e03db130579cd9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39304
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

6 files changed, 25 insertions, 65 deletions

diff --git a/import/chips/p9/common/pmlib/include/cmehw_common.h b/import/chips/p9/common/pmlib/include/cmehw_common.h
index 65abb697..b3bfae1c 100644
--- a/import/chips/p9/common/pmlib/include/cmehw_common.h
+++ b/import/chips/p9/common/pmlib/include/cmehw_common.h
@@ -57,7 +57,7 @@ enum CME_SCOM_CONTROLS
 
 #if defined(USE_CME_QUEUED_SCOM) && defined(USE_PPE_IMPRECISE_MODE)
 #define CME_GETSCOM(addr, core, scom_op, data)                 \
-    PPE_LVD(CME_SCOM_ADDR(addr, core, CME_SCOM_QUEUED), data);
+    PPE_LVD(CME_SCOM_ADDR(addr, core, scom_op), data);
 #define CME_PUTSCOM(addr, core, data)                          \
     putscom_norc(CME_SCOM_ADDR(addr, core, CME_SCOM_QUEUED), data);
 #else
diff --git a/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h b/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h
index afd30489..aa8faab5 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/cme_panic_codes.h
@@ -47,17 +47,17 @@ CME_UIH_NOT_ALL_IN_PRTY_GROUP       = 0x1c01,
 CME_UIH_EIMR_STACK_UNDERFLOW        = 0x1c02,
 CME_UIH_EIMR_STACK_OVERFLOW         = 0x1c03,
 CME_UIH_PHANTOM_INTERRUPT           = 0x1c04,
-CME_STOP_PUTRING_HEADER_ERROR       = 0x1c05,
-CME_STOP_BCE_CORE_RING_FAILED       = 0x1c06,
-CME_STOP_EXIT_PHANTOM_WAKEUP        = 0x1c07,
-CME_STOP_EXIT_BCE_SCOM_FAILED       = 0x1c08,
-CME_STOP_EXIT_SELF_RES_SPATTN       = 0x1c09,
-CME_STOP_EXIT_STARTCLK_FAILED       = 0x1c0a,
-CME_STOP_ENTRY_STOPCLK_FAILED       = 0x1c0d,
-CME_STOP_ENTRY_XSTOP_ERROR          = 0x1c1c,
-CME_STOP_ENTRY_WITH_AUTO_NAP        = 0x1c1d, // NDD1
-CME_STOP_ENTRY_BAD_LPID_ERROR       = 0x1c1e, // NDD1
-//_UNUSED_1c1f                      = 0x1c1f,
+CME_STOP_NO_PARTIAL_GOOD_CORE       = 0x1c05,
+CME_STOP_PUTRING_HEADER_ERROR       = 0x1c06,
+CME_STOP_BCE_CORE_RING_FAILED       = 0x1c07,
+CME_STOP_EXIT_PHANTOM_WAKEUP        = 0x1c08,
+CME_STOP_EXIT_BCE_SCOM_FAILED       = 0x1c09,
+CME_STOP_EXIT_SELF_RES_SPATTN       = 0x1c0a,
+CME_STOP_EXIT_STARTCLK_FAILED       = 0x1c0d,
+CME_STOP_ENTRY_STOPCLK_FAILED       = 0x1c1c,
+CME_STOP_ENTRY_XSTOP_ERROR          = 0x1c1d,
+CME_STOP_ENTRY_WITH_AUTO_NAP        = 0x1c1e, // NDD1
+CME_STOP_ENTRY_BAD_LPID_ERROR       = 0x1c1f, // NDD1
 //
 //_UNUSED_1d00                      = 0x1d00,
 //_UNUSED_1d01                      = 0x1d01,
diff --git a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c
index 644559d9..d78513f0 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/p9_cme_main.c
@@ -182,6 +182,10 @@ main(int argc, char** argv)
         out32(CME_LCL_LMCR_OR, BITS32(8, 2));
     }
 
+#if defined(USE_CME_QUEUED_SCOM) && defined(USE_PPE_IMPRECISE_MODE)
+    out32(CME_LCL_LMCR_OR, BITS32(8, 2));
+#endif
+
     // Unified interrupt handler checks
     if (IDX_PRTY_LVL_DISABLED != (NUM_EXT_IRQ_PRTY_LEVELS - 1))
     {
@@ -197,58 +201,6 @@ main(int argc, char** argv)
         PK_PANIC(CME_UIH_NOT_ALL_IN_PRTY_GROUP);
     }
 
-
-    //Currently, commenting this.
-    //This shouldn't really be here at all as SGPE will write this register.
-    //For verification in SIMICS, SOA, EPM currently just write the CME_LCL_FLAGS manually
-    //
-    //
-    //
-    /*   //CMO-Temporary setting
-    // Setup up CME_LCL_FLAGS to indicate whether
-    // this CME is QMGR master or slave.
-    // Rules:
-    // - If even CME then set FLAGS(3)=1. Otherwise =0.
-    // - Whether in CME or Simics or HW,
-    //   the assumption here is that the even CME in
-    //   a configured Quad is always configured.
-    uint32_t l_pir;
-    asm volatile ("mfpir %[data] \n" : [data]"=r"(l_pir) );
-
-    #ifndef _SOA_SC_ENVIRONMENT_
-    if ( l_pir & PIR_INSTANCE_EVEN_ODD_MASK )
-    {
-        // Odd: Set slave status
-        out32(CME_LCL_FLAGS_CLR, CME_FLAGS_QMGR_MASTER);
-    }
-    else
-    {
-        // Even: Set master status
-        out32(CME_LCL_FLAGS_OR, CME_FLAGS_QMGR_MASTER);
-    }
-
-    #else
-
-    if ( l_pir & PIR_INSTANCE_EVEN_ODD_MASK )
-    {
-        // Odd: Set slave status
-        out32(CME_LCL_FLAGS_OR, CME_FLAGS_QMGR_MASTER);
-    }
-    else
-    {
-        // Even: Set master status
-        out32(CME_LCL_FLAGS_CLR, CME_FLAGS_QMGR_MASTER);
-    }
-
-    #endif
-
-    //\todo Fix  this
-    #ifndef _SOA_SC_ENVIRONMENT_
-    out32(CME_LCL_FLAGS_OR, CME_FLAGS_CORE0_GOOD | CME_FLAGS_CORE1_GOOD | CME_FLAGS_SIBLING_FUNCTIONAL);
-    #else
-    out32(CME_LCL_FLAGS_OR, CME_FLAGS_CORE0_GOOD | CME_FLAGS_CORE1_GOOD);
-    #endif
-    */
     // Initialize the thread control block for G_p9_cme_stop_exit_thread
     pk_thread_create(&G_p9_cme_stop_exit_thread,
                      (PkThreadRoutine)p9_cme_stop_exit_thread,
diff --git a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h
index ae9e69bd..ccdf0b5d 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h
+++ b/import/chips/p9/procedures/ppe_closed/cme/pk_app_cfg.h
@@ -37,6 +37,7 @@
 #define DEBUG_RUNTIME_STATE_CHECK 0
 
 #define USE_PPE_IMPRECISE_MODE
+#define USE_CME_QUEUED_SCOM
 
 /// @todo RTC 161182
 
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
index f5a15fcc..09a8a4de 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
@@ -203,7 +203,7 @@ void p9_cme_stop_exit_end(uint32_t core, uint32_t spwu_stop)
 
     while((in32(CME_LCL_EINR)) & (core << SHIFT32(21)));
 
-#ifdef USE_PPE_IMPRECISE_MODE
+#if defined(USE_CME_QUEUED_SCOM) && defined(USE_PPE_IMPRECISE_MODE)
 
     // execute sync before change pcbmux to prevent queued scom issues
     sync();
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
index e9a960ee..8b0a8b9a 100644
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_chiplet_reset.c
@@ -84,6 +84,13 @@ p9_hcd_core_chiplet_reset(uint32_t core)
     PK_TRACE("Drop PCB fence via NET_CTRL0[25]");
     CME_PUTSCOM(CPPM_NC0INDIR_CLR, core, BIT64(25));
 
+#if defined(USE_CME_QUEUED_SCOM) && defined(USE_PPE_IMPRECISE_MODE)
+
+    // execute sync before change pcbmux to prevent queued scom issues
+    sync();
+
+#endif
+
     // HW390253: The core clock controller itself is clocked at 2:1 versus the core clock,
     // so it will introduce an additional 2:1 into whatever scan raito is set up. Hence,
     // to get the core to scan at 4:1, need to put a scan ratio of 2:1 if run at pll speed.