diff options
| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2016-10-21 02:07:16 -0500 |
|---|---|---|
| committer | Joshua Hunsberger <jahunsbe@us.ibm.com> | 2017-10-23 16:53:18 -0500 |
| commit | e8562da550069c2045aa4cf856a251a303539fff (patch) | |
| tree | 547bb2004de347ceda6441ac204939fb18aed7f9 | |
| parent | dd088b547f762421f9fe4dd6630c1522e169814a (diff) | |
| download | talos-hcode-e8562da550069c2045aa4cf856a251a303539fff.tar.gz talos-hcode-e8562da550069c2045aa4cf856a251a303539fff.zip | |
PM: Image layout change for CME/SGPE Region of P9 HOMER.
- implements compact image layout for CME
- implements compact image layout for SGPE
- enhances ring debug infrastructure
- implements size check for consolidated CME/SGPE SRAM Image.
- Reversal of magic byte used to represent FUSED and NON FUSED core.
- enhances putring to support scan ring overrides.
- added gptr and time rings
- updated in SGPE debug pointer location and boot loader constants.
- Fixed ex instance ring issue (need to skip conversion of scan
region type for ex instance ring)
- memset for CME, SGPE override offset init and
sanity check in ring code.
Change-Id: Ifb6157dd73a24e0158e6a5f39844d897fba6af56
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32544
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
17 files changed, 730 insertions, 290 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 26353bac..e35faf40 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -58,6 +58,7 @@ CONST_UINT32_T(QPMR_HEADER_SIZE, 512); HCD_MAGIC_NUMBER(CPMR_MAGIC_NUMBER, ULL(0x43504d525f312e30)); // CPMR_1.0 HCD_MAGIC_NUMBER(QPMR_MAGIC_NUMBER, ULL(0x51504d525f312e30)); // QPMR_1.0 HCD_MAGIC_NUMBER(CME_MAGIC_NUMBER , ULL(0x434d455f5f312e30)); // CME__1.0 +HCD_MAGIC_NUMBER(SGPE_MAGIC_NUMBER, ULL(0x534750455f312e30 )); // SGPE_1.0 HCD_MAGIC_NUMBER(PGPE_MAGIC_NUMBER , ULL(0x504750455F312E30)); // PGPE_1.0 @@ -86,13 +87,16 @@ HCD_HDR_UINT32( sgpeImgOffset, 0); HCD_HDR_UINT32( sgpeImgLength, 0); HCD_HDR_UINT32( quadCommonRingOffset, 0); HCD_HDR_UINT32( quadCommonRingLength, 0); +HCD_HDR_UINT32( quadCommonOvrdOffset, 0 ); +HCD_HDR_UINT32( quadCommonOvrdLength, 0 ); HCD_HDR_UINT32( quadSpecRingOffset, 0); HCD_HDR_UINT32( quadSpecRingLength, 0); -HCD_HDR_UINT32( quadSpecScomOffset, 0); -HCD_HDR_UINT32( quadSpecScomLength, 0); -HCD_HDR_UINT32( quadCmnRingOccOffset, 0); -HCD_HDR_UINT32( quadSpecRingOccOffset, 0); -HCD_HDR_UINT32( quadCmnScomOccOffset, 0); +HCD_HDR_UINT32( quadScomOffset, 0); +HCD_HDR_UINT32( quadScomLength, 0); +HCD_HDR_UINT32( quad24x7Offset, 0); +HCD_HDR_UINT32( quad24x7Length, 0); +HCD_HDR_UINT32( stopFfdcOffset, 0); +HCD_HDR_UINT32( stopFfdcLength, 0); HCD_HDR_PAD(512); #ifdef __ASSEMBLER__ .endm @@ -176,9 +180,9 @@ HCD_HDR_UINT64(g_sgpe_reserve_flags, 0); HCD_HDR_UINT32(g_sgpe_cmn_ring_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_cmn_ring_ovrd_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_spec_ring_occ_offset, 0); -HCD_HDR_UINT32(g_sgpe_cmn_scom_offset, 0); -HCD_HDR_UINT32(g_sgpe_cmn_scom_mem_offset, 0); -HCD_HDR_UINT32(g_sgpe_cmn_scom_length, 0); +HCD_HDR_UINT32(g_sgpe_scom_offset, 0); +HCD_HDR_UINT32(g_sgpe_scom_mem_offset, 0); +HCD_HDR_UINT32(g_sgpe_scom_mem_length, 0); HCD_HDR_UINT32(g_sgpe_24x7_offset, 0); HCD_HDR_UINT32(g_sgpe_24x7_length, 0); HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); @@ -217,12 +221,12 @@ HCD_HDR_UINT32(g_cme_common_ring_length, 0); HCD_HDR_UINT32(g_cme_pstate_region_offset, 0); HCD_HDR_UINT32(g_cme_pstate_region_length, 0); HCD_HDR_UINT32(g_cme_core_spec_ring_offset, 0); -HCD_HDR_UINT32(g_cme_core_spec_ring_ovrd_offset, 0); HCD_HDR_UINT32(g_cme_max_spec_ring_length, 0); HCD_HDR_UINT32(g_cme_scom_offset, 0); HCD_HDR_UINT32(g_cme_scom_length, 0); HCD_HDR_UINT32(g_cme_mode_flags, 0); HCD_HDR_UINT32(g_cme_reserved1, 0); +HCD_HDR_UINT32(g_cme_reserved2, 0); //Retain next field at 8B boundary HCD_HDR_UINT64(g_cme_cpmr_PhyAddr, 0); HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); #ifdef __ASSEMBLER__ @@ -301,8 +305,8 @@ enum CORE0_CHIPLET_ID = 0x20, PAD_OPCODE = 0x00000200, //ATTN Opcode PPE_RESERVE_AREA = 0x200, - FUSE_STATE = 0xAA, - UNFUSE_STATE = 0xBB, + FUSED_MODE = 0xBB, + NONFUSED_MODE = 0xAA, PK_DBG_PTR_AREA_SIZE = 64, SCOM_ENTRY_SIZE = 16, // 4B pad, 4B address, 8B data @@ -319,8 +323,7 @@ enum SGPE_DBG_PTR_AREA_SIZE = 64, SGPE_HCODE_SIZE = (45 * ONE_KB) + HALF_KB, // @todo RTC 158543 Reallocate space - SGPE_EXE_SIZE = (SGPE_HCODE_SIZE - ( SGPE_INT_VECT + - SGPE_IMG_HEADER + PK_DBG_PTR_AREA_SIZE )), + SGPE_IMAGE_SIZE = 80 * ONE_KB, SGPE_ALLOCATED_SIZE = SGPE_HCODE_SIZE, // @todo RTC 158543 Reallocate space (collapse??) @@ -369,10 +372,11 @@ enum CME_INT_VECTOR_SIZE = 384, CME_IMG_HEADER_SIZE = 64, CPMR_CME_HCODE_OFFSET = (CORE_SCOM_START + CORE_SCOM_RES_SIZE), - CME_HCODE_SIZE = (30 * ONE_KB), //FIXME RTC 159737 Needs review before merge of P-State + CME_REGION_SIZE = (64 * ONE_KB), // CME hcode and data's footprint in HOMER + CME_SRAM_SIZE = (32 * ONE_KB ), //** Scan - CORE_COMMON_RING_SIZE = 1 * ONE_KB, // common ring( 2KB) + common overrides (1KB) + CORE_COMMON_RING_SIZE = 2 * ONE_KB, // common ring( 2KB) + common overrides (1KB) MAX_SIZE_CME_INST_RING = 1 * ONE_KB, CORE_OVERRIDE_RING = 1 * ONE_KB, // common for all cores QUAD_PSTATE_SIZE = HALF_KB, // common for all cores @@ -381,10 +385,6 @@ enum CME_SRAM_HCODE_OFFSET = 0x00, //(???) CME_INST_SPEC_RING_START = 300 * ONE_KB, CME_REGION_START = (CORE_SCOM_START + CORE_SCOM_RES_SIZE), - RESERVE_CME_RING_AREA = ( CME_INST_SPEC_RING_START - ( CME_REGION_START + - CME_HCODE_SIZE + - CORE_COMMON_RING_SIZE + - QUAD_PSTATE_SIZE)), CME_BLOCK_READ_LEN = 32, CME_BLK_SIZE_SHIFT = 0x05, @@ -442,6 +442,9 @@ enum ImgBldRetCode_t BUILD_SEC_SIZE_OVERFLOW = 28, BUILD_FAIL_INVALID_SECTN = 29, BUILD_FAIL_RING_EXTRACTN = 30, + CME_SRAM_IMG_SIZE_ERR = 31, + SGPE_SRAM_IMG_SIZE_ERR = 32, + PGPE_SRAM_IMG_SIZE_ERR = 33, }; /** @@ -599,12 +602,7 @@ typedef struct uint8_t qpmrHeader[sizeof(QpmrHeaderLayout_t)]; uint8_t l1BootLoader[SGPE_LVL_1_BOOT_LOAD_SIZE]; uint8_t l2BootLoader[SGPE_LVL_2_BOOT_LOAD_SIZE]; - uint8_t hcodeIntVect[SGPE_INT_VECT]; - uint8_t imgHeader[sizeof(sgpeHeader_t)]; - uint8_t debugPtrs[PK_DBG_PTR_AREA_SIZE]; - uint8_t hcode[SGPE_EXE_SIZE]; - CmnRingLayoutSgpe_t quadCmnRingArea; - InstRingLayoutSgpe_t quadSpecRingArea; + uint8_t sgpeSramImage[SGPE_IMAGE_SIZE]; } SgpeLayout_t; typedef union CPMRSelfRestoreLayout @@ -628,26 +626,10 @@ typedef struct uint8_t coreScom[CORE_SCOM_RES_SIZE]; } SelfRestoreLayout_t; -typedef union CmeHcodeLayout -{ - uint8_t hcode[CME_HCODE_SIZE]; - struct - { - uint8_t cmeIntVector[CME_INT_VECTOR_SIZE]; - cmeHeader_t imgHeader; - uint8_t exe[CME_HCODE_SIZE - CME_INT_VECTOR_SIZE - sizeof(cmeHeader_t)]; - } elements; -} CmeHcodeLayout_t; - - typedef struct { SelfRestoreLayout_t selfRestoreRegion; - CmeHcodeLayout_t cmeBin; - CoreCmnRingLayout_t coreCmnRingArea; - uint8_t quadPstateArea[QUAD_PSTATE_SIZE]; - uint8_t resvRingArea[RESERVE_CME_RING_AREA]; - CoreSpecRingLayout_t coreSpecRingArea[MAX_CME_PER_CHIP]; + uint8_t cmeSramRegion[CME_REGION_SIZE]; } CPMRLayout_t; /** diff --git a/import/chips/p9/procedures/hwp/lib/p9_stop_util.H b/import/chips/p9/procedures/hwp/lib/p9_stop_util.H index 0004736a..329b851a 100755 --- a/import/chips/p9/procedures/hwp/lib/p9_stop_util.H +++ b/import/chips/p9/procedures/hwp/lib/p9_stop_util.H @@ -88,11 +88,11 @@ namespace stopImageSection typedef struct { uint64_t attnOpcodes; - uint64_t homerMagicNumber; + uint64_t cpmrMagicWord; uint32_t buildDate; uint32_t version; uint8_t reserve1[7]; - uint8_t fuseModeStatus; + uint8_t fusedModeStatus; uint32_t cmeImgOffset; uint32_t cmeImgLength; uint32_t cmeCommonRingOffset; @@ -111,10 +111,10 @@ typedef struct */ enum { - FUSE_BIT0 = 0x08, - FUSE_BIT1 = 0x04, - FUSE_BIT2 = 0x02, - FUSE_BIT3 = 0x01, + FUSED_CORE_BIT0 = 0x08, + FUSED_CORE_BIT1 = 0x04, + FUSED_CORE_BIT2 = 0x02, + FUSED_CORE_BIT3 = 0x01, QUAD_BITS = 0x70 }; diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c index ace36071..90b5e68c 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_gptr_time_initf.c @@ -23,13 +23,22 @@ /* */ /* IBM_PROLOG_END_TAG */ +#include "plat_ring_traverse.h" #include "p9_cme_stop.h" #include "p9_cme_stop_exit_marks.h" +#include "p9_ringid_cme_enums.h" int p9_hcd_core_gptr_time_initf(uint32_t core) { int rc = CME_STOP_SUCCESS; // Markers needed for gptr time initf + + PK_TRACE_DBG("Scan ec_gptr ring core value %d", core); + putRing(core, CME_SCOM_EQ, ec_gptr); + + PK_TRACE_DBG("Scan ec_time ring core value %d", core); + putRing(core, CME_SCOM_EQ, ec_time); + return rc; } diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c index d973bfc7..76d1549e 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c +++ b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c @@ -245,7 +245,8 @@ void queuedScan(enum CME_CORE_MASKS i_core, int rs4DecompressionSvc( enum CME_CORE_MASKS i_core, enum CME_SCOM_CONTROLS i_scom_op, - uint8_t* i_rs4) + uint8_t* i_rs4, + uint8_t i_applyOverride) { CompressedScanData_t* l_rs4Header = (CompressedScanData_t*) i_rs4; uint8_t* l_rs4Str = (i_rs4 + sizeof(CompressedScanData_t)); @@ -256,10 +257,16 @@ int rs4DecompressionSvc( uint32_t l_bitsDecoded = 0; uint64_t l_scanRegion = rs4_revle64(l_rs4Header->iv_scanSelect); uint32_t l_scanData = 0; - PK_TRACE ("rs4DecompressionSvc"); + uint8_t l_mask = 0x08; do { + if (!l_scanRegion) + { + PK_TRACE_INF("No data in RS4 container so coming out"); + break; + } + // Set up the scan region for the ring. CME_PUTSCOM(0x00030005, i_core, l_scanRegion); @@ -285,6 +292,7 @@ int rs4DecompressionSvc( { // Determine the no.of ROTATE operations encoded in stop-code uint32_t l_count = 0; + l_scanData = 0; l_nibbleIndx += stop_decode(l_rs4Str, l_nibbleIndx, &l_count); // Determine the no.of rotates in bits @@ -314,23 +322,102 @@ int rs4DecompressionSvc( { uint32_t l_scanCount = rs4_get_nibble(l_rs4Str, l_nibbleIndx); l_nibbleIndx++; + l_scanData = 0; if (l_scanCount == 0) { - PK_TRACE("SCAN COUNT 0"); break; } - l_bitsDecoded += (4 * l_scanCount); - - // Parse the non-zero nibbles of the RS4 string and - // scan them into the ring - l_scomData = rs4_get_verbatim(l_rs4Str, - l_nibbleIndx, - l_scanCount); - l_nibbleIndx += l_scanCount; - l_opValue = SCAN; - l_scanData = l_scanCount * 4; + if ((!i_applyOverride) && l_scanCount != 0xF) + { + l_bitsDecoded += (4 * l_scanCount); + + // Parse the non-zero nibbles of the RS4 string and + // scan them into the ring + l_scomData = rs4_get_verbatim(l_rs4Str, + l_nibbleIndx, + l_scanCount); + l_nibbleIndx += l_scanCount; + l_opValue = SCAN; + l_scanData = l_scanCount * 4; + } + else // We are parsing RS4 for override rings + { + if(0xF == l_scanCount) // We are parsing RS4 for override rings + { + i_applyOverride = 1; + uint8_t l_careMask = + rs4_get_nibble(l_rs4Str, l_nibbleIndx); + l_nibbleIndx++; + uint8_t l_spyData = + rs4_get_nibble(l_rs4Str, l_nibbleIndx); + l_nibbleIndx++; + uint8_t i = 0; + + for(i = 0; i < 4; i++) + { + l_bitsDecoded += 1; + l_scomData = 0x0; + + if((l_careMask & (l_mask >> i))) + { + if((l_spyData & (l_mask >> i))) + { + l_scomData = 0xFFFFFFFFFFFFFFFF; + } + + l_opValue = SCAN; + } + else + { + l_opValue = ROTATE; + } + + queuedScan(i_core, + i_scom_op, + l_opValue, + 1, + l_scomData); + } // end of looper for bit-parsing a non-zero nibble + } + else // We are parsing RS4 for base rings + { + uint8_t x = 0; + uint8_t i = 0; + + for (x = 0; x < l_scanCount; x++) + { + // Parse the non-zero nibbles of the RS4 string and + // scan them into the ring + uint8_t l_data = + rs4_get_nibble(l_rs4Str, l_nibbleIndx); + l_nibbleIndx += 1; + + for(i = 0; i < 4; i++) + { + l_scomData = 0x0; + + if((l_data & (l_mask >> i))) + { + l_opValue = SCAN; + l_scomData = 0xFFFFFFFFFFFFFFFF; + } + else + { + l_opValue = ROTATE; + } + + queuedScan(i_core, + i_scom_op, + l_opValue, + 1, + l_scomData); + }//end of for loop + + } // end of looper for bit-parsing a non-zero nibble + } + } l_opType = ROTATE; } // end of - if(l_opType == SCAN) @@ -360,16 +447,89 @@ int rs4DecompressionSvc( } else { - l_bitsDecoded += l_nibble; - uint64_t l_scomData = rs4_get_verbatim(l_rs4Str, - l_nibbleIndx, - 1); // return 1 nibble + if (!i_applyOverride) + { + l_bitsDecoded += l_nibble; + uint64_t l_scomData = rs4_get_verbatim(l_rs4Str, + l_nibbleIndx, + 1); // return 1 nibble + queuedScan(i_core, + i_scom_op, + SCAN, + (4 - l_padding_bits) , // scan 4 bits + l_scomData); + } + else + { + PK_TRACE_INF("OVERRIDE !!!!!!"); - queuedScan(i_core, - i_scom_op, - SCAN, - (4 - l_padding_bits) , // scan 4 bits - l_scomData); + if(0x8 & l_nibble) // We are parsing RS4 for override rings + { + uint8_t l_careMask = rs4_get_nibble(l_rs4Str, l_nibbleIndx); + l_nibbleIndx++; + uint8_t l_spyData = rs4_get_nibble(l_rs4Str, l_nibbleIndx); + l_nibbleIndx++; + uint8_t i = 0; + + for(i = 0; i < 4; i++) + { + l_bitsDecoded += 1; + l_scomData = 0x0; + + if((l_careMask & (l_mask >> i))) + { + if((l_spyData & (l_mask >> i))) + { + l_scomData = 0xFFFFFFFFFFFFFFFF; + } + + l_opValue = SCAN; + } + else + { + l_opValue = ROTATE; + } + + queuedScan(i_core, + i_scom_op, + l_opValue, + 1, + l_scomData); + } // end of looper for bit-parsing a non-zero nibble + } + else // We are parsing RS4 for base rings + { + // scan them into the ring + uint8_t l_data = rs4_get_nibble(l_rs4Str, l_nibbleIndx); + uint8_t i = 0; + + l_nibbleIndx += 1; + + for(i = 0; i < l_nibble; i++) + { + l_scomData = 0x0; + l_bitsDecoded += 1; + + if((l_data & (l_mask >> i))) + { + l_opValue = SCAN; + l_scomData = 0xFFFFFFFFFFFFFFFF; + + } + else + { + l_opValue = ROTATE; + + } + + queuedScan(i_core, + i_scom_op, + l_opValue, + 1, + l_scomData); + } //end of for + } + } } } // end of if(l_nibble != 0) @@ -377,15 +537,12 @@ int rs4DecompressionSvc( uint64_t l_readHeader = 0; CME_GETSCOM(0x0003E000, i_core, i_scom_op, l_readHeader); + PK_TRACE_DBG ("l_readHeader %08X %08X", l_readHeader >> 32, l_readHeader); + if(l_readHeader != 0xa5a5a5a5a5a5a5a5) { - PK_TRACE("Check word data mismatch"); pk_halt(); } - else - { - PK_TRACE("CHECK WORD DATA MATCH Hurrayy !!!!!!"); - } // Clean scan region and type data CME_PUTSCOM(0x00030005, i_core, 0); diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.h b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.h index d56976c7..a19b7e37 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.h +++ b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.h @@ -177,10 +177,12 @@ int verifyHeader(enum CME_CORE_MASKS i_core, // @param[in] i_core - core select value // @param[in] i_scom_op - scom control value like queue/non-queue /// @param[in] i_rs4 The RS4 compressed string +// @param[in] i_applyOverride- 0 (no override) 1 (override mode) int rs4DecompressionSvc( enum CME_CORE_MASKS i_core, enum CME_SCOM_CONTROLS i_scom_op, - uint8_t* i_rs4); + uint8_t* i_rs4, + uint8_t i_applyOverride); #endif diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c b/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c index 0694b4fe..70e76fea 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c +++ b/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c @@ -80,17 +80,14 @@ int putRing( l_chipletData.iv_num_instance_rings = 0; l_chipletData.iv_num_variants = 0; uint8_t l_chipletID = 0; - uint32_t* l_sectionAddr; - uint16_t* l_ringTorAddr; - + uint32_t* l_sectionAddr = 0; + uint16_t* l_ringTorAddr = 0; getRingProperties(i_ringID, &l_torOffset, &l_ringType); - CmeHcodeLayout_t* l_hcodeLayout = (CmeHcodeLayout_t*)(CME_SRAM_BASE); - - cmeHeader_t* l_cmeHeader = - (cmeHeader_t*) & l_hcodeLayout->elements.imgHeader; + uint8_t* pCmeImage = (uint8_t*)(CME_SRAM_BASE); + cmeHeader_t* l_cmeHeader = (cmeHeader_t*) ( pCmeImage + CME_INT_VECTOR_SIZE ); l_chipletData = g_ecData; @@ -131,16 +128,44 @@ int putRing( } - if(*l_ringTorAddr != 0) + if((l_ringTorAddr) && (*l_ringTorAddr != 0)) { uint8_t* l_addr = (uint8_t*)(l_sectionAddr); uint8_t* l_rs4Address = (uint8_t*)(l_addr + *l_ringTorAddr); - l_rc = rs4DecompressionSvc(i_core, i_scom_op, l_rs4Address); + l_rc = rs4DecompressionSvc(i_core, i_scom_op, l_rs4Address, 0); } else { - PK_TRACE("No data for this ringId %d", i_ringID); + PK_TRACE_DBG("No data for this ringId %d in .RING section", i_ringID); } + + if(INSTANCE_RING != l_ringType) + { + if (!(l_cmeHeader->g_cme_cmn_ring_ovrd_offset)) + { + break; + } + + l_sectionAddr = + (uint32_t*)(CME_SRAM_BASE + l_cmeHeader->g_cme_cmn_ring_ovrd_offset); + // TOR records of Ring TOR are 2 bytes in size. + l_ringTorAddr = (uint16_t*)(l_sectionAddr) + (l_torOffset); + + if((l_ringTorAddr) && (*l_ringTorAddr != 0)) + { + uint8_t* l_addr = (uint8_t*)(l_sectionAddr); + uint8_t* l_rs4Address = (uint8_t*)(l_addr + *l_ringTorAddr); + l_rc = rs4DecompressionSvc(i_core, i_scom_op, l_rs4Address, 1); + } + else + { + PK_TRACE_DBG("No data for this ringId %d in .OVERRIDE section", i_ringID); + } + + } + + + } while(0); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_loader.S b/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_loader.S index 26a2b04b..76d4f2c9 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_loader.S +++ b/import/chips/p9/procedures/ppe_closed/sgpe/boot/sgpe_boot_loader.S @@ -82,7 +82,7 @@ __bootLoader: _liw %r9, SRAM_SGPE_BOOT_LOADER_ADDR _liw %r8, SGPE_IVPR_OCI_ADDR stw r9, 0(r8) - + ## Enable halt on trap lis %r3, 0x0100 li %r3, 0 @@ -194,7 +194,7 @@ end_specific_rings: ## start copying mtctr r5 nop - + payload_copy_loop: lvd d28, 0(r8) stvd d28, 0(r4) @@ -217,7 +217,7 @@ payload_copy_loop: _liw %r9, SRAM_SGPE_BASE_ADDR _liw %r8, SGPE_IVPR_OCI_ADDR stw r9, 0(r8) - + blr .epilogue __bootLoader diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/link.cmd b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/link.cmd index f3889abd..8f069e29 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/link.cmd +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/link.cmd @@ -35,7 +35,7 @@ OUTPUT_FORMAT(elf32-powerpc); // GPE3 is loaded at 0xfff30000 #define SRAM_START 0xfff30000 #define SRAM_LENGTH 0x10000 -#define PPE_DEBUG_PTRS_OFFSET 0x1C0 +#define PPE_DEBUG_PTRS_OFFSET 0x200 #define SGPE_IMAGE_OFFSET 0x180 MEMORY diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_gptr_time_initf.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_gptr_time_initf.C new file mode 100644 index 00000000..3725e197 --- /dev/null +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_gptr_time_initf.C @@ -0,0 +1,112 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_gptr_time_initf.C $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2016,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_gptr_time_init.C +/// @brief Load gptr and time ring for EX non-core +/// +/// Procedure Summary: +/// Load cache ring images from MVPD +/// These rings must contain ALL chip customization data. +/// This includes the following: Repair Power headers, and DTS +/// Historically this was stored in MVPD keywords are #R, #G. Still stored in +/// MVPD, but SBE image is customized with rings for booting cores + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include "p9_sgpe_stop.h" +#include "p9_sgpe_stop_exit_marks.h" +#include "hw_access.H" +#include "p9_ringid_sgpe.H" +#include <fapi2.H> + + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Load Repair ring for cache +//------------------------------------------------------------------------------ + + +extern "C" int p9_hcd_cache_gptr_time_initf(uint32_t quad) +{ + FAPI_INF(">>p9_hcd_cache_gptr_time_initf"); + + int rc = SGPE_STOP_SUCCESS; + fapi2::Target<fapi2::TARGET_TYPE_EQ> l_eqTarget + ( + fapi2::plat_getTargetHandleByChipletNumber((uint8_t)quad + EQ_CHIPLET_OFFSET) + ); + + auto l_ex_targets = l_eqTarget.getChildren<fapi2::TARGET_TYPE_EX>(); + + FAPI_DBG("Scan eq_gptr ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_gptr)); + + FAPI_DBG("Scan eq_time ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_time)); + + for (auto l_ex : l_ex_targets) + { + FAPI_DBG("Scan ex_l3_gptr ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l3_gptr)); + + FAPI_DBG("Scan ex_l2_gptr ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l2_gptr)); + + FAPI_DBG("Scan ex_l3_refr_gptr ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l3_refr_gptr)); + + FAPI_DBG("Scan ex_l3_time ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l3_time)); + + FAPI_DBG("Scan ex_l2_time ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l2_time)); + + FAPI_DBG("Scan ex_l3_refr_time ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l3_refr_time)); + } + + FAPI_DBG("Scan eq_dpll_gptr ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_dpll_gptr)); + + FAPI_DBG("Scan eq_ana_gptr ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_ana_gptr)); + +fapi_try_exit: + + FAPI_INF("<<9_hcd_cache_gptr_time_init"); + return rc; +} diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c index e28d1396..32ebb9e3 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_sgpe_boot_cme.c @@ -191,12 +191,12 @@ BootErrorCode_t boot_cme( uint16_t i_bootCme ) //1. start of CME Image //2. Length of first block copy HomerImgDesc_t* pCpmrHdrAddr = (HomerImgDesc_t*)(CPMR_POSITION | SET_ADDR_MSB); // Set MSB to point OCI to PBA - PK_TRACE("Magic Number [ 0:31]: 0x%08x", ((pCpmrHdrAddr->homerMagicNumber & 0xffffffff00000000) >> 32)); - PK_TRACE("Magic Number [32:63]: 0x%08x", ((pCpmrHdrAddr->homerMagicNumber & 0x00000000ffffffff))); + PK_TRACE("Magic Number [ 0:31]: 0x%08x", ((pCpmrHdrAddr->cpmrMagicWord & 0xffffffff00000000) >> 32)); + PK_TRACE("Magic Number [32:63]: 0x%08x", ((pCpmrHdrAddr->cpmrMagicWord & 0x00000000ffffffff))); PK_TRACE("Build Date: 0x%08x", (pCpmrHdrAddr->buildDate)); PK_TRACE("Version : 0x%08x", (pCpmrHdrAddr->version)); - PK_TRACE("Fused Flag: 0x%08x", (pCpmrHdrAddr->fuseModeStatus)); + PK_TRACE("Fused Flag: 0x%08x", (pCpmrHdrAddr->fusedModeStatus)); PK_TRACE("Cme Hcode Offset: 0x%08x", (pCpmrHdrAddr->cmeImgOffset)); PK_TRACE("Cme Hcode Length: 0x%08x", (pCpmrHdrAddr->cmeImgLength)); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk index 1b25c814..8c44c7dc 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk @@ -30,7 +30,6 @@ TOP-C-SOURCES = p9_sgpe_stop_entry.c \ p9_hcd_cache_scan0.c \ p9_hcd_cache_poweron.c \ p9_hcd_cache_chiplet_reset.c \ - p9_hcd_cache_gptr_time_initf.c \ p9_hcd_cache_dpll_setup.c \ p9_hcd_cache_chiplet_init.c \ p9_hcd_cache_arrayinit.c \ @@ -53,6 +52,7 @@ TOP-CPP-SOURCES += p9_hcd_cache_dpll_initf.C TOP-CPP-SOURCES += p9_hcd_cache_chiplet_l3_dcc_setup.C TOP-CPP-SOURCES += p9_hcd_cache_dcc_skewadjust_setup.C TOP-CPP-SOURCES += p9_hcd_cache_repair_initf.C +TOP-CPP-SOURCES += p9_hcd_cache_gptr_time_initf.C UTILS_OBJECTS = $(UTILS-SRC:.C=.o) TOP_OBJECTS = $(TOP-C-SOURCES:.c=.o) $(TOP-S-SOURCES:.S=.o) $(TOP-CPP-SOURCES:.C=.o) diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C index 7afe6205..e633f0eb 100755 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C @@ -330,19 +330,12 @@ fapi2::ReturnCode verifyHeader(const fapi2::Target<fapi2::TARGET_TYPE_ALL>& fapi2::getScom(i_target, l_scomAddress, l_readHeader); - FAPI_INF("Got header - %016x", uint64_t(l_readHeader)); + PK_TRACE_DBG("Got header - %08x %08x", l_readHeader >> 32, l_readHeader); if(l_readHeader != i_header) { - FAPI_ERR("Read header(%016x) data incorrect", uint64_t(l_readHeader)); l_rc = fapi2::FAPI2_RC_PLAT_ERR_RING_HEADER_CHECK; pk_halt(); - break; - //PK_PANIC(0xFABD); - } - else - { - PK_TRACE("CHECK word matched"); } } while(0); @@ -354,11 +347,14 @@ fapi2::ReturnCode verifyHeader(const fapi2::Target<fapi2::TARGET_TYPE_ALL>& /// @brief Function to decompress the RS4 and apply the Ring data /// @param[in] i_target Chiplet Target of Scan /// @param[in] i_rs4 The RS4 compressed string -/// @param[in] i_scanType Type of Scan +/// @param[in] i_applyOverride 0 - no override 1- override mode +/// @param[in] i_ringType Common or Instance ring /// @return FAPI2_RC_SUCCESS if success, else error code. fapi2::ReturnCode rs4DecompressionSvc( const fapi2::Target<fapi2::TARGET_TYPE_ALL>& i_target, - const uint8_t* i_rs4) + const uint8_t* i_rs4, + bool i_applyOverride, + RINGTYPE i_ringType) { FAPI_INF(">> rs4DecompressionSvc"); CompressedScanData* l_rs4Header = (CompressedScanData*) i_rs4; @@ -372,6 +368,8 @@ fapi2::ReturnCode rs4DecompressionSvc( fapi2::ReturnCode l_rc; uint32_t l_chiplet = (l_rs4Header->iv_chipletId) << 24; uint32_t l_chipletID = i_target.getChipletNumber(); + uint8_t l_mask = 0x08; + uint64_t l_scomData = 0x0; if ( l_chipletID ) { @@ -381,7 +379,14 @@ fapi2::ReturnCode rs4DecompressionSvc( do { - if (fapi2::TARGET_TYPE_EX & i_target.getTargetType()) + if (!l_scanRegion) + { + PK_TRACE_INF("No valid data in RS4 container so coming out"); + break; + } + + if ((fapi2::TARGET_TYPE_EX & i_target.getTargetType()) && + (i_ringType != INSTANCE_RING)) { // this gives position of ex (0 or 1) uint32_t l_ex_number = i_target.getTargetNumber(); @@ -484,46 +489,72 @@ fapi2::ReturnCode rs4DecompressionSvc( break; } - if (l_scanCount != 0xF) + if ((!i_applyOverride) && l_scanCount != 0xF) { l_bitsDecoded += (4 * l_scanCount); - } - if(l_bitsDecoded > l_rs4Header->iv_length) - { - FAPI_ERR("Scan decompression done." - "l_bitsDecoded = %d, length = %d", - l_bitsDecoded, l_rs4Header->iv_length); - l_decompressionDone = true; - l_rc = fapi2::FAPI2_RC_PLAT_RING_DECODE_LENGTH_EXCEEDED; - break; - } + if(l_bitsDecoded > l_rs4Header->iv_length) + { + FAPI_ERR("Scan decompression done." + "l_bitsDecoded = %d, length = %d", + l_bitsDecoded, l_rs4Header->iv_length); + l_decompressionDone = true; + l_rc = fapi2::FAPI2_RC_PLAT_RING_DECODE_LENGTH_EXCEEDED; + break; + } - if(0xF == l_scanCount) // We are parsing RS4 for override rings - { - uint8_t l_careMask = rs4_get_nibble(l_rs4Str, l_nibbleIndx); - l_nibbleIndx++; - uint8_t l_spyData = rs4_get_nibble(l_rs4Str, l_nibbleIndx); - l_nibbleIndx++; + // Parse the non-zero nibbles of the RS4 string and + // scan them into the ring + l_scomData = rs4_get_verbatim(l_rs4Str, + l_nibbleIndx, + l_scanCount); + l_nibbleIndx += l_scanCount; - uint8_t l_mask = 0x08; + l_rc = standardScan(i_target, + l_chiplet, + SCAN, + (l_scanCount * 4), + l_scomData); - for(uint8_t i = 0; i < 4; i++) + if(l_rc != fapi2::FAPI2_RC_SUCCESS) + { + break; + } + } + else + { + if(0xF == l_scanCount) // We are parsing RS4 for override rings { - if((l_careMask & (l_mask >> i))) + i_applyOverride = true; + uint8_t l_careMask = + rs4_get_nibble(l_rs4Str, l_nibbleIndx); + l_nibbleIndx++; + uint8_t l_spyData = + rs4_get_nibble(l_rs4Str, l_nibbleIndx); + l_nibbleIndx++; + + for(uint8_t i = 0; i < 4; i++) { - uint64_t l_scomData = 0x0; + l_bitsDecoded += 1; + l_scomData = 0x0; - if((l_spyData & (l_mask >> i))) + if((l_careMask & (l_mask >> i))) { - l_scomData = 0xFFFFFFFFFFFFFFFF; - } + if((l_spyData & (l_mask >> i))) + { + l_scomData = 0xFFFFFFFFFFFFFFFF; + } - l_bitsDecoded += 1; + l_opType = SCAN; + } + else + { + l_opType = ROTATE; + } l_rc = standardScan(i_target, l_chiplet, - SCAN, + l_opType, 1, // Insert 1 bit l_scomData); @@ -531,56 +562,62 @@ fapi2::ReturnCode rs4DecompressionSvc( { break; } - } - else + } // end of looper for bit-parsing a non-zero nibble + } + else // We are parsing RS4 for base rings + { + for (uint8_t x = 0; x < l_scanCount; x++) { - l_bitsDecoded += 1; + // Parse the non-zero nibbles of the RS4 string and + // scan them into the ring + uint8_t l_data = + rs4_get_nibble(l_rs4Str, l_nibbleIndx); + l_nibbleIndx += 1; - l_rc = standardScan(i_target, - l_chiplet, - ROTATE, - 1, 0); + FAPI_INF ("VERBATIm l_nibbleIndx %u l_scanCount %u " + "l_bitsDecoded %u", l_nibbleIndx, l_scanCount, l_bitsDecoded); + + for(uint8_t i = 0; i < 4; i++) + { + l_scomData = 0x0; + + if((l_data & (l_mask >> i))) + { + l_opType = SCAN; + l_scomData = 0xFFFFFFFFFFFFFFFF; + } + else + { + l_opType = ROTATE; + } + + l_rc = standardScan(i_target, + l_chiplet, + l_opType, + 1, // Insert 1 bit + l_scomData); + + if(l_rc != fapi2::FAPI2_RC_SUCCESS) + { + break; + } + } if(l_rc != fapi2::FAPI2_RC_SUCCESS) { break; } - - - } - } // end of looper for bit-parsing a non-zero nibble - - if(l_rc != fapi2::FAPI2_RC_SUCCESS) - { - break; - } - } - else // We are parsing RS4 for base rings - { - // Parse the non-zero nibbles of the RS4 string and - // scan them into the ring - uint64_t l_scomData = rs4_get_verbatim(l_rs4Str, - l_nibbleIndx, - l_scanCount); - l_nibbleIndx += l_scanCount; - - FAPI_INF ("VERBATIm l_nibbleIndx %u l_scanCount %u " - "l_bitsDecoded %u", l_nibbleIndx, l_scanCount, l_bitsDecoded); - - l_rc = standardScan(i_target, - l_chiplet, - SCAN, - (l_scanCount * 4), - l_scomData); - - if(l_rc != fapi2::FAPI2_RC_SUCCESS) - { - break; + } // end of looper for bit-parsing a non-zero nibble } } l_opType = ROTATE; } // end of - if(l_opType == SCAN) + + if(l_rc != fapi2::FAPI2_RC_SUCCESS) + { + break; + } } while(1); @@ -607,19 +644,98 @@ fapi2::ReturnCode rs4DecompressionSvc( } else { - l_bitsDecoded += l_nibble; - uint64_t l_scomData = rs4_get_verbatim(l_rs4Str, - l_nibbleIndx, - 1); // return 1 nibble - - FAPI_INF ("l_nibbleIndx %u l_scomData %llu l_bitsDecoded %u", - l_nibbleIndx, l_scomData, l_bitsDecoded); - - l_rc = standardScan(i_target, - l_chiplet, - SCAN, - (4 - l_padding_bits) , // scan 4 bits - l_scomData); + if (!i_applyOverride) + { + l_bitsDecoded += l_nibble; + l_scomData = rs4_get_verbatim(l_rs4Str, + l_nibbleIndx, + 1); // return 1 nibble + + l_rc = standardScan(i_target, + l_chiplet, + SCAN, + (4 - l_padding_bits) , // scan 4 bits + l_scomData); + } + else + { + PK_TRACE_INF("OVERRIDE |||||||||||"); + + if(0x8 & l_nibble) // We are parsing RS4 for override rings + { + uint8_t l_careMask = rs4_get_nibble(l_rs4Str, l_nibbleIndx); + l_nibbleIndx++; + uint8_t l_spyData = rs4_get_nibble(l_rs4Str, l_nibbleIndx); + l_nibbleIndx++; + + for(uint8_t i = 0; i < 4; i++) + { + l_bitsDecoded += 1; + l_scomData = 0x0; + + if((l_careMask & (l_mask >> i))) + { + if((l_spyData & (l_mask >> i))) + { + l_scomData = 0xFFFFFFFFFFFFFFFF; + } + + l_opType = SCAN; + } + else + { + l_opType = ROTATE; + } + + l_rc = standardScan(i_target, + l_chiplet, + l_opType, + 1, // Insert 1 bit + l_scomData); + + if(l_rc != fapi2::FAPI2_RC_SUCCESS) + { + break; + } + } // end of looper for bit-parsing a non-zero nibble + } + else // We are parsing RS4 for base rings + { + // scan them into the ring + uint8_t l_data = rs4_get_nibble(l_rs4Str, l_nibbleIndx); + + l_nibbleIndx += 1; + + for(uint8_t i = 0; i < l_nibble; i++) + { + l_scomData = 0x0; + l_bitsDecoded += 1; + + if((l_data & (l_mask >> i))) + { + l_opType = SCAN; + l_scomData = 0xFFFFFFFFFFFFFFFF; + + } + else + { + l_opType = ROTATE; + + } + + l_rc = standardScan(i_target, + l_chiplet, + l_opType, + 1, // Insert 1 bit + l_scomData); + + if(l_rc != fapi2::FAPI2_RC_SUCCESS) + { + break; + } + } //end of for + } + } } } // end of if(l_nibble != 0) diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.H b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.H index 29305055..155fad74 100755 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.H +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.H @@ -194,10 +194,14 @@ fapi2::ReturnCode verifyHeader(const fapi2::Target<fapi2::TARGET_TYPE_ALL>& /// @brief Function to decompress the RS4 and apply the Ring data /// @param[in] i_target Chiplet Target of Scan /// @param[in] i_rs4 The RS4 compressed string +/// @param[in] i_applyOverride 0 - no override 1- override mode +/// @param[in] i_ringType Common or Instance ring /// @return FAPI2_RC_SUCCESS if success, else error code. fapi2::ReturnCode rs4DecompressionSvc( const fapi2::Target<fapi2::TARGET_TYPE_ALL>& i_target, - const uint8_t* i_rs4); + const uint8_t* i_rs4, + bool i_applyOverride, + RINGTYPE i_ringType); /// @brief Function to clean up the scan region and type diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C index 00e454ac..57bfaf00 100755 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C @@ -47,7 +47,6 @@ fapi2::ReturnCode findRS4InImageAndApply( do { - FAPI_INF("findRS4InImageAndApply i_ringID %d", i_ringID); // Determine the Offset ID and Ring Type for the given Ring ID. uint32_t l_torOffset = 0; RINGTYPE l_ringType = COMMON_RING; @@ -72,7 +71,7 @@ fapi2::ReturnCode findRS4InImageAndApply( { if (l_hcodeLayout->g_sgpe_spec_ring_occ_offset == 0) { - FAPI_INF("No data in Instance spec ring section"); + break; } l_sectionAddr = @@ -86,10 +85,9 @@ fapi2::ReturnCode findRS4InImageAndApply( if (fapi2::TARGET_TYPE_EX & (i_target.getTargetType())) { l_ex_number = (i_target.getTargetNumber()) % 2; - PK_TRACE ("l_chipletID %d l_ex_number %d", l_chipletID, l_ex_number); + PK_TRACE_DBG ("l_chipletID %d l_ex_number %d", l_chipletID, l_ex_number); } - //12 is considered as instance ring size l_ringTorAddr = reinterpret_cast<uint16_t*>(l_sectionAddr ) + ((l_chipletOffset * 12) + (l_torOffset + l_ex_number)); } @@ -98,7 +96,7 @@ fapi2::ReturnCode findRS4InImageAndApply( { if (l_hcodeLayout->g_sgpe_cmn_ring_occ_offset == 0) { - FAPI_INF("No data in common ring section"); + break; } l_sectionAddr = @@ -108,17 +106,43 @@ fapi2::ReturnCode findRS4InImageAndApply( } - if(*l_ringTorAddr != 0) + if((l_ringTorAddr) && (*l_ringTorAddr != 0)) { uint8_t* l_addr = (uint8_t*)(l_sectionAddr); uint8_t* l_rs4Address = (uint8_t*)(l_addr + *l_ringTorAddr); - FAPI_INF("l_rs4Address %08x", l_rs4Address); - l_rc = rs4DecompressionSvc(i_target, l_rs4Address); + l_rc = rs4DecompressionSvc(i_target, l_rs4Address, false, l_ringType); } else { - FAPI_INF("No data for this ringId %d", i_ringID); + PK_TRACE_DBG("No data for this ringId %d in .RING section", i_ringID); } + + if(INSTANCE_RING != l_ringType) + { + if (l_hcodeLayout->g_sgpe_cmn_ring_ovrd_occ_offset == 0) + { + PK_TRACE_DBG("No data in common ring section"); + break; + } + + l_sectionAddr = + (uint32_t*)(SGPE_SRAM_BASE + l_hcodeLayout->g_sgpe_cmn_ring_ovrd_occ_offset); + + l_ringTorAddr = reinterpret_cast<uint16_t*>(l_sectionAddr) + (l_torOffset); + + + if((l_ringTorAddr) && (*l_ringTorAddr != 0)) + { + uint8_t* l_addr = (uint8_t*)(l_sectionAddr); + uint8_t* l_rs4Address = (uint8_t*)(l_addr + *l_ringTorAddr); + l_rc = rs4DecompressionSvc(i_target, l_rs4Address, true, l_ringType); + } + else + { + PK_TRACE_DBG("No data for this ringId %d in .OVERRIDE section", i_ringID); + } + } + } while(0); diff --git a/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C b/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C index 85664524..ba5547f9 100755 --- a/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C +++ b/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C @@ -487,6 +487,13 @@ StopReturnCode_t p9_stop_save_cpureg( void* const i_pImage, l_rc = getCoreAndThread( i_pImage, i_pir, &coreId, &threadId ); + if( l_rc ) + { + MY_ERR("Failed to determine Core Id and Thread Id from PIR 0x%016llx", + i_pir); + break; + } + MY_INF( " PIR 0x%016llx coreId %d threadid %d " " registerId %d", i_pir, coreId, threadId, i_regId ); diff --git a/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H b/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H index 2f9f8ce3..21f0a077 100755 --- a/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H +++ b/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H @@ -78,7 +78,8 @@ typedef enum STOP_SAVE_SCOM_INVALID_ADDRESS = 10, STOP_SAVE_SCOM_INVALID_CHIPLET = 11, STOP_SAVE_SCOM_ENTRY_UPDATE_FAILED = 12, - STOP_SAVE_FAIL = 13, // for internal failure within firmware. + STOP_SAVE_INVALID_FUSED_CORE_STATUS = 13, + STOP_SAVE_FAIL = 14, // for internal failure within firmware. } StopReturnCode_t; /** diff --git a/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C b/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C index 27f3ad61..902ed28d 100755 --- a/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C +++ b/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C @@ -45,53 +45,53 @@ namespace stopImageSection /** * @brief Returns proc chip's fuse mode status. * @param i_pImage points to start of chip's HOMER image. - * @param o_fuseMode points to fuse mode information. + * @param o_fusedMode points to fuse mode information. * @return STOP_SAVE_SUCCESS if functions succeeds, error code otherwise. */ -StopReturnCode_t isFusedMode( void* const i_pImage, bool* o_fuseMode ) +StopReturnCode_t isFusedMode( void* const i_pImage, bool* o_fusedMode ) { - *o_fuseMode = false; - StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; +*o_fusedMode = false; +StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; - do +do +{ + if( !i_pImage ) { - if( !i_pImage ) - { - MY_ERR( "invalid pointer to HOMER image"); - l_rc = STOP_SAVE_ARG_INVALID_IMG; - break; - } + MY_ERR( "invalid pointer to HOMER image"); + l_rc = STOP_SAVE_ARG_INVALID_IMG; + break; + } - HomerSection_t* pHomerDesc = ( HomerSection_t* ) i_pImage; - HomerImgDesc_t* pHomer = (HomerImgDesc_t*)( pHomerDesc->interrruptHandler ); - - if( SWIZZLE_8_BYTE(HOMER_MAGIC_WORD) != pHomer->homerMagicNumber ) - { - MY_ERR("corrupt or invalid HOMER image location 0x%016llx", - pHomer->homerMagicNumber ); - break; - } + HomerSection_t* pHomerDesc = ( HomerSection_t* ) i_pImage; + HomerImgDesc_t* pHomer = (HomerImgDesc_t*)( pHomerDesc->interrruptHandler ); + if( SWIZZLE_8_BYTE(CPMR_MAGIC_WORD) != pHomer->cpmrMagicWord ) + { + MY_ERR("corrupt or invalid HOMER image location 0x%016llx", + SWIZZLE_8_BYTE(pHomer->cpmrMagicWord) ); + l_rc = STOP_SAVE_ARG_INVALID_IMG; + break; + } - if( (uint8_t) FUSE_MODE == pHomer->fuseModeStatus ) - { - *o_fuseMode = true; - break; - } + if( (uint8_t) FUSED_MODE == pHomer->fusedModeStatus ) + { + *o_fusedMode = true; + break; + } - if( (uint8_t) REGULAR_MODE == pHomer->fuseModeStatus ) - { - break; - } + if( (uint8_t) NONFUSED_MODE == pHomer->fusedModeStatus ) + { + break; + } - MY_ERR("Unexpected value 0x%08x for fuse mode. Bad or corrupt " - "HOMER location", pHomer->fuseModeStatus ); - l_rc = STOP_SAVE_FAIL; + MY_ERR("Unexpected value 0x%08x for fused mode. Bad or corrupt " + "HOMER location", pHomer->fuseModeStatus ); + l_rc = STOP_SAVE_INVALID_FUSED_CORE_STATUS ; - } - while(0); +} +while(0); - return l_rc; +return l_rc; } //---------------------------------------------------------------------- @@ -99,80 +99,81 @@ StopReturnCode_t isFusedMode( void* const i_pImage, bool* o_fuseMode ) StopReturnCode_t getCoreAndThread( void* const i_pImage, const uint64_t i_pir, uint32_t* o_pCoreId, uint32_t* o_pThreadId ) { - StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; +StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; - do +do +{ + // for SPR restore using 'Virtual Thread' and 'Physical Core' number + // In Fused Mode: + // bit b28 and b31 of PIR give physical core and b29 and b30 gives + // virtual thread id. + // In Non Fused Mode + // bit 28 and b29 of PIR give both logical and physical core number + // whereas b30 and b31 gives logical and virtual thread id. + bool fusedMode = false; + uint8_t coreThreadInfo = (uint8_t)i_pir; + *o_pCoreId = 0; + *o_pThreadId = 0; + l_rc = isFusedMode( i_pImage, &fusedMode ); + + if( l_rc ) { - // for SPR restore using 'Virtual Thread' and 'Physical Core' number - // In Fuse Mode: - // bit b28 and b31 of PIR give physical core and b29 and b30 gives - // virtual thread id. - // In Non Fuse Mode - // bit 28 and b29 of PIR give both logical and physical core number - // whereas b30 and b31 gives logical and virtual thread id. - bool fuseMode = false; - uint8_t coreThreadInfo = (uint8_t)i_pir; - *o_pCoreId = 0; - *o_pThreadId = 0; - l_rc = isFusedMode( i_pImage, &fuseMode ); - - if( l_rc ) + MY_ERR(" Checking Fused mode. Read failed 0x%08x", l_rc ); + break; + } + + if( fusedMode ) + { + if( coreThreadInfo & FUSED_CORE_BIT1 ) + { + *o_pThreadId = 2; + } + + if( coreThreadInfo & FUSED_CORE_BIT2 ) + { + *o_pThreadId += 1; + } + + if( coreThreadInfo & FUSED_CORE_BIT0 ) + { + *o_pCoreId = 2; + } + + if( coreThreadInfo & FUSED_CORE_BIT3 ) + { + *o_pCoreId += 1; + } + } + else + { + if( coreThreadInfo & FUSED_CORE_BIT0 ) { - MY_ERR(" Checking Fuse mode. Read failed 0x%08x", l_rc ); - break; + *o_pCoreId = 2; } - if( fuseMode ) + if ( coreThreadInfo & FUSED_CORE_BIT1 ) { - if( coreThreadInfo & FUSE_BIT1 ) - { - *o_pThreadId = 2; - } - - if( coreThreadInfo & FUSE_BIT2 ) - { - *o_pThreadId += 1; - } - - if( coreThreadInfo & FUSE_BIT0 ) - { - *o_pCoreId = 2; - } - - if( coreThreadInfo & FUSE_BIT3 ) - { - *o_pCoreId += 1; - } + *o_pCoreId += 1; } - else + + if( coreThreadInfo & FUSED_CORE_BIT2 ) { - if( coreThreadInfo & FUSE_BIT0 ) - { - *o_pCoreId = 2; - } - - if ( coreThreadInfo & FUSE_BIT1 ) - { - *o_pCoreId += 1; - } - - if( coreThreadInfo & FUSE_BIT2 ) - { - *o_pThreadId = 2; - } - - if( coreThreadInfo & FUSE_BIT3 ) - { - *o_pThreadId += 1; - } + *o_pThreadId = 2; } - //quad field is not affected by fuse mode - *o_pCoreId += 4 * (( coreThreadInfo & 0x70 ) >> 4 ); + if( coreThreadInfo & FUSED_CORE_BIT3 ) + { + *o_pThreadId += 1; + } } - while(0); - return l_rc; + MY_INF("Core Type %s", fusedMode ? "Fused" : "Un-Fused" ); + //quad field is not affected by fuse mode + *o_pCoreId += 4 * (( coreThreadInfo & 0x70 ) >> 4 ); +} +while(0); + +return l_rc; } #ifdef __cplusplus |

