STOP: Atomic lock of cache clock controller and PCB slave

Atomic lock the Cache clock controller before stopping L2 clocks.
Do not release it until both EXs exit Stop8.
Atomic lock the entire cache chiplet only for Stop11 entry, exit.

Change-Id: I6dce138bc1c10f54fafe86ad8f0eb305a6daf1c9
Original-Change-Id: I63691b707c17026ac744b461d40b438666c40d01
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37881
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

2 files changed, 24 insertions, 0 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
index 561a4e39..67183acd 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
@@ -79,6 +79,7 @@ extern "C" {
 #define EQ_CLK_REGION            0x10030006
 #define EQ_CLOCK_STAT_SL         0x10030008
 #define EQ_CLOCK_STAT_ARY        0x1003000A
+#define EQ_CC_ATOMIC_LOCK        0x100303FF
 #define EQ_HOST_ATTN             0x10040009
 #define EQ_LOCAL_XSTOP_ERR       0x10040018
 #define EQ_THERM_MODE_REG        0x1005000F
@@ -117,6 +118,7 @@ extern "C" {
 #define EQ_QPPM_QCCR             0x100F01BD
 #define EQ_QPPM_QCCR_WCLEAR      0x100F01BE
 #define EQ_QPPM_QCCR_WOR         0x100F01BF
+#define EQ_QPPM_ATOMIC_LOCK      0x100F03FF
 
 #define EX_L2_MODE_REG0          0x1001080A
 #define EX_L2_MODE_REG1          0x1001080B
diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
index 0a0ffcfa..4497e57a 100644
--- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
@@ -301,6 +301,17 @@ p9_sgpe_stop_entry()
 
         PK_TRACE_DBG("Check: q[%d]ex[%d] start ex entry", qloop, ex);
 
+        PK_TRACE("Acquire cache clock controller atomic lock");
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CC_ATOMIC_LOCK, qloop), BITS64(0, 5));
+        GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CC_ATOMIC_LOCK, qloop), scom_data.value);
+
+        if ((scom_data.words.upper & BITS32(0, 5)) != 0xC0000000)
+        {
+            PKTRACE("ERROR: Failed to Obtain Cache %d Clk Ctrl Atomic Lock. Register Content: %x",
+                    qloop, scom_data.words.upper);
+            pk_halt();
+        }
+
         PK_TRACE("Update QSSR: stop_entry_ongoing");
         out32(OCB_QSSR_OR, BIT32(qloop + 20));
 
@@ -503,6 +514,17 @@ p9_sgpe_stop_entry()
 
         PK_TRACE_DBG("Check: q[%d]ex[%d] starts quad entry", qloop, ex);
 
+        PK_TRACE("Acquire cache PCB slave atomic lock");
+        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_ATOMIC_LOCK, qloop), BITS64(0, 5));
+        GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_ATOMIC_LOCK, qloop), scom_data.value);
+
+        if ((scom_data.words.upper & BITS32(0, 5)) != 0xC0000000)
+        {
+            PKTRACE("ERROR: Failed to Obtain Cache %d PCB Slave Atomic Lock. Register Content: %x",
+                    qloop, scom_data.words.upper);
+            pk_halt();
+        }
+
         PK_TRACE("Update QSSR: stop_entry_ongoing");
         out32(OCB_QSSR_OR, BIT32(qloop + 20));