WOF: Pass PGPE VPD IQ good normal core per sort for WOF Phase 2

- p9_pstate_parameter_block fills in repurposed Pstate options field
- PGPE checks for non-zero value and uses for number of cores in vratio calc
- Forward and backward compatible with present (bad) behavior;  both Hostboot
  and Hcode must both be present for correct behavior
- Update p9_dump_pstate_table tool HWP (not consumed by FW).  However, it uses
  the update p9_pstates_pgpe.h,  Overlay structure compatible with back levels
  of p9_dump_pstate_table_wrap tool

Key_Cronus_Test=PM_REGRESS

Change-Id: I2d973fc28bbf645ae030015c609318cb7351d7ec
CQ: SW415420
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52931
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

1 files changed, 19 insertions, 3 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
index 36e0143d..ac4acbf9 100644
--- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
+++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c
@@ -94,9 +94,6 @@ void p9_pgpe_pstate_init()
         PK_TRACE_INF("Safe Frequency is NOT set.  Using POWERSAVE as Pstate as safe");
     }
 
-    PK_TRACE_INF("SafePstate=0x%x", G_pgpe_pstate_record.safePstate);
-    PK_TRACE_INF("SafeFrequency=0x%x,SafeVoltage=0x%x", G_gppb->safe_frequency_khz, G_gppb->safe_voltage_mv);
-
     for (q = 0; q < MAX_QUADS; q++)
     {
         G_pgpe_pstate_record.psClipMax[q] = G_pgpe_pstate_record.safePstate;
@@ -110,6 +107,8 @@ void p9_pgpe_pstate_init()
         G_pgpe_pstate_record.quadPSNext[q] = G_pgpe_pstate_record.safePstate;
         G_pgpe_pstate_record.globalPSNext  = G_pgpe_pstate_record.safePstate;
 
+        // Original behavior.  Can be removed once G_gppb->options.pad has
+        // good_cores_in_sort always filled in correctly.
         for (c = (q * CORES_PER_QUAD); c < (q + 1)*CORES_PER_QUAD; c++)
         {
             if (ccsr.value & CORE_MASK(c))
@@ -119,6 +118,23 @@ void p9_pgpe_pstate_init()
         }
     }
 
+    // CQ: SW415420
+    // Load the number of cores for this part.  Note: this is called
+    // "Configured Cores" but this is really not the actual case;  this
+    // is the originally good cores from the VPD for this sort to be
+    // used by the WOF algorithm to compute vratio.
+    //
+    // The following overlay is done so allow external tooling to use
+    // the earlier version of header (pre-adding the good_cores_in_sort
+    // field in the options.pad word).
+    GPPBOptionsPadUse pad;
+    pad = (GPPBOptionsPadUse)G_gppb->options.pad;
+
+    if (pad.fields.good_cores_in_sort)
+    {
+        G_pgpe_pstate_record.numConfCores = pad.fields.good_cores_in_sort;
+    }
+
     //Init OCC Shared SRAM
     G_pgpe_pstate_record.pQuadState0 = (quad_state0_t*)G_pgpe_header_data->g_quad_status_addr;
     G_pgpe_pstate_record.pQuadState1 = (quad_state1_t*)(G_pgpe_header_data->g_quad_status_addr + 2);