STOP: Remove sdisn dd1 workaround from dd2, add sync

Change-Id: I10076fbe888392d7495fa3088ce8cce8a2717ffd
Original-Change-Id: I1cd4a9ac567e723165cc4f709c23948b38d669aa
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43128
Reviewed-by: JAMES DEZELLE <jdezelle@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: BRIAN D. VICTOR <brian.d.victor1@ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

1 files changed, 12 insertions, 2 deletions

diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
index c0c6158d..82c4d95b 100755
--- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
+++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
@@ -722,6 +722,8 @@ p9_cme_stop_entry()
             PK_TRACE("Assert core chiplet fence via NET_CTRL0[18]");
             CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(18));
 
+            sync();
+
             PK_TRACE("Clear SCAN_REGION_TYPE prior to stop core clocks");
             CME_PUTSCOM(C_SCAN_REGION_TYPE, core, 0);
 
@@ -781,6 +783,8 @@ p9_cme_stop_entry()
             MARK_TRAP(SE_STOP_CORE_GRID)
             //==============================
 
+            sync();
+
             PK_TRACE("Drop clock sync enable before switch to refclk via CACCR[15]");
             CME_PUTSCOM(CPPM_CACCR_CLR, core, BIT64(15));
 
@@ -800,6 +804,8 @@ p9_cme_stop_entry()
             PK_TRACE("Assert skew sense to skewadjust fence via NET_CTRL0[22]");
             CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(22));
 
+            sync();
+
             PK_TRACE("Drop ABIST_SRAM_MODE_DC to support ABIST Recovery via BIST[1]");
             CME_GETSCOM(C_BIST, core, scom_data.value);
             scom_data.words.upper &= ~BIT32(1);
@@ -811,12 +817,16 @@ p9_cme_stop_entry()
             PK_TRACE("Assert regional fences via CPLT_CTRL1[4-13]");
             CME_PUTSCOM(C_CPLT_CTRL1_OR, core, BITS64(4, 11));
 
-            // Allow queued scoms to complete to Core EPS before switching to Core PPM
-            sync();
+#if NIMBUS_DD_LEVEL == 10
 
             PK_TRACE("Drop sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
             CME_PUTSCOM(C_CPLT_CONF0_CLEAR, core, BIT64(34));
 
+#endif
+
+            // Allow queued scoms to complete to Core EPS before switching to Core PPM
+            sync();
+
             PK_TRACE("Copy PECE CME sample to PPM Shadow via PECES");
 
             if (core & CME_MASK_C0)